From 0a76c24490ae09386911ae13b3f0752e5d9db8a1 Mon Sep 17 00:00:00 2001 From: Akilan Date: Sun, 19 Apr 2026 23:07:57 +0100 Subject: [PATCH] saving current changes --- .../CPrograms/Benchmarks/Richards/build.sh | 2 +- .../CPrograms/Benchmarks/Richards/richards.c | 20 +- .../isa/CPrograms/Benchmarks/barnes/barnes.c | 522 +- .../CPrograms/Benchmarks/barnes/barnes_hut.h | 92 - .../isa/CPrograms/Benchmarks/barnes/build.sh | 16 +- Tests/isa/CPrograms/Benchmarks/barnes/test | Bin 0 -> 16888 bytes Tests/isa/CPrograms/Benchmarks/barnes/test.c | 38 + Tests/isa/testC | Bin 9704 -> 10184 bytes .../test.txt | 167723 ++++++--------- 9 files changed, 69375 insertions(+), 99038 deletions(-) delete mode 100644 Tests/isa/CPrograms/Benchmarks/barnes/barnes_hut.h create mode 100755 Tests/isa/CPrograms/Benchmarks/barnes/test create mode 100644 Tests/isa/CPrograms/Benchmarks/barnes/test.c diff --git a/Tests/isa/CPrograms/Benchmarks/Richards/build.sh b/Tests/isa/CPrograms/Benchmarks/Richards/build.sh index 9e58987..e16a5ab 100644 --- a/Tests/isa/CPrograms/Benchmarks/Richards/build.sh +++ b/Tests/isa/CPrograms/Benchmarks/Richards/build.sh @@ -7,7 +7,7 @@ scp ../../link.ld home-1:/home/akilan/cheri/output/sdk/bin/ scp richards.c home-1:/home/akilan/cheri/output/sdk/bin/ # ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -Wl,-Ttext=0x80000000 -o testC start.S malloc.c memaccess.c' -ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -DDEFINE_MALLOC -DDEFINE_FREE -nostartfiles -fno-builtin-malloc -mcmodel=medany -T link.ld -o testC start.S richards.c malloc.c malloc_test.c' +ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -DDEFINE_MALLOC -DDEFINE_FREE --gcc-toolchain=/opt/riscv -nostartfiles -fno-builtin-malloc -mcmodel=medany -T link.ld -o testC start.S richards.c malloc.c malloc_test.c' # ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./llvm-objdump -d testC' diff --git a/Tests/isa/CPrograms/Benchmarks/Richards/richards.c b/Tests/isa/CPrograms/Benchmarks/Richards/richards.c index ed87346..616fcac 100644 --- a/Tests/isa/CPrograms/Benchmarks/Richards/richards.c +++ b/Tests/isa/CPrograms/Benchmarks/Richards/richards.c @@ -392,18 +392,18 @@ int bench() { createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0); - wkq = 0; - createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0); - createtask(I_DEVB, 5000, wkq, S_WAIT, devfn, 0, 0); + // wkq = 0; + // createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0); + // createtask(I_DEVB, 5000, wkq, S_WAIT, devfn, 0, 0); - tcb = tasklist; + // tcb = tasklist; - qpktcount = holdcount = 0; + // qpktcount = holdcount = 0; - // printf("Starting\n"); + // // printf("Starting\n"); - tracing = FALSE; - layout = 0; + // tracing = FALSE; + // layout = 0; schedule(); @@ -434,9 +434,9 @@ int inner_loop(int inner) { int main(int argc, char* argv[]) { //INITREGULARALLOC(); - int iterations = 100; + int iterations = 10; int warmup = 0; - int inner_iterations = 100; + int inner_iterations = 10; // parse_argv(argc, argv, &iterations, &warmup, &inner_iterations); diff --git a/Tests/isa/CPrograms/Benchmarks/barnes/barnes.c b/Tests/isa/CPrograms/Benchmarks/barnes/barnes.c index 87b9cc8..ee0ac7c 100644 --- a/Tests/isa/CPrograms/Benchmarks/barnes/barnes.c +++ b/Tests/isa/CPrograms/Benchmarks/barnes/barnes.c @@ -1,495 +1,77 @@ -/* - * File: barnes_hut.c - * -------------- - * Implements the Barnes Hut algorithm for n-body - * simulation with galaxy-like initial conditions. - * Uses OpenGl and GLUT for graphics. Written by: - * Joel Backsell, Kim Torberntsson & Alexander Bilock. - * Source: https://github.com/KimTorberntsson/Barnes-Hut/blob/master/barnes_hut.c - */ +/* The Computer Language Benchmarks Game + * https://salsa.debian.org/benchmarksgame-team/benchmarksgame/ + * + * Contributed by Mr Ledrug + * https://github.com/dstogov/c-benchmarks + * spectral-norm + * Algorithm lifted from Intel Fortran #2 code by Steve Decker et al. +*/ -// #include -// #include // #include // #include -// #include -// #include - -#include #include #include -#include "barnes_hut.h" -// #include "graphics.h" +void* tiny_malloc(size_t); +void tiny_free(void*); -// void free(void *ptr); -// void *malloc(size_t size); - -void free(void * __capability ptr); -void * __capability malloc(size_t size); - -//Some constants and global variables -int N = 10; -const double L = 1, W = 1, dt = 1e-3, alpha = 0.25, V = 50, epsilon = 1e-1, grav = 0.04; //grav should be 100/N -double __capability *x; -double __capability *y; -double __capability *u; -double __capability *v; -double __capability *force_x; -double __capability *force_y; -double __capability *mass; -struct node_t __capability *root; - -// -------- Modified by Akilan ---------- - -double my_sqrt(double x) { - if (x <= 0) return 0; - - double guess = x; - for (int i = 0; i < 10; i++) { - guess = 0.5 * (guess + x / guess); - } - return guess; +static inline int A(int i, int j) { + return ((i+j) * (i+j+1) / 2 + i + 1); } -#define PI 3.141592653589793 - -double wrap_angle(double x) { - while (x > PI) x -= 2*PI; - while (x < -PI) x += 2*PI; - return x; +double dot(double * v, double * u, int n) { + int i; + double sum = 0; + for (i = 0; i < n; i++) + sum += v[i] * u[i]; + return sum; } -double my_sin(double x) { - x = wrap_angle(x); +void mult_Av(double * v, double * out, int n) { + int i, j; + double sum; - double x2 = x * x; - return x - - (x * x2) / 6 - + (x * x2 * x2) / 120 - - (x * x2 * x2 * x2) / 5040; + for (i = 0; i < n; i++) { + for (sum = j = 0; j < n; j++) + sum += v[j] / A(i,j); + out[i] = sum; + } } -double my_cos(double x) { - x = wrap_angle(x); +void mult_Atv(double * v, double * out,int n) { + int i, j; + double sum; - double x2 = x * x; - return 1 - - x2 / 2 - + (x2 * x2) / 24 - - (x2 * x2 * x2) / 720; + for (i = 0; i < n; i++) { + for (sum = j = 0; j < n; j++) + sum += v[j] / A(j,i); + out[i] = sum; + } } -// -------------------------------------- - -// -------- Modified by Akilan ---------- - -static unsigned int seed = 123456789; // must be initialized somehow - -unsigned int rand_test(void) -{ - seed = (1103515245 * seed + 12345); - return (seed >> 16) & 0x7FFF; // 15-bit result +double *tmp; +void mult_AtAv(double *v, double *out,int n) { + //mult_Av(v, tmp, n); + mult_Atv(tmp, out, n); } -// --------------------------------------- - -/* - * Function for producing a random number between two double values - */ -double frand(double xmin, double xmax) { - return xmin + (xmax-xmin)*rand_test()/32767; -} - -/* - * Prints the time between two clocks in seconds - */ -// void print_time(clock_t s, clock_t e) -// { -// printf("Time: %f seconds\n", (double)(e-s)/CLOCKS_PER_SEC); -// } - -/* - * This function is called every time GLUT refreshes the display. - */ -// void display(void) { -// //Do a time step -// time_step(); - -// //Draw points -// drawPoints(x, y, N); -// } - -/* - * Updates the positions of the particles of a time step. - */ -void time_step(void) { - //Allocate memory for root - root = malloc(sizeof(struct node_t)); - set_node(root); - root->min_x = 0; root->max_x = 1; root->min_y = 0; root->max_y = 1; - - //Put particles in tree - for(int i = 0; i < N; i++) { - put_particle_in_tree(i, root); - } - - //Calculate mass and center of mass - calculate_mass(root); - calculate_center_of_mass_x(root); - calculate_center_of_mass_y(root); - - //Calculate forces - update_forces(); - - //Update velocities and positions - for(int i = 0; i < N; i++) { - double ax = force_x[i]/mass[i]; - double ay = force_y[i]/mass[i]; - u[i] += ax*dt; - v[i] += ay*dt; - x[i] += u[i]*dt; - y[i] += v[i]*dt; - - /* This of course doesn't make any sense physically, - * but makes sure that the particles stay within the - * bounds. Normally the particles won't leave the - * area anyway. - */ - bounce(&x[i], &y[i], &u[i], &v[i]); - } - - //Free memory - free_node(root); - free(root); -} - -/* - * If a particle moves beyond any of the boundaries then bounce it back - */ -void bounce(double __capability *x, double __capability *y, double __capability *u, double __capability *v) { - double W = 1.0f, H = 1.0f; - if(*x > W) { - *x = 2*W - *x; - *u = -*u; - } - - if(*x < 0) { - *x = -*x; - *u = -*u; - } - - if(*y > H) { - *y = 2*H - *y; - *v = -*v; - } - - if(*y < 0) { - *y = -*y; - *v = -*v; - } -} - -/* - * Puts a particle recursively in the Barnes Hut quad-tree. - */ -void put_particle_in_tree(int new_particle, struct node_t __capability *node) { - //If no particle is assigned to the node - if(!node->has_particle) { - node->particle = new_particle; - node->has_particle = 1; - } - //If the node has no children - else if(!node->has_children) { - //Allocate and initiate children - node->children = malloc(4*sizeof(struct node_t)); - for(int i = 0; i < 4; i++) { - set_node(&node->children[i]); - } - - //Set boundaries for the children - node->children[0].min_x = node->min_x; node->children[0].max_x = (node->min_x + node->max_x)/2; - node->children[0].min_y = node->min_y; node->children[0].max_y = (node->min_y + node->max_y)/2; - - node->children[1].min_x = (node->min_x + node->max_x)/2; node->children[1].max_x = node->max_x; - node->children[1].min_y = node->min_y; node->children[1].max_y = (node->min_y + node->max_y)/2; - - node->children[2].min_x = node->min_x; node->children[2].max_x = (node->min_x + node->max_x)/2; - node->children[2].min_y = (node->min_y + node->max_y)/2; node->children[2].max_y = node->max_y; - - node->children[3].min_x = (node->min_x + node->max_x)/2; node->children[3].max_x = node->max_x; - node->children[3].min_y = (node->min_y + node->max_y)/2; node->children[3].max_y = node->max_y; - - //Put old particle into the appropriate child - place_particle(node->particle, node); - - //Put new particle into the appropriate child - place_particle(new_particle, node); - - //It now has children - node->has_children = 1; - } - //Add the new particle to the appropriate children - else { - //Put new particle into the appropriate child - place_particle(new_particle, node); - } -} - - -/* - * Puts a particle in the right child of a node with children. - */ -void place_particle(int particle, struct node_t __capability *node) { - if(x[particle] <= (node->min_x + node->max_x)/2 && y[particle] <= (node->min_y + node->max_y)/2) { - put_particle_in_tree(particle, &node->children[0]); - } else if(x[particle] > (node->min_x + node->max_x)/2 && y[particle] < (node->min_y + node->max_y)/2) { - put_particle_in_tree(particle, &node->children[1]); - } else if(x[particle] < (node->min_x + node->max_x)/2 && y[particle] > (node->min_y + node->max_y)/2) { - put_particle_in_tree(particle, &node->children[2]); - } else { - put_particle_in_tree(particle, &node->children[3]); - } -} - -/* - * Sets initial values for a new node - */ -void set_node(struct node_t __capability *node) { - node->has_particle = 0; - node->has_children = 0; -} - -/* - * Frees memory for a node and its children recursively. - */ -void free_node(struct node_t __capability *node){ - if(node->has_children){ - free_node(&node->children[0]); - free_node(&node->children[1]); - free_node(&node->children[2]); - free_node(&node->children[3]); - free(node->children); - } -} - -/* - * Displays the boundaries of the tree using OpenGL and GLUT. - * Used for debugging purposes. - */ -// void display_tree(struct node_t *node) { -// drawRect(node->min_x, node->max_x, node->min_y, node->max_y); -// if(node->has_children == 1) { -// for(int i = 0; i < 4; i++) { -// display_tree(&node->children[i]); -// } -// } -// } - -/* - * Calculates the total mass for the node. It recursively updates the mass - * of itself and all of its children. - */ -double calculate_mass(struct node_t __capability *node) { - if(!node->has_particle) { - node->total_mass = 0; - } else if(!node->has_children) { - node->total_mass = mass[node->particle]; - } else { - node->total_mass = 0; - for(int i = 0; i < 4; i++) { - node->total_mass += calculate_mass(&node->children[i]); - } - } - return node->total_mass; -} - -/* - * Calculates the x-position of the centre of mass for the - * node. It recursively updates the position of itself and - * all of its children. - */ -double calculate_center_of_mass_x(struct node_t __capability *node) { - if(!node->has_children) { - node->c_x = x[node->particle]; - } else { - node->c_x = 0; - double m_tot = 0; - for(int i = 0; i < 4; i++) { - if(node->children[i].has_particle) { - node->c_x += node->children[i].total_mass*calculate_center_of_mass_x(&node->children[i]); - m_tot += node->children[i].total_mass; - } - } - node->c_x /= m_tot; - } - return node->c_x; -} - -/* - * Calculates the y-position of the centre of mass for the - * node. It recursively updates the position of itself and - * all of its children. - */ -double calculate_center_of_mass_y(struct node_t __capability *node) { - if(!node->has_children) { - node->c_y = y[node->particle]; - } else { - node->c_y = 0; - double m_tot = 0; - for(int i = 0; i < 4; i++) { - if(node->children[i].has_particle) { - node->c_y += node->children[i].total_mass*calculate_center_of_mass_y(&node->children[i]); - m_tot += node->children[i].total_mass; - } - } - node->c_y /= m_tot; - } - return node->c_y; -} - -/* - * Calculates the forces in a time step of all particles in - * the simulation using the Barnes Hut quad tree. - */ -void update_forces(){ - for(int i = 0; i < N; i++) { - force_x[i] = 0; - force_y[i] = 0; - update_forces_help(i, root); - } -} - -/* - * Help function for calculating the forces recursively - * using the Barnes Hut quad tree. - */ -void update_forces_help(int particle, struct node_t __capability *node) { - //The node is a leaf node with a particle and not the particle itself - if(!node->has_children && node->has_particle && node->particle != particle) { - double r = my_sqrt((x[particle] - node->c_x)*(x[particle] - node->c_x) + (y[particle] - node->c_y)*(y[particle] - node->c_y)); - calculate_force(particle, node, r); - } - //The node has children - else if(node->has_children) { - //Calculate r and theta - double r = my_sqrt((x[particle] - node->c_x)*(x[particle] - node->c_x) + (y[particle] - node->c_y)*(y[particle] - node->c_y)); - double theta = (node->max_x - node->min_x)/r; - - /* If the distance to the node's centre of mass is far enough, calculate the force, - * otherwise traverse further down the tree - */ - if(theta < 0.5){ - calculate_force(particle, node, r); - } else { - update_forces_help(particle, &node->children[0]); - update_forces_help(particle, &node->children[1]); - update_forces_help(particle, &node->children[2]); - update_forces_help(particle, &node->children[3]); - } - } -} - -/* - * Calculates and updates the force of a particle from a node. - */ -void calculate_force(int particle, struct node_t __capability *node, double r){ - double temp = -grav*mass[particle]*node->total_mass/((r + epsilon)*(r + epsilon)*(r + epsilon)); - force_x[particle] += (x[particle] - node->c_x)*temp; - force_y[particle] += (y[particle] - node->c_y)*temp; -} - -/* - * Main function. - */ int main(void) { + int n = 1; +// if (n <= 0) n = 2000; - //The first arguments sets if the graphics should be used - // int graphics = 1; - // if (argc > 1) { - // graphics = atoi(argv[1]); - // } + double *u, *v; + u = tiny_malloc(n * sizeof(double)); + v = tiny_malloc(n * sizeof(double)); + tmp = tiny_malloc(n * sizeof(double)); - //The second argument sets the number of time steps - // int time_steps = 1; - // if (argc > 2) { - // time_steps = atoi(argv[2]); - // } + int i; + for (i = 0; i < n; i++) u[i] = 1; + for (i = 0; i < 10; i++) { + mult_AtAv(u, v, n); + mult_AtAv(v, u, n); + } - //Initiate memory for the vectors - // x = (double __capability *)malloc(N*sizeof(double)); - // y = (double __capability *)malloc(N*sizeof(double)); - // u = (double __capability *)malloc(N*sizeof(double)); - // v = (double __capability *)malloc(N*sizeof(double)); - // // -------- Modified by Akilan ---------- - // force_x = (double __capability *)malloc(N*sizeof(double)); - // force_y = (double __capability *)malloc(N*sizeof(double)); - // // -------------------------------------- - // mass = (double __capability *)malloc(N*sizeof(double)); +// printf("%.9f\n", sqrt(dot(u,v, n) / dot(v,v,n))); - //Set the initial values - // for(int i = 0; i < N; i++) { - // mass[i] = 1; - // double R = frand(0, L/4); - // double theta = frand(0, 2*M_PI); - // x[i] = L/2 + R*my_cos(theta); - // y[i] = W/2 + alpha*R*my_sin(theta); - // double R_prim = my_sqrt(pow(x[i] - L/2, 2) + pow(y[i] - W/2, 2)); - // u[i] = -V*R_prim*my_sin(theta); - // v[i] = V*R_prim*my_cos(theta); - // } - // for (int i = 0; i < N; i++) { - // mass[i] = 1; - - // double R = frand(0, L/4); - // double theta = frand(0, 2*PI); - - // double c = my_cos(theta); - // double s = my_sin(theta); - - // x[i] = L/2 + R * c; - // y[i] = W/2 + alpha * R * s; - - // double dx = x[i] - L/2; - // double dy = y[i] - W/2; - - // double R_prim = my_sqrt(dx*dx + dy*dy); - - // u[i] = -V * R_prim * s; - // v[i] = V * R_prim * c; - // } - - /* Run the GLUT display function if the graphics mode is on. - * Otherwise just run the simulations without graphics - */ - // if (graphics) { - // // Initialize the graphics routines - // graphicsInit(&argc, argv, display); - - // //Used for the display window - // glutMainLoop(); - // } else { - //Begin taking time - // long start = clock(); - - //The main loop - // for(int i = 0; i < time_steps; i++) { - // time_step(); - // } - - //Stop taking time and print elapsed time - // long stop = clock(); - // print_time(start, stop); - // } - - //Free memory - // free(x); - // free(y); - // free(u); - // free(v); - // free(force_x); - // free(force_y); - // free(mass); - - return 0; + return 0; } \ No newline at end of file diff --git a/Tests/isa/CPrograms/Benchmarks/barnes/barnes_hut.h b/Tests/isa/CPrograms/Benchmarks/barnes/barnes_hut.h deleted file mode 100644 index 64f19b2..0000000 --- a/Tests/isa/CPrograms/Benchmarks/barnes/barnes_hut.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * File: barnes_hut.h - * -------------- - * Header file for barnes_hut.c - * Written by: - * Joel Backsell, Kim Torberntsson & Alexander Bilock. - */ - -#ifndef Barnes_Hut_barnes_hut_h -#define Barnes_Hut_barnes_hut_h - -/* - * Struct that represents a node of the Barnes Hut quad tree. - */ -struct node_t { - int particle; - int has_particle; - int has_children; - double min_x, max_x, min_y, max_y, total_mass, c_x, c_y; - - struct node_t __capability *children; -}; - -//Function for producing a random number between two double values. -double frand(double xmin, double xmax); - -//Prints the time between two clocks in seconds -// void print_time(clock_t s, clock_t e); - -//OpenGL method for displaying the particles -// void display(void); - -//Calculates the positions of a time step -// void time_step(void); - -//If a particle moves beyond any of the boundaries then bounce it back -// void bounce(double *x, double *y, double *u, double *v); - -// //Functions for handling the placement of particles in the tree -// void put_particle_in_tree(int new_particle, struct node_t *node); -// void place_particle(int particle, struct node_t *node); -// void set_node(struct node_t *node); -// void free_node(struct node_t *node); -// void display_tree(struct node_t *node); - -// //Functions for calculating the mass and centre of mass of the tree -// double calculate_mass(struct node_t *node); -// double calculate_center_of_mass_x(struct node_t *node); -// double calculate_center_of_mass_y(struct node_t *node); - -// //Functions for the force calculations -// void update_forces(); -// void update_forces_help(int particle, struct node_t *node); -// void calculate_force(int particle, struct node_t *node, double r); - -void bounce(double __capability *x, - double __capability *y, - double __capability *u, - double __capability *v); - -/* Tree functions */ -void put_particle_in_tree(int new_particle, - struct node_t __capability *node); - -void place_particle(int particle, - struct node_t __capability *node); - -void set_node(struct node_t __capability *node); - -void free_node(struct node_t __capability *node); - -void display_tree(struct node_t __capability *node); - -/* Mass / COM */ -double calculate_mass(struct node_t __capability *node); - -double calculate_center_of_mass_x(struct node_t __capability *node); - -double calculate_center_of_mass_y(struct node_t __capability *node); - -/* Forces */ -void update_forces(void); - -void update_forces_help(int particle, - struct node_t __capability *node); - -void calculate_force(int particle, - struct node_t __capability *node, - double r); - - -#endif \ No newline at end of file diff --git a/Tests/isa/CPrograms/Benchmarks/barnes/build.sh b/Tests/isa/CPrograms/Benchmarks/barnes/build.sh index d2dcb1b..787d192 100644 --- a/Tests/isa/CPrograms/Benchmarks/barnes/build.sh +++ b/Tests/isa/CPrograms/Benchmarks/barnes/build.sh @@ -1,14 +1,16 @@ -scp ../../start.S home-1:/home/akilan/cheri/output/sdk/bin/ -# scp main.c home-1:/home/akilan/cheri/output/sdk/bin/ -scp ../../malloc.c home-1:/home/akilan/cheri/output/sdk/bin/ -scp ../../malloc_test.c home-1:/home/akilan/cheri/output/sdk/bin/ -scp ../../link.ld home-1:/home/akilan/cheri/output/sdk/bin/ +# scp ../../start.S home-1:/home/akilan/cheri/output/sdk/bin/ +# # scp main.c home-1:/home/akilan/cheri/output/sdk/bin/ +# scp ../../malloc.c home-1:/home/akilan/cheri/output/sdk/bin/ +# scp ../../malloc_test.c home-1:/home/akilan/cheri/output/sdk/bin/ +# scp ../../link.ld home-1:/home/akilan/cheri/output/sdk/bin/ scp barnes.c home-1:/home/akilan/cheri/output/sdk/bin/ -scp barnes_hut.h home-1:/home/akilan/cheri/output/sdk/bin/ +# scp barnes_hut.h home-1:/home/akilan/cheri/output/sdk/bin/ + +scp test.c home-1:/home/akilan/cheri/output/sdk/bin/ # ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -Wl,-Ttext=0x80000000 -o testC start.S malloc.c memaccess.c' -ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -DDEFINE_MALLOC -DDEFINE_FREE -nostdlib -nostartfiles -fno-builtin-malloc -mcmodel=medany -T link.ld -o testC start.S barnes.c malloc.c malloc_test.c' +ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=lp64d -DDEFINE_MALLOC -DDEFINE_FREE -nostdlib -nostartfiles -fno-builtin-malloc --gcc-toolchain=/opt/riscv -mcmodel=medany -T link.ld -o testC start.S barnes.c malloc.c malloc_test.c' # ssh home-1 'cd /home/akilan/cheri/output/sdk/bin/ && ./llvm-objdump -d testC' diff --git a/Tests/isa/CPrograms/Benchmarks/barnes/test b/Tests/isa/CPrograms/Benchmarks/barnes/test new file mode 100755 index 0000000000000000000000000000000000000000..a23b6cf374c70572b44b0e0d3980ff4c44863a9c GIT binary patch literal 16888 zcmeI4T}YE*6vv-;TlulQtxWoGMI$JzOv56&31%f_pRyz*h^Nd+YfiyU(roooMwHzY zgb@|p*@rhc^s@A-J%=RD{6ZM!@U zjDG&^5<(LY8+0l(3Fo-*!V_XPbOTh%>WcN1J1hO$D4Q*6b9U;Ni0UMvQr1+~)?_cM z{l4s+u;NKblTvRaQbq%9QPVf$?0Us^^D_6WS13;JRVjxstR-cnY;8IaY^s;RriNx@ zCieHis<+$PL~&LKWzv`+drG6kEwP<%&3S!<-FtT9+uR^Q%OkC?;*r9LjS zd|NVo{)$j%&&n@n&nHflBj<&hcXGokQoicL@x-wh8FfEc67+6Ro!$wJ(z$ehS~IzC z#@9g`?*;vAZ;wO+;nFpw=qp%<7aBl;dbo_BXQ{5PpochWAd59Xjhr|28&sJMpr)jqo39P3h@qPzio80Vco%m;e)C0!)AjFaajO1egF5U;<2l2`~XBzyz28 z6JP>NfC(@GCcp%k025#WOn?b60Vco%m;e)C0!)AjFaajO1egF5U;<2l2`~XBzyz28 z6JP>NfC(@GCh*?~cu{GYrBpO?9D2eyHZ7Z?NwI)D8VRL)+b&ISEdQ87emCz|(WfZaC?=elI5U zf2}FQbgT@U=c2?<8GY~S$Bm{Tq0WOXM2?Of6E=)5+tdwqA+CjzV7}Zp=(VYlcQf1<2%}+lz z^gCY1<00F&+DWNHcMcsq{`P*?hLa^d|GK_>X;;OX@^=sF65T^XtD7%<>L} +#include + +// double PI = 3.141592653589793; + +// double wrap_angle(double x) { +// while (x > PI) x -= 2*PI; +// while (x < -PI) x += 2*PI; +// return x; +// } + +// double my_sin(double x) { +// x = wrap_angle(x); + +// double x2 = x * x; +// return x +// - (x * x2) / 6 +// + (x * x2 * x2) / 120 +// - (x * x2 * x2 * x2) / 5040; +// } + +int my_cos(int x) { + x *= x; + return 1 - x/2 * (1 - x/12 * (1 - x/30 * (1 - x/56 * (1 - x/90)))); +} + +int main(void) { +// const double PI = 3.141592653589793; + +int x = my_cos(3); + +// printf("%f\n", cos(3)); +// printf("%f\n", cos(-3)); +// printf("%f\n", cos(0)); +// printf("%f\n", cos(PI)); +// printf("%f\n", cos(PI / 2.0)); + return 0; +} \ No newline at end of file diff --git a/Tests/isa/testC b/Tests/isa/testC index c755c91314aafe60520a850254a997168e27fd29..46e9c88c1dfdeaafbe5afff71d0dcc81cef2486c 100755 GIT binary patch literal 10184 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'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffb0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000048, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000040, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff70 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000088, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000080, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 13430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000088, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000048, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 13440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000048, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff8 After delta: vaddr = 0x80000ff8 - 13440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000080, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000040, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 4c <= 00000000200003dc000000001fffff44000000 - 13450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 4c <= 00000000200003ec000000001fffff44000000 + 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000048, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 13450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000040, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff0 After delta: vaddr = 0x80000ff0 - 13450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 12660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 - 13460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 13460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000040, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 13460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 12670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:12 PC:0x1ffff0000000000000000000080001096 instr:0x0000715d iType:Alu [doCommitNormalInst [0]] 1267 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff52 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 12680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fec After delta: vaddr = 0x80000fec - 13460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd4, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:12 PC:0x1ffff00000000000000000000800004e6 instr:0x00007175 iType:Alu [doCommitNormalInst [0]] 1346 + 12680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:13 PC:0x1ffff0000000000000000000080001098 instr:0x0000e486 iType:St [doCommitNormalInst [0]] 1268 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 - 13470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } - 13470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 0: r 53 <= 0000000000000000c00000001fffff44000000 + 12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9098 } + 12690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 13470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd4, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd4 -After delta: vaddr = 0x80000fd4 - 13470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:13 PC:0x1ffff00000000000000000000800004e8 instr:0x0000e506 iType:St [doCommitNormalInst [0]] 1347 +Before delta: vaddr = 0x80000fe8 +After delta: vaddr = 0x80000fe8 + 12690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } +instret:14 PC:0x1ffff000000000000000000008000109a instr:0x0000e0a2 iType:St [doCommitNormalInst [0]] 1269 +instret:15 PC:0x1ffff000000000000000000008000109c instr:0x00000880 iType:Alu [doCommitNormalInst [1]] 1269 calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000001000000001fffff44000000 - 13480 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84e8 } - 13480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd4, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd4 o: 'h0000000080000fd4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd4, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 55 <= 000000002000082b800000001fffff44000000 + 12700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } + 12700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 13480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } + 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 12700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 13480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } -instret:14 PC:0x1ffff00000000000000000000800004ea instr:0x0000e122 iType:St [doCommitNormalInst [0]] 1348 -instret:15 PC:0x1ffff00000000000000000000800004ec instr:0x00000900 iType:Alu [doCommitNormalInst [1]] 1348 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 12700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:16 PC:0x1ffff000000000000000000008000109e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 +instret:17 PC:0x1ffff00000000000000000000800010a0 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 1270 calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000004000000001fffff44000000 - 13490 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd4 o: 'h0000000080000fd4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd4, check_high: 'h00000000080000fd8, check_inclusive: True } }, specBits: 'h000 } - 13490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 56 <= 0000000020000800000000001fffff44000000 + 12710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe8, check_high: 'h00000000080000fec, check_inclusive: True } }, specBits: 'h000 } + 12710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } - 13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:16 PC:0x1ffff00000000000000000000800004ee instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1349 -instret:17 PC:0x1ffff00000000000000000000800004f0 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1349 + 12710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +instret:18 PC:0x1ffff00000000000000000000800010a4 instr:0xfea42623 iType:St [doCommitNormalInst [0]] 1271 +instret:19 PC:0x1ffff00000000000000000000800010a8 instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1271 calling cycle - 13500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fd4, check_inclusive: True } }, specBits: 'h000 } -instret:18 PC:0x1ffff00000000000000000000800004f4 instr:0x00004511 iType:Alu [doCommitNormalInst [0]] 1350 -instret:19 PC:0x1ffff00000000000000000000800004f6 instr:0xfca42a23 iType:St [doCommitNormalInst [1]] 1350 + 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 12720 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 12720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:20 PC:0x1ffff00000000000000000000800010aa instr:0xfea42423 iType:St [doCommitNormalInst [0]] 1272 +instret:21 PC:0x1ffff00000000000000000000800010ae instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1272 calling cycle - 13510 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -instret:20 PC:0x1ffff00000000000000000000800004fa instr:0x00004541 iType:Alu [doCommitNormalInst [0]] 1351 -instret:21 PC:0x1ffff00000000000000000000800004fc instr:0xfca42823 iType:St [doCommitNormalInst [1]] 1351 + 12730 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 12730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 12730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } +instret:22 PC:0x1ffff00000000000000000000800010b2 instr:0xf5250513 iType:Alu [doCommitNormalInst [0]] 1273 +instret:23 PC:0x1ffff00000000000000000000800010b6 instr:0xfaa43c23 iType:St [doCommitNormalInst [1]] 1273 +calling cycle + 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } + 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 12760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h1a, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002da }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +[RFile] wr_ 1: r 5a <= 000000002000042f800000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5b <= 0000000020000431800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; calling cycle calling cycle calling cycle @@ -1563,11285 +1580,8979 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 13980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000600 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 13990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14270 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h909a } + 14290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } +calling cycle + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90a0 } + 14310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } +calling cycle + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90a4 } + 14330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } +calling cycle + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90aa } + 14350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } +calling cycle + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90b6 } + 14370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } +calling cycle + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } + 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 14400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 14790 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002000, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } + 14800 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 14810 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:24 PC:0x1ffff00000000000000000000800010ba instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 1483 +calling cycle +[RFile] wr_ 0: r 59 <= 0000000000000006000000001fffff44000000 +calling cycle +instret:25 PC:0x1ffff00000000000000000000800010bc instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 1485 +instret:26 PC:0x1ffff00000000000000000000800010be instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1485 +calling cycle +instret:27 PC:0x1ffff00000000000000000000800010c2 instr:0x2da080e7 iType:Jr [doCommitNormalInst [0]] 1486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 15160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 00000000200003d4000000001fffff44000000 + 15170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010c6 o: 'h00000000800010c6 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1d6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 00000000200003ec000000001fffff44000000 + 15180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 15180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 15180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:28 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1518 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15190 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:29 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1519 +calling cycle +[RFile] wr_ 0: r 62 <= 0000000000000001c00000001fffff44000000 + 15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 15200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:30 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1520 +instret:31 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1520 +calling cycle + 15210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 15210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:32 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1521 +calling cycle + 15220 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:33 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 1524 +instret:34 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 1524 +calling cycle +calling cycle +instret:35 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1526 +instret:36 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 1526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 15410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 15430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +calling cycle + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 15450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +calling cycle + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 15470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +calling cycle + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 15800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 0000000000000000000000001fffff44000000 + 15810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 15810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } + 15820 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 15830 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 + 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 15850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:37 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1585 +instret:38 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 1585 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1fa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 + 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 70 <= 0000000020040814000000001fffff44000000 + 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 15870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:39 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 1587 +calling cycle + 15880 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 69 <= 0000000000000006000000001fffff44000000 + 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 +instret:40 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [0]] 1588 +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000008000000001fffff44000000 + 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:41 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1589 +calling cycle + 15900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 15900 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000020040814000000001fffff44000000 + 15900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:42 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1590 +calling cycle + 15910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 +instret:43 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 1591 +instret:44 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1591 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 15920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +calling cycle + 15930 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 15930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 15930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +calling cycle + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 15960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080102050, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16650 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 16660 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +calling cycle + 16670 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 3f810d60ffb10940cfe000001fffff44000000 + 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 16680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +calling cycle + 16690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfe043583fec42503 o: 'hfe043583fec42503 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 17290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080102050, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 17300 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 17310 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 18360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1fa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 00000000200408f7800000001fffff44000000 + 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 18370 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 18370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 0000000020040814000000001fffff44000000 + 18380 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 18380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 18380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 18400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:45 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 1840 +calling cycle +[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 + 18410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 18410 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000020040814000000001fffff44000000 + 18410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 000000002000094d000000001fffff44000000 + 18420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 18420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:46 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1842 +instret:47 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 1842 +calling cycle +[RFile] wr_ 0: r 79 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 18430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 18430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:48 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 1843 +instret:49 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1843 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18440 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 18440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:50 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 1844 +calling cycle + 18450 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 18450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 18450 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:51 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1845 +calling cycle + 18460 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 + 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 18460 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18470 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000804000000001fffff44000000 + 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:52 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1848 +calling cycle +calling cycle +[RFile] wr_ 1: r 7b <= 3ffffffffffffbe80fff00001fffff44000000 +instret:53 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 1850 +instret:54 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 1850 +calling cycle +instret:55 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 1851 +instret:56 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 1851 +calling cycle +instret:57 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 1852 +instret:58 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 1852 +calling cycle +instret:59 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 1853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 18930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +calling cycle +[RFile] wr_ 1: r 7c <= 3ffffffffffffbe00fff00001fffff44000000 + 18940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 18940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } +calling cycle + 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 18950 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:60 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [0]] 1895 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18960 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:61 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1898 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 18990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 18990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000020000802000000001fffff44000000 + 19000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 19000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:62 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 1900 +instret:63 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [1]] 1900 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19010 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 19010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:64 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [0]] 1901 +instret:65 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [1]] 1901 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19020 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 19020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 19020 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19030 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000804000000001fffff44000000 + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 19030 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 19030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19040 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000804000000001fffff44000000 + 19040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 19040 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 19050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19050 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000000000008000000001fffff44000000 + 19050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 19050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:66 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1905 +calling cycle + 19060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 19060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 19060 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 19070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 19070 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000008000000001fffff44000000 + 19070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 +instret:67 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 1907 +calling cycle +[RFile] wr_ 1: r 43 <= 000000002000080c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 19080 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 0000000020000804000000001fffff44000000 + 19080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19090 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:68 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1909 +calling cycle +instret:69 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 1910 +instret:70 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 1910 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:71 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1911 +instret:72 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1911 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 19120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:73 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 1912 +calling cycle + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:74 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 1913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002010 +After delta: vaddr = 0x80002010 + 19520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002010, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19540 : [doFinishMem] DTlbResp { resp: <'h0000000080002010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002010, check_high: 'h00000000080002018, check_inclusive: True } }, specBits: 'h000 } + 19540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 19550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 19550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } +instret:75 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1955 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002010, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 19560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } + 19560 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 19560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19570 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000020000804000000001fffff44000000 + 19570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 19570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19580 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 19580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 19580 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 0: r 50 <= 00000000200003ec000000001fffff44000000 + 19590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 19590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19590 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 196b3f810d60ffb1065a00001fffff44000000 + 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 19590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 19590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:76 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 1959 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 0000000020000806000000001fffff44000000 + 19600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000020000431800000001fffff44000000 + 19600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002018 o: 'h0000000080002018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 19600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff74 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 19610 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 + 19610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:77 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1961 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 19620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 +instret:78 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1962 +instret:79 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 1962 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 196b3f810d60ffb1065a00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 19630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 19630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020040833000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 19640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90c8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102040 +After delta: vaddr = 0x80102040 + 19640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } +calling cycle +calling cycle + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } + 19660 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 19670 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 20230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 20240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 20250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 20250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 20260 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 20260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 20260 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 50 <= 00000000200003ec000000001fffff44000000 + 20270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 20270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20270 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000806000000001fffff44000000 + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 20270 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20280 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000020000431800000001fffff44000000 + 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 20280 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff60 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20290 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 + 20290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:80 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2029 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 +instret:81 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2030 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000806000000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800010c6; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 20310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:82 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2031 +instret:83 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2031 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:84 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2033 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff74 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000806000000001fffff44000000 + 20400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 20400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90c8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020040833000000001fffff44000000 + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } + 20410 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } + 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102040 +After delta: vaddr = 0x80102040 +instret:85 PC:0x1ffff00000000000000000000800010c6 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2041 +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020040810000000001fffff44000000 + 20420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 0000000020000800000000001fffff44000000 + 20420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002018 o: 'h0000000080002018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102040, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20430 : [doFinishMem] DTlbResp { resp: <'h0000000080102040,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102040, check_high: 'h00000000080102048, check_inclusive: True } }, specBits: 'h000 } + 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 4c <= 0000000020000436800000001fffff44000000 + 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:86 PC:0x1ffff00000000000000000000800010c8 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2044 +instret:87 PC:0x1ffff00000000000000000000800010cc instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2044 +calling cycle +[RFile] wr_ 0: r 5d <= 0000000020000438800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 20450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } +instret:88 PC:0x1ffff00000000000000000000800010d0 instr:0xf7460613 iType:Alu [doCommitNormalInst [0]] 2045 +instret:89 PC:0x1ffff00000000000000000000800010d4 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2045 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102040, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90d4 } + 20460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } + 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } + 20470 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 20480 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 + 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } + 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:90 PC:0x1ffff00000000000000000000800010d6 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2050 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5a <= 0000000000000006000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:91 PC:0x1ffff00000000000000000000800010d8 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2052 +instret:92 PC:0x1ffff00000000000000000000800010da instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2052 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 20530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:93 PC:0x1ffff00000000000000000000800010de instr:0x2be080e7 iType:Jr [doCommitNormalInst [0]] 2053 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 00000000200003d4000000001fffff44000000 + 20540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010e2 o: 'h00000000800010e2 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 20540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 00000000200003ec000000001fffff44000000 + 20550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 20550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 20550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:94 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2055 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20560 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 20560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 20560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:95 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2056 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000000000001c00000001fffff44000000 + 20570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 20570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 20570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +instret:96 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2057 +instret:97 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2057 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 20580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 20580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:98 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2058 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 20590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20590 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 + 20590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20600 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000006000000001fffff44000000 + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 20610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +instret:99 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2061 +instret:100 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2061 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 3ffffffffffffffa0fff00001fffff44000000 + 20630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 20630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:101 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2063 +instret:102 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2063 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000000000000000001fffff44000000 + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 20640 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:103 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2064 +instret:104 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2064 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 6b <= 0000000000000006000000001fffff44000000 + 20650 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 20650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 20650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:105 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2065 +instret:106 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2065 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 0000000020040814000000001fffff44000000 + 20660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 20660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:107 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2066 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 20670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 20670 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:108 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2067 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 00000000200003ec000000001fffff44000000 + 20680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 20680 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000020040814000000001fffff44000000 + 20680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:109 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2068 +instret:110 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2068 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 20690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 20690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 20690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 0000000020000802000000001fffff44000000 + 20700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 20700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20710 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 20710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 20720 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 20720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 20720 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 20730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 20730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20730 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 20730 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 20730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20740 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000080c000000001fffff44000000 + 20740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 20740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20750 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 20750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20750 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 20750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20760 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 20760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 20760 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 3ffffffffffffbe00fff00001fffff44000000 + 20770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 20770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20770 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000080c000000001fffff44000000 + 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 20770 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 20770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 3ffffffffffffbd80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20780 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000080c000000001fffff44000000 + 20780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 20780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 20790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20790 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000008000000001fffff44000000 + 20790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 20790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 20800 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000008000000001fffff44000000 + 20800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 20810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 20810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 0000000020000814000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20820 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 000000002000080c000000001fffff44000000 + 20820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 20820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20830 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 20830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002030 +After delta: vaddr = 0x80002030 + 20830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 20840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002030, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 20840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 20860 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 20940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 20950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 00000000200408f7800000001fffff44000000 + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 20960 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 0000000020040814000000001fffff44000000 + 20970 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 20970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 20980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 20990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 20990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:111 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2099 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 00000000200003ec000000001fffff44000000 + 21000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 21000 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000020040814000000001fffff44000000 + 21000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 000000002000094d000000001fffff44000000 + 21010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 21010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:112 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2101 +instret:113 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2101 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 21020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:114 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2102 +instret:115 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2102 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21030 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 21030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:116 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2103 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21040 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 21040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 21040 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:117 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2104 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 + 21050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 21050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21050 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 21050 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21060 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000080c000000001fffff44000000 + 21060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 21060 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21070 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 21070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21070 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:118 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2107 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 21080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 21080 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 3ffffffffffffbe00fff00001fffff44000000 + 21090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 21090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21090 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000080c000000001fffff44000000 + 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 21090 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:119 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2109 +instret:120 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2109 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 3ffffffffffffbd80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21100 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000080c000000001fffff44000000 + 21100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 21100 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:121 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2110 +instret:122 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2110 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 21110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21110 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000008000000001fffff44000000 + 21110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:123 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2111 +instret:124 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2111 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 21120 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:125 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2112 +instret:126 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2112 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21130 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000000000008000000001fffff44000000 + 21130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:127 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2113 +instret:128 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2113 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 0000000020000814000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21140 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 000000002000080c000000001fffff44000000 + 21140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:129 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2114 +instret:130 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2114 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21150 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 21150 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 000000002000080c000000001fffff44000000 + 21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002030 +After delta: vaddr = 0x80002030 + 21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:131 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2115 +instret:132 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2115 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 21160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002030, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 21160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +instret:133 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2116 +instret:134 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2116 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21170 : [doFinishMem] DTlbResp { resp: <'h0000000080002030,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002030, check_high: 'h00000000080002038, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 21170 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 21170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:135 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2117 +instret:136 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2117 +calling cycle +[RFile] wr_ 0: r 45 <= 00000000200003ec000000001fffff44000000 +[RFile] wr_ 1: r 08 <= 000000002000080e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21180 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000020000806000000001fffff44000000 + 21180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002038 o: 'h0000000080002038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:137 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2118 +instret:138 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2118 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 21190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 21190 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:139 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2119 +instret:140 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2119 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 21200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21200 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000020000438800000001fffff44000000 + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:141 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2120 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002030, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 21210 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:142 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2121 +instret:143 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2121 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 01 <= 0000000020000806000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21220 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000020000400000000001fffff44000000 + 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 21220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:144 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2122 +instret:145 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2122 +calling cycle +[RFile] wr_ 1: r 58 <= 0000000000000000400000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff00000000000000000000800010e2; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 21230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 21230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 21360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 21360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 21370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 21370 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 45 <= 00000000200003ec000000001fffff44000000 + 21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 21380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21380 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 000000002000080e000000001fffff44000000 + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 21380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000020000438800000001fffff44000000 + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 21390 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21400 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000020000400000000001fffff44000000 +instret:146 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2140 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:147 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2141 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800010e2; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:148 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2142 +instret:149 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2142 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:150 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff60 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 000000002000080e000000001fffff44000000 + 21530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 21530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90e4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002a2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 000000002004083a000000001fffff44000000 + 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } + 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } + 21540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } + 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102048 +After delta: vaddr = 0x80102048 +instret:151 PC:0x1ffff00000000000000000000800010e2 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2154 +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020040812000000001fffff44000000 + 21550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000800000000001fffff44000000 + 21550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002038 o: 'h0000000080002038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102048, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21560 : [doFinishMem] DTlbResp { resp: <'h0000000080102048,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102048, check_high: 'h00000000080102050, check_inclusive: True } }, specBits: 'h000 } + 21560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 50 <= 000000002000043d800000001fffff44000000 + 21570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:152 PC:0x1ffff00000000000000000000800010e4 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2157 +instret:153 PC:0x1ffff00000000000000000000800010e8 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2157 +calling cycle +[RFile] wr_ 0: r 4f <= 000000002000043f800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 21580 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 21580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } +instret:154 PC:0x1ffff00000000000000000000800010ec instr:0xf6060613 iType:Alu [doCommitNormalInst [0]] 2158 +instret:155 PC:0x1ffff00000000000000000000800010f0 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2158 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102048, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90f0 } + 21590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } + 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } + 21600 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 21610 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000c00000001fffff44000000 + 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } + 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:156 PC:0x1ffff00000000000000000000800010f2 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2163 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 0000000000000006000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:157 PC:0x1ffff00000000000000000000800010f4 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2165 +instret:158 PC:0x1ffff00000000000000000000800010f6 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2165 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 21660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:159 PC:0x1ffff00000000000000000000800010fa instr:0x2a2080e7 iType:Jr [doCommitNormalInst [0]] 2166 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 00000000200003d4000000001fffff44000000 + 21670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010fe o: 'h00000000800010fe b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 21670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 00000000200003ec000000001fffff44000000 + 21680 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 21680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 21680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:160 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2168 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 21690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 21690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:161 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2169 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000000000001c00000001fffff44000000 + 21700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 21700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 21700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +instret:162 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2170 +instret:163 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2170 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 21710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 21710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:164 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2171 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 21720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21720 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000006000000001fffff44000000 + 21720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21730 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000006000000001fffff44000000 + 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 21740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 21740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +instret:165 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2174 +instret:166 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2174 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 3ffffffffffffffa0fff00001fffff44000000 + 21760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 21760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:167 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2176 +instret:168 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2176 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 21770 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 21770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:169 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2177 +instret:170 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2177 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 6a <= 0000000000000006000000001fffff44000000 + 21780 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 21780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 21780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:171 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2178 +instret:172 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2178 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 73 <= 0000000020040814000000001fffff44000000 + 21790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 21790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:173 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2179 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 21800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 21800 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:174 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2180 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 00000000200003ec000000001fffff44000000 + 21810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 21810 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000020040814000000001fffff44000000 + 21810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:175 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2181 +instret:176 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2181 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 21820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 21820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000020000802000000001fffff44000000 + 21830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21840 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 21840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21850 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 21850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 21850 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 21860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 21860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21860 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 + 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 21860 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21870 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000814000000001fffff44000000 + 21870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21880 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 21880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21880 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 21880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21890 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 21890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 21890 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 3ffffffffffffbd80fff00001fffff44000000 + 21900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 21900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21900 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000814000000001fffff44000000 + 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 21900 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 3ffffffffffffbd00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21910 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000814000000001fffff44000000 + 21910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 21920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21920 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000008000000001fffff44000000 + 21920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21930 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000008000000001fffff44000000 + 21930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 21940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 000000002000081c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21950 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000814000000001fffff44000000 + 21950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21960 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 21960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002050 +After delta: vaddr = 0x80002050 + 21960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002050, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 21970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 21990 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 00000000200408f7800000001fffff44000000 + 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 22090 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 0000000020040814000000001fffff44000000 + 22100 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 22100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:177 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2212 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 00000000200003ec000000001fffff44000000 + 22130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22130 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000020040814000000001fffff44000000 + 22130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 000000002000094d000000001fffff44000000 + 22140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 22140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:178 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2214 +instret:179 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2214 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 22150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 22150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:180 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2215 +instret:181 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2215 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22160 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 22160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:182 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2216 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22170 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 22170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 22170 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:183 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2217 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 + 22180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 22180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22180 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 22180 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 22180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22190 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000814000000001fffff44000000 + 22190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 22190 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 22190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22200 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 22200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22200 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 22200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:184 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2220 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22210 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 22210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 22210 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 3ffffffffffffbd80fff00001fffff44000000 + 22220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 22220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22220 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000814000000001fffff44000000 + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 22220 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:185 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2222 +instret:186 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2222 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 3ffffffffffffbd00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22230 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000814000000001fffff44000000 + 22230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 22230 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:187 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2223 +instret:188 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2223 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 22240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22240 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000000000008000000001fffff44000000 + 22240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:189 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2224 +instret:190 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2224 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 22250 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:191 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2225 +instret:192 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2225 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22260 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000008000000001fffff44000000 + 22260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 22260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:193 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2226 +instret:194 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2226 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 000000002000081c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22270 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000814000000001fffff44000000 + 22270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:195 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2227 +instret:196 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2227 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22280 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 22280 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000020000814000000001fffff44000000 + 22280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002050 +After delta: vaddr = 0x80002050 + 22280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:197 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2228 +instret:198 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2228 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002050, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 22290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +instret:199 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2229 +instret:200 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2229 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22300 : [doFinishMem] DTlbResp { resp: <'h0000000080002050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002050, check_high: 'h00000000080002058, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 22300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 22300 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:201 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2230 +instret:202 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2230 +calling cycle +[RFile] wr_ 0: r 02 <= 00000000200003ec000000001fffff44000000 +[RFile] wr_ 1: r 5b <= 0000000020000816000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22310 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 22310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22310 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 000000002000080e000000001fffff44000000 + 22310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002058 o: 'h0000000080002058 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 22310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:203 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2231 +instret:204 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2231 +calling cycle + 22320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 22320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 22320 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:205 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2232 +instret:206 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2232 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22330 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 22330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22330 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 000000002000043f800000001fffff44000000 + 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:207 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2233 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002050, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 22340 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:208 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2234 +instret:209 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2234 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 22350 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000400000000001fffff44000000 + 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:210 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2235 +instret:211 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2235 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff00000000000000000000800010fe; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +calling cycle + 22370 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002050, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 22370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 22380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +calling cycle +calling cycle + 22400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002090, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 22420 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800020d0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 22480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 +calling cycle + 22500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 22500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22500 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000020000816000000001fffff44000000 + 22500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 02 <= 00000000200003ec000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 22510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 22510 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +calling cycle + 22520 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 000000002000043f800000001fffff44000000 + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 22520 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } + 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:212 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2252 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22530 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 42 <= 0000000020000400000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:213 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2254 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800010fe; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:214 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2255 +instret:215 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2255 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:216 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff2c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 0000000020000816000000001fffff44000000 + 22660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 22660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9100 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000286 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4b <= 0000000020040841000000001fffff44000000 + 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } + 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } + 22670 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102030 +After delta: vaddr = 0x80102030 +instret:217 PC:0x1ffff00000000000000000000800010fe instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2267 +calling cycle +[RFile] wr_ 0: r 57 <= 000000002004080c000000001fffff44000000 + 22680 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000020000800000000001fffff44000000 + 22680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002058 o: 'h0000000080002058 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102030, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22690 : [doFinishMem] DTlbResp { resp: <'h0000000080102030,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102030, check_high: 'h00000000080102038, check_inclusive: True } }, specBits: 'h000 } + 22690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 45 <= 0000000020000444800000001fffff44000000 + 22700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:218 PC:0x1ffff0000000000000000000080001100 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2270 +instret:219 PC:0x1ffff0000000000000000000080001104 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2270 +calling cycle +[RFile] wr_ 0: r 52 <= 0000000020000446800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 22710 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 22710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h910e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } +instret:220 PC:0x1ffff0000000000000000000080001108 instr:0xf2c60613 iType:Alu [doCommitNormalInst [0]] 2271 +instret:221 PC:0x1ffff000000000000000000008000110c instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2271 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } + 22730 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 22740 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000000000000c00000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:222 PC:0x1ffff000000000000000000008000110e instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2276 +calling cycle +[RFile] wr_ 1: r 50 <= 0000000000000006000000001fffff44000000 +calling cycle +instret:223 PC:0x1ffff0000000000000000000080001110 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2278 +instret:224 PC:0x1ffff0000000000000000000080001112 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2278 +calling cycle +instret:225 PC:0x1ffff0000000000000000000080001116 instr:0x286080e7 iType:Jr [doCommitNormalInst [0]] 2279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 22850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002050, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +calling cycle + 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 22870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102030, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h910c } + 22890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } +calling cycle + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 22920 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080102030, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 23160 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002090, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 23470 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800020d0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 59 <= 00000000200003d4000000001fffff44000000 + 23870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000111a o: 'h000000008000111a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 23870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 00000000200003ec000000001fffff44000000 + 23880 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 23880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:226 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2388 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 23890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 23890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:227 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2389 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 63 <= 0000000000000001c00000001fffff44000000 + 23900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 23900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:228 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2390 +instret:229 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2390 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 23910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 23910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:230 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2391 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } + 23920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23920 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000006000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23930 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 + 23930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 +instret:231 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2394 +instret:232 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2394 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 + 23960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 23960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:233 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2396 +instret:234 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2396 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 23970 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 23970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:235 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2397 +instret:236 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2397 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 6c <= 0000000000000006000000001fffff44000000 + 23980 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 23980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 23980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:237 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2398 +instret:238 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2398 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 75 <= 0000000020040814000000001fffff44000000 + 23990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 23990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 23990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:239 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2399 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 24000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 24000 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:240 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2400 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 00000000200003ec000000001fffff44000000 + 24010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 24010 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000020040814000000001fffff44000000 + 24010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:241 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2401 +instret:242 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2401 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 24020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 24020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 + 24030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24040 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 24040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24050 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 24050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 24050 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 24060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24060 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 24060 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24070 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000081c000000001fffff44000000 + 24070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24080 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 24080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24080 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 24080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080102030, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24090 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 24090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 24090 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 3ffffffffffffbd00fff00001fffff44000000 + 24100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 24100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24100 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000081c000000001fffff44000000 + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 3ffffffffffffbc80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 24110 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000008000000001fffff44000000 + 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 24110 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 24120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24120 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000081c000000001fffff44000000 + 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 24130 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 + 24130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 24140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000824000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 24150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24150 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 000000002000081c000000001fffff44000000 + 24150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24160 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 24160 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 000000002000081c000000001fffff44000000 + 24160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002070 +After delta: vaddr = 0x80002070 + 24160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 24170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002070, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 24170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 24180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +calling cycle + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24190 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 24200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 24280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 72 <= 00000000200408f7800000001fffff44000000 + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 24290 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 24290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 0000000020040814000000001fffff44000000 + 24300 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 24310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 24320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:243 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2432 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 + 24330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 24330 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000020040814000000001fffff44000000 + 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 000000002000094d000000001fffff44000000 + 24340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 24340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:244 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2434 +instret:245 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2434 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 24350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:246 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2435 +instret:247 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2435 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24360 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 24360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:248 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2436 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24370 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 24370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 24370 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:249 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2437 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 + 24380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 24380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24380 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 24380 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24390 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000081c000000001fffff44000000 + 24390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 24390 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24400 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 24400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24400 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 24400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:250 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2440 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24410 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 24410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 24410 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 3ffffffffffffbd00fff00001fffff44000000 + 24420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 24420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24420 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000081c000000001fffff44000000 + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 24420 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 24420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:251 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2442 +instret:252 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2442 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 3ffffffffffffbc80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24430 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000081c000000001fffff44000000 + 24430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 24430 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:253 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2443 +instret:254 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2443 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 24440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24440 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 47 <= 0000000000000008000000001fffff44000000 + 24440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:255 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2444 +instret:256 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2444 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 24450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 24450 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:257 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2445 +instret:258 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2445 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 24460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24460 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 + 24460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 24460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:259 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2446 +instret:260 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2446 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000020000824000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 24470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24470 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 000000002000081c000000001fffff44000000 + 24470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:261 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2447 +instret:262 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2447 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24480 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 24480 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 000000002000081c000000001fffff44000000 + 24480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002070 +After delta: vaddr = 0x80002070 + 24480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:263 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2448 +instret:264 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2448 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002070, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 24490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +instret:265 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2449 +instret:266 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2449 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24500 : [doFinishMem] DTlbResp { resp: <'h0000000080002070,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002070, check_high: 'h00000000080002078, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 24500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24500 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:267 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2450 +instret:268 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2450 +calling cycle +[RFile] wr_ 0: r 4a <= 00000000200003ec000000001fffff44000000 +[RFile] wr_ 1: r 5d <= 000000002000081e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 24510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24510 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000020000816000000001fffff44000000 + 24510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002078 o: 'h0000000080002078 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 24510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:269 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2451 +instret:270 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2451 +calling cycle + 24520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 24520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 24520 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:271 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2452 +instret:272 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2452 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 24530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24530 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000020000446800000001fffff44000000 + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:273 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2453 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002070, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 24540 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:274 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2454 +instret:275 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2454 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24550 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 + 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:276 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2455 +instret:277 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2455 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff000000000000000000008000111a; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 24560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 24680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 24690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 24700 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 4a <= 00000000200003ec000000001fffff44000000 + 24710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 24710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24710 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 000000002000081e000000001fffff44000000 + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 24710 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24720 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000020000446800000001fffff44000000 + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 24720 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24730 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 +instret:278 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2473 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:279 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2474 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000111a; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:280 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2475 +instret:281 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2475 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:282 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff18 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 000000002000081e000000001fffff44000000 + 24860 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h911c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000026a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000020040848000000001fffff44000000 + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } + 24870 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102038 +After delta: vaddr = 0x80102038 +instret:283 PC:0x1ffff000000000000000000008000111a instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2487 +calling cycle +[RFile] wr_ 0: r 58 <= 000000002004080e000000001fffff44000000 + 24880 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000020000800000000001fffff44000000 + 24880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002078 o: 'h0000000080002078 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102038, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24890 : [doFinishMem] DTlbResp { resp: <'h0000000080102038,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102038, check_high: 'h00000000080102040, check_inclusive: True } }, specBits: 'h000 } + 24890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 02 <= 000000002000044b800000001fffff44000000 + 24900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:284 PC:0x1ffff000000000000000000008000111c instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2490 +instret:285 PC:0x1ffff0000000000000000000080001120 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2490 +calling cycle +[RFile] wr_ 0: r 54 <= 000000002000044d800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 24910 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 24910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h912a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } +instret:286 PC:0x1ffff0000000000000000000080001124 instr:0xf1860613 iType:Alu [doCommitNormalInst [0]] 2491 +instret:287 PC:0x1ffff0000000000000000000080001128 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2491 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102038, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9128 } + 24920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } + 24930 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 24940 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000c00000001fffff44000000 + 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } + 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:288 PC:0x1ffff000000000000000000008000112a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2496 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 45 <= 0000000000000006000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:289 PC:0x1ffff000000000000000000008000112c instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2498 +instret:290 PC:0x1ffff000000000000000000008000112e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2498 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 24990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:291 PC:0x1ffff0000000000000000000080001132 instr:0x26a080e7 iType:Jr [doCommitNormalInst [0]] 2499 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5a <= 00000000200003d4000000001fffff44000000 + 25000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001136 o: 'h0000000080001136 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 25000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 46 <= 00000000200003ec000000001fffff44000000 + 25010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 25010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:292 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2501 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 25020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:293 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2502 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 62 <= 0000000000000001c00000001fffff44000000 + 25030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 25030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +instret:294 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2503 +instret:295 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2503 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 25040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 25040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:296 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2504 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 25050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25050 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 + 25050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25060 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000006000000001fffff44000000 + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 25070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +instret:297 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2507 +instret:298 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2507 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 3ffffffffffffffa0fff00001fffff44000000 + 25090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 25090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:299 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2509 +instret:300 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2509 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000000000000000000001fffff44000000 + 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 25100 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:301 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2510 +instret:302 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2510 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 73 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 6e <= 0000000000000006000000001fffff44000000 + 25110 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 25110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:303 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2511 +instret:304 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2511 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 74 <= 0000000020040814000000001fffff44000000 + 25120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 25120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:305 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2512 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 25130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:306 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2513 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 00000000200003ec000000001fffff44000000 + 25140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000020040814000000001fffff44000000 + 25140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:307 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2514 +instret:308 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2514 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h005, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 25150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 25150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 0000000020000802000000001fffff44000000 + 25160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25170 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 25170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25180 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 25180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 25180 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 25190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 25190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25190 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 25190 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25200 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000824000000001fffff44000000 + 25200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25210 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 25210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25210 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 25210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25220 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 25220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 25220 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 3ffffffffffffbc80fff00001fffff44000000 + 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 25230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25230 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000824000000001fffff44000000 + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 25230 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 3ffffffffffffbc00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25240 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000824000000001fffff44000000 + 25240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 25250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25250 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000008000000001fffff44000000 + 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25260 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000008000000001fffff44000000 + 25260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0c <= 000000002000082c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000020000824000000001fffff44000000 + 25280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25290 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 25290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002090 +After delta: vaddr = 0x80002090 + 25290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002090, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 25320 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 73 <= 00000000200408f7800000001fffff44000000 + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 25420 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 0000000020040814000000001fffff44000000 + 25430 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 25430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:309 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2545 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 00000000200003ec000000001fffff44000000 + 25460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25460 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000020040814000000001fffff44000000 + 25460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h002, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 000000002000094d000000001fffff44000000 + 25470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 25470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:310 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2547 +instret:311 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2547 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 25480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:312 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2548 +instret:313 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2548 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25490 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 25490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:314 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2549 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25500 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 25500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 25500 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:315 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2550 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 + 25510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 25510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25510 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 25510 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25520 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000824000000001fffff44000000 + 25520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 25520 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25530 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 25530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25530 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 25530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:316 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2553 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25540 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 25540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 25540 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 3ffffffffffffbc80fff00001fffff44000000 + 25550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 25550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25550 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000824000000001fffff44000000 + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 25550 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:317 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2555 +instret:318 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2555 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7c <= 3ffffffffffffbc00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25560 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000824000000001fffff44000000 + 25560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 25560 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:319 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2556 +instret:320 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2556 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 25570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25570 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000000000008000000001fffff44000000 + 25570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:321 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2557 +instret:322 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2557 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 25580 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:323 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2558 +instret:324 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2558 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25590 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000000000008000000001fffff44000000 + 25590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 25590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:325 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2559 +instret:326 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2559 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0c <= 000000002000082c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25600 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000020000824000000001fffff44000000 + 25600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:327 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2560 +instret:328 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2560 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25610 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 25610 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000824000000001fffff44000000 + 25610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002090 +After delta: vaddr = 0x80002090 + 25610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:329 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2561 +instret:330 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2561 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002090, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 25620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +instret:331 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2562 +instret:332 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2562 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25630 : [doFinishMem] DTlbResp { resp: <'h0000000080002090,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002090, check_high: 'h00000000080002098, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 25630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 25630 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:333 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2563 +instret:334 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2563 +calling cycle +[RFile] wr_ 0: r 49 <= 00000000200003ec000000001fffff44000000 +[RFile] wr_ 1: r 4f <= 0000000020000826000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 25640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25640 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 000000002000081e000000001fffff44000000 + 25640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002098 o: 'h0000000080002098 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 25640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:335 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2564 +instret:336 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2564 +calling cycle + 25650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 25650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 25650 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:337 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2565 +instret:338 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2565 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 25660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25660 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 000000002000044d800000001fffff44000000 + 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:339 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2566 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002090, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 25670 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:340 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2567 +instret:341 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2567 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25680 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:342 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2568 +instret:343 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2568 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080001136; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 25690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle + 25700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +calling cycle +calling cycle + 25750 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002110, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 25810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 25820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 25830 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 25830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 25830 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 49 <= 00000000200003ec000000001fffff44000000 + 25840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 25840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25840 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000826000000001fffff44000000 + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 25840 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25850 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 000000002000044d800000001fffff44000000 + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 25850 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } + 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25860 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 +instret:344 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2586 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:345 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2587 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080001136; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:346 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2588 +instret:347 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2588 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:348 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffedc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 0000000020000826000000001fffff44000000 + 25990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 25990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000024e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 000000002004084f000000001fffff44000000 + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } + 26000 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102018 +After delta: vaddr = 0x80102018 +instret:349 PC:0x1ffff0000000000000000000080001136 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2600 +calling cycle +[RFile] wr_ 0: r 4b <= 0000000020040806000000001fffff44000000 + 26010 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000020000800000000001fffff44000000 + 26010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002098 o: 'h0000000080002098 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102018, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26020 : [doFinishMem] DTlbResp { resp: <'h0000000080102018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102018, check_high: 'h00000000080102020, check_inclusive: True } }, specBits: 'h000 } + 26020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 4a <= 0000000020000452800000001fffff44000000 + 26030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:350 PC:0x1ffff0000000000000000000080001138 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2603 +instret:351 PC:0x1ffff000000000000000000008000113c instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2603 +calling cycle +[RFile] wr_ 0: r 42 <= 0000000020000454800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 26040 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 26040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } +instret:352 PC:0x1ffff0000000000000000000080001140 instr:0xedc60613 iType:Alu [doCommitNormalInst [0]] 2604 +instret:353 PC:0x1ffff0000000000000000000080001144 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2604 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102018, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9144 } + 26050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } + 26060 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 26070 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 0000000000000000c00000001fffff44000000 + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:354 PC:0x1ffff0000000000000000000080001146 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2609 +calling cycle +[RFile] wr_ 1: r 02 <= 0000000000000006000000001fffff44000000 +calling cycle +instret:355 PC:0x1ffff0000000000000000000080001148 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2611 +instret:356 PC:0x1ffff000000000000000000008000114a instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2611 +calling cycle +instret:357 PC:0x1ffff000000000000000000008000114e instr:0x24e080e7 iType:Jr [doCommitNormalInst [0]] 2612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 26230 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002110, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 26620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 00000000200003d4000000001fffff44000000 + 26630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001152 o: 'h0000000080001152 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 26630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 43 <= 00000000200003ec000000001fffff44000000 + 26640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 26640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 26640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:358 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2664 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26650 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 26650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 26650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:359 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2665 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 64 <= 0000000000000001c00000001fffff44000000 + 26660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 26660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 26660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +instret:360 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2666 +instret:361 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2666 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 26670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:362 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2667 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 26680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26680 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 + 26680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26690 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 67 <= 0000000000000006000000001fffff44000000 + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 26700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 26700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +instret:363 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2670 +instret:364 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2670 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 66 <= 3ffffffffffffffa0fff00001fffff44000000 + 26720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 26720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } +instret:365 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2672 +instret:366 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2672 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000000000000001fffff44000000 + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 26730 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 26730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:367 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2673 +instret:368 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2673 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 6f <= 0000000000000006000000001fffff44000000 + 26740 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 26740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 26740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:369 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2674 +instret:370 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2674 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 70 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 76 <= 0000000020040814000000001fffff44000000 + 26750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 26750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:371 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2675 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 26760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 26760 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } + 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:372 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2676 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 00000000200003ec000000001fffff44000000 + 26770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 26770 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000020040814000000001fffff44000000 + 26770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:373 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2677 +instret:374 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2677 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h001, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 26780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 26780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 26780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 78 <= 0000000020000802000000001fffff44000000 + 26790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 26790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26800 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 26800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 26810 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 26810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 26810 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 26820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 26820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26820 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 26820 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 26820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26830 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000082c000000001fffff44000000 + 26830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 26830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26840 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 26840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26840 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 26840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26850 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 26850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 26850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 3ffffffffffffbc00fff00001fffff44000000 + 26860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 26860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000082c000000001fffff44000000 + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 26860 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7e <= 3ffffffffffffbb80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26870 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000082c000000001fffff44000000 + 26870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 26870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 26880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26880 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000008000000001fffff44000000 + 26880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 26880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 26890 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000008000000001fffff44000000 + 26890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 26900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 26900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 56 <= 0000000020000834000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26910 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 000000002000082c000000001fffff44000000 + 26910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 26910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26920 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 26920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800020b0 +After delta: vaddr = 0x800020b0 + 26920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 26930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020b0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 26950 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 27040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 00000000200408f7800000001fffff44000000 + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 27050 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 27050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 76 <= 0000000020040814000000001fffff44000000 + 27060 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 27060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 27060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 27070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 27080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:375 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2708 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 79 <= 00000000200003ec000000001fffff44000000 + 27090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 27090 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 69 <= 0000000020040814000000001fffff44000000 + 27090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 000000002000094d000000001fffff44000000 + 27100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:376 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2710 +instret:377 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2710 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 0000000020000802000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 27110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:378 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2711 +instret:379 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2711 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27120 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 27120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } +instret:380 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2712 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27130 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 27130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 27130 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } + 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } +instret:381 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2713 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 + 27140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 27140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27140 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 27140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 000000002000082c000000001fffff44000000 + 27150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 27150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27160 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 27160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 + 27160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:382 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2716 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27170 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 27170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 27170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7a <= 3ffffffffffffbc00fff00001fffff44000000 + 27180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 27180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 000000002000082c000000001fffff44000000 + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 27180 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:383 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2718 +instret:384 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2718 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 3ffffffffffffbb80fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27190 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000002000082c000000001fffff44000000 + 27190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 27190 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:385 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2719 +instret:386 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2719 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 27200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27200 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000000000008000000001fffff44000000 + 27200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 27200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:387 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2720 +instret:388 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2720 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 27210 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } + 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 27210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:389 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2721 +instret:390 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2721 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27220 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000000000008000000001fffff44000000 + 27220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:391 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2722 +instret:392 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2722 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 56 <= 0000000020000834000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 27230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27230 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 000000002000082c000000001fffff44000000 + 27230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:393 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2723 +instret:394 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2723 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27240 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 27240 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 000000002000082c000000001fffff44000000 + 27240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800020b0 +After delta: vaddr = 0x800020b0 + 27240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:395 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2724 +instret:396 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2724 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020b0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 27250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +instret:397 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2725 +instret:398 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2725 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27260 : [doFinishMem] DTlbResp { resp: <'h00000000800020b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020b0, check_high: 'h000000000800020b8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 27260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 27260 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:399 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2726 +instret:400 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2726 +calling cycle +[RFile] wr_ 0: r 4e <= 00000000200003ec000000001fffff44000000 +[RFile] wr_ 1: r 52 <= 000000002000082e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27270 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000020000826000000001fffff44000000 + 27270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b8 o: 'h00000000800020b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:401 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2727 +instret:402 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2727 +calling cycle + 27280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 27280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 27280 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:403 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2728 +instret:404 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2728 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27290 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 27290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27290 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000020000454800000001fffff44000000 + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:405 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2729 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 27300 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:406 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2730 +instret:407 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2730 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 27310 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000020000400000000001fffff44000000 + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:408 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2731 +instret:409 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2731 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080001152; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 27320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 27430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 27440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 27450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 27460 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 27460 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +calling cycle +[RFile] wr_ 1: r 4e <= 00000000200003ec000000001fffff44000000 + 27470 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 27470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27470 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 000000002000082e000000001fffff44000000 + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 27470 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27480 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000020000454800000001fffff44000000 + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 27480 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27490 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000020000400000000001fffff44000000 +instret:410 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2749 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:411 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2750 +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080001152; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:412 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2751 +instret:413 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2751 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:414 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffed0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 000000002000082e000000001fffff44000000 + 27620 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9154 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h12, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000232 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000020040856000000001fffff44000000 + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } + 27630 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102028 +After delta: vaddr = 0x80102028 +instret:415 PC:0x1ffff0000000000000000000080001152 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2763 +calling cycle +[RFile] wr_ 0: r 51 <= 000000002004080a000000001fffff44000000 + 27640 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5c <= 0000000020000800000000001fffff44000000 + 27640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b8 o: 'h00000000800020b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102028, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27650 : [doFinishMem] DTlbResp { resp: <'h0000000080102028,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102028, check_high: 'h00000000080102030, check_inclusive: True } }, specBits: 'h000 } + 27650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 +calling cycle +[RFile] wr_ 1: r 49 <= 0000000020000459800000001fffff44000000 + 27660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:416 PC:0x1ffff0000000000000000000080001154 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2766 +instret:417 PC:0x1ffff0000000000000000000080001158 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2766 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h000000b8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5f <= 000000002000045b800000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 27670 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 27670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9162 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h000000b8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } +instret:418 PC:0x1ffff000000000000000000008000115c instr:0xed060613 iType:Alu [doCommitNormalInst [0]] 2767 +instret:419 PC:0x1ffff0000000000000000000080001160 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2767 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102028, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9160 } + 27680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } + 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } + 27690 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27700 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 0000000000000000c00000001fffff44000000 + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:420 PC:0x1ffff0000000000000000000080001162 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2772 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 0000000000000006000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:421 PC:0x1ffff0000000000000000000080001164 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2774 +instret:422 PC:0x1ffff0000000000000000000080001166 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2774 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 27750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:423 PC:0x1ffff000000000000000000008000116a instr:0x232080e7 iType:Jr [doCommitNormalInst [0]] 2775 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 50 <= 00000000200003d4000000001fffff44000000 + 27760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000116e o: 'h000000008000116e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 00000000200003ec000000001fffff44000000 + 27770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 27770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:424 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2777 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27780 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 27780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 27780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:425 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2778 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 61 <= 0000000000000001c00000001fffff44000000 + 27790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } + 27790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 27790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +instret:426 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2779 +instret:427 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2779 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 27800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 27800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:428 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2780 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } + 27810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27810 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000006000000001fffff44000000 + 27810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27820 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } + 27830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 27830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +instret:429 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2783 +instret:430 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2783 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 + 27850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } + 27850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:431 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2785 +instret:432 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2785 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6f <= 0000000000000000000000001fffff44000000 + 27860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 27860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:433 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2786 +instret:434 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2786 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 00000000200408f7800000001fffff44000000 +[RFile] wr_ 1: r 71 <= 0000000000000006000000001fffff44000000 + 27870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 27870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:435 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2787 +instret:436 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2787 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 72 <= 0000000000000008000000001fffff44000000 +[RFile] wr_ 1: r 68 <= 0000000020040814000000001fffff44000000 + 27880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } + 27880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 27880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } +instret:437 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2788 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 27890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 27890 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:438 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2789 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 77 <= 00000000200003ec000000001fffff44000000 + 27900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 27900 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000020040814000000001fffff44000000 + 27900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:439 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2790 +instret:440 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2790 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } + 27910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 27910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 + 27920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27930 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 27930 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27940 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 27940 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } + 27940 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 27950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 27950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27950 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 27950 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27960 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 + 27960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 27960 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27970 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 27970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27970 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000834000000001fffff44000000 + 27970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 27970 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 27970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:441 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2797 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 27980 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 27980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 27980 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27990 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } + 27990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27990 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000834000000001fffff44000000 + 27990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 27990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } +instret:442 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2799 +instret:443 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2799 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 3ffffffffffffbb80fff00001fffff44000000 + 28000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } + 28000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 28000 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +instret:444 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2800 +instret:445 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2800 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 3ffffffffffffbb00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 28010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } + 28010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28010 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000834000000001fffff44000000 + 28010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:446 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2801 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } + 28020 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000008000000001fffff44000000 + 28020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28030 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000008000000001fffff44000000 + 28030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 28040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28040 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000834000000001fffff44000000 + 28040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 000000002000083c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28050 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000020000834000000001fffff44000000 + 28050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020f0 o: 'h00000000800020f0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800020d0 +After delta: vaddr = 0x800020d0 + 28050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28060 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 28170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } + 28180 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 + 28190 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6b <= 0000000020040814000000001fffff44000000 + 28190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102050 +After delta: vaddr = 0x80102050 + 28200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 + 28210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 28210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:447 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2821 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28220 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } + 28220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 28220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28230 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } + 28230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } + 28230 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 + 28240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } + 28240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28240 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } + 28240 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 28240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 58 <= 0000000020000802000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28250 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000834000000001fffff44000000 + 28250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } + 28250 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } + 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 28250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28260 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h005 } + 28260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28260 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 + 28260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 28260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } +instret:448 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2826 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28270 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h005 } + 28270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } + 28270 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7b <= 3ffffffffffffbb80fff00001fffff44000000 + 28280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h004 } + 28280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28280 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000020000834000000001fffff44000000 + 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 28280 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 28280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } +instret:449 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2828 +instret:450 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2828 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 3ffffffffffffbb00fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28290 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000020000834000000001fffff44000000 + 28290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 28290 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:451 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2829 +instret:452 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2829 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h004 } + 28300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28300 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000008000000001fffff44000000 + 28300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } +instret:453 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2830 +instret:454 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2830 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 28310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } + 28310 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:455 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2831 +instret:456 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2831 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28320 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000008000000001fffff44000000 + 28320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002008 +After delta: vaddr = 0x80002008 + 28320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:457 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2832 +instret:458 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2832 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 000000002000083c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 28330 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020000834000000001fffff44000000 + 28330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020f0 o: 'h00000000800020f0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:459 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2833 +instret:460 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2833 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28340 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } + 28340 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 0000000020000834000000001fffff44000000 + 28340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x800020d0 +After delta: vaddr = 0x800020d0 + 28340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:461 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2834 +instret:462 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2834 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa8 +After delta: vaddr = 0x80000fa8 + 28350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:463 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2835 +instret:464 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2835 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28360 : [doFinishMem] DTlbResp { resp: <'h00000000800020d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020d0, check_high: 'h000000000800020d8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } + 28360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 28360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +instret:465 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2836 +instret:466 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2836 +calling cycle +[RFile] wr_ 0: r 54 <= 0000000020000836000000001fffff44000000 +[RFile] wr_ 1: r 4d <= 00000000200003ec000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 28370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } + 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 28370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } +instret:467 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2837 +instret:468 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2837 +calling cycle + 28380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } + 28380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } + 28380 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } + 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +instret:469 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2838 +instret:470 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2838 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } + 28390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28390 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4c <= 000000002000045b800000001fffff44000000 + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } +instret:471 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2839 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } + 28400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +instret:472 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2840 +instret:473 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2840 +calling cycle + 28410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000400000000001fffff44000000 + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:474 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2841 +instret:475 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2841 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000116e; 'h1; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } + 28420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +calling cycle + 28430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 28450 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 28450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } +calling cycle + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } + 28460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 28470 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002150, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 0000000020000836000000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:476 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2849 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:477 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2850 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffeac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 +instret:478 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2851 +instret:479 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2851 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 28520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:480 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2852 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000020000836000000001fffff44000000 + 28530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } + 28530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h9170 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 28530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 000000002004085d000000001fffff44000000 + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } + 28540 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } + 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80102020 +After delta: vaddr = 0x80102020 + 28540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:481 PC:0x1ffff000000000000000000008000116e instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2854 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe76 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020040808000000001fffff44000000 + 28550 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000000000000001fffff44000000 + 28550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102020, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe4 +After delta: vaddr = 0x80000fe4 + 28550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0cb }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 28560 : [doFinishMem] DTlbResp { resp: <'h0000000080102020,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102020, check_high: 'h00000000080102028, check_inclusive: True } }, specBits: 'h000 } + 28560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe4 +After delta: vaddr = 0x80000fe4 + 28560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000020000862800000001fffff44000000 + 28570 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 28570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h9186 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 + 28570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } +instret:482 PC:0x1ffff0000000000000000000080001170 instr:0xfc043503 iType:Ld [doCommitNormalInst [0]] 2857 +instret:483 PC:0x1ffff0000000000000000000080001174 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2857 +calling cycle +[RFile] wr_ 0: r 45 <= 0000000020000800000000001fffff44000000 + 28580 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 28580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } + 28580 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:484 PC:0x1ffff0000000000000000000080001178 instr:0xeac60613 iType:Alu [doCommitNormalInst [0]] 2858 +instret:485 PC:0x1ffff000000000000000000008000117c instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2858 +calling cycle + 28590 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102020, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h917c } + 28590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9192 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28590 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 000000000847254b800000001fffff44000000 + 28590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } +instret:486 PC:0x1ffff000000000000000000008000117e instr:0xfea42223 iType:St [doCommitNormalInst [0]] 2859 +instret:487 PC:0x1ffff0000000000000000000080001182 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2859 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } + 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } + 28600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } +calling cycle + 28610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000c00000001fffff44000000 + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h917e } + 28620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } +calling cycle + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 28950 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002150, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe76 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 29330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe4 +After delta: vaddr = 0x80000fe4 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0ca }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 29340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 0000000020000862800000001fffff44000000 + 29350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 29350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h9186 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80002000 +After delta: vaddr = 0x80002000 + 29350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 45 <= 0000000020000800000000001fffff44000000 + 29360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } + 29360 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29370 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } + 29370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9192 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29370 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 + 29370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fcc After delta: vaddr = 0x80000fcc - 13990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000b4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000003000000001fffff44000000 - 14000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fcc, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 14000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc8 -After delta: vaddr = 0x80000fc8 - 14000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc4, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000002000000001fffff44000000 - 14010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fcc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fcc, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } - 14010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 14010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc4, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc4 -After delta: vaddr = 0x80000fc4 -instret:22 PC:0x1ffff0000000000000000000080000500 instr:0x00004531 iType:Alu [doCommitNormalInst [0]] 1401 -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000180000000001fffff44000000 - 14020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fcc, check_inclusive: True } }, specBits: 'h000 } - 14020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc4, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc4 o: 'h0000000080000fc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc4, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:23 PC:0x1ffff0000000000000000000080000502 instr:0xfca42623 iType:St [doCommitNormalInst [0]] 1402 -calling cycle -[RFile] wr_ 0: r 5c <= 0000000020000145000000001fffff44000000 - 14030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc4 o: 'h0000000080000fc4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc4, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } -instret:24 PC:0x1ffff0000000000000000000080000506 instr:0xfca42423 iType:St [doCommitNormalInst [0]] 1403 -instret:25 PC:0x1ffff000000000000000000008000050a instr:0x00004521 iType:Alu [doCommitNormalInst [1]] 1403 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff90, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000020000147000000001fffff44000000 -[ALU redirect - 1] 'h1ffff00000000000000000000800005c8; 'h0; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } -instret:26 PC:0x1ffff000000000000000000008000050c instr:0xfca42223 iType:St [doCommitNormalInst [0]] 1404 -instret:27 PC:0x1ffff0000000000000000000080000510 instr:0x60000513 iType:Alu [doCommitNormalInst [1]] 1404 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle -instret:28 PC:0x1ffff0000000000000000000080000514 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1406 -instret:29 PC:0x1ffff0000000000000000000080000518 instr:0x0b4080e7 iType:Jr [doCommitNormalInst [1]] 1406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 14240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84e8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84ea } - 14260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ea } -calling cycle - 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ea } - 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84ea } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84f0 } - 14280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f0 } -calling cycle - 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f0 } - 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd4, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84f6 } - 14300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f6 } -calling cycle - 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f6 } - 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fd4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84f6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h84fc } - 14320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } -calling cycle - 14330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } - 14330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h84fc } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fcc, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8502 } - 14340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fcc, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8502 } -calling cycle - 14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fcc, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8502 } - 14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fcc, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8502 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8506 } - 14360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } -calling cycle - 14370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } - 14370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8506 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc4, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h850c } - 14380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fc4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } -calling cycle - 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fc4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } - 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fc4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h850c } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 15140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 00000000200003cc000000001fffff44000000 - 15150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000051c o: 'h000000008000051c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 15150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 15150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 00000000200003dc000000001fffff44000000 - 15160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 15160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 15160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 15160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:30 PC:0x1ffff00000000000000000000800005c8 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1516 -calling cycle - 15170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 15170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000600 o: 'h0000000000000600 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 15170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 -instret:31 PC:0x1ffff00000000000000000000800005ca instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1517 -calling cycle -[RFile] wr_ 0: r 64 <= 0000000020000176000000001fffff44000000 - 15180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85ca } - 15180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 15180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } -instret:32 PC:0x1ffff00000000000000000000800005cc instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1518 -instret:33 PC:0x1ffff00000000000000000000800005ce instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1518 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 0000000020000178000000001fffff44000000 -[ALU redirect - 1] 'h1ffff000000000000000000008000069e; 'h0; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } - 15190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 15190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h85d4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } - 15190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:34 PC:0x1ffff00000000000000000000800005d0 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1519 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 15210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f68, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 15210 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000180000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:35 PC:0x1ffff00000000000000000000800005d4 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 1523 -instret:36 PC:0x1ffff00000000000000000000800005d8 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1523 -calling cycle -instret:37 PC:0x1ffff00000000000000000000800005dc instr:0x0c6080e7 iType:Jr [doCommitNormalInst [0]] 1524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 15970 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f68, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 15980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 15980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85cc } - 15990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } -calling cycle - 16000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } - 16000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 16000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85d0 } - 16010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } -calling cycle - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 16020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 16340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 00000000200003b4000000001fffff44000000 - 16350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005e0 o: 'h00000000800005e0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 16350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 16350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h359 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 00000000200003cc000000001fffff44000000 - 16360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 16360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 16360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 16360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:38 PC:0x1ffff000000000000000000008000069e instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1636 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 16370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000600 o: 'h0000000000000600 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 16370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 -instret:39 PC:0x1ffff00000000000000000000800006a0 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1637 -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000001c00000001fffff44000000 - 16380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a0 } - 16380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 16380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } -instret:40 PC:0x1ffff00000000000000000000800006a2 instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1638 -instret:41 PC:0x1ffff00000000000000000000800006a4 instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1638 -calling cycle - 16390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 16390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h86aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } - 16390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:42 PC:0x1ffff00000000000000000000800006a6 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1639 -calling cycle - 16400 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000180000000001fffff44000000 -calling cycle - 16410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f28, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:43 PC:0x1ffff00000000000000000000800006aa instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 1642 -instret:44 PC:0x1ffff00000000000000000000800006ae instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 1642 -calling cycle -calling cycle -instret:45 PC:0x1ffff00000000000000000000800006b0 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1644 -instret:46 PC:0x1ffff00000000000000000000800006b4 instr:0x0120006f iType:J [doCommitNormalInst [1]] 1644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000000000000001fffff44000000 - 16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h86c6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 16940 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000180000000001fffff44000000 - 16940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 16950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff924 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 16960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:47 PC:0x1ffff00000000000000000000800006c6 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1696 -instret:48 PC:0x1ffff00000000000000000000800006ca instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 1696 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 3ffffffffffffe800fff00001fffff44000000 - 16970 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } - 16970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h86dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 16970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 16970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h37d }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 - 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 16980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 16980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:49 PC:0x1ffff00000000000000000000800006cc instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 1698 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000180000000001fffff44000000 - 16990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 16990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 - 16990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:50 PC:0x1ffff00000000000000000000800006ce instr:0x0000899d iType:Alu [doCommitNormalInst [0]] 1699 -calling cycle - 17000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ed8, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 0: r 79 <= 00000000200405b9000000001fffff44000000 -[RFile] wr_ 1: r 74 <= 0000000000000182000000001fffff44000000 - 17000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h002 } - 17000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f08, shiftedBE: tagged DataMemAccess , pcHash: 'h86f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 17000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000608 o: 'h0000000000000608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 17000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 17000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } -instret:51 PC:0x1ffff00000000000000000000800006d0 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1700 -calling cycle -[RFile] wr_ 1: r 7a <= 0000000020040402000000001fffff44000000 - 17010 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } - 17010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } - 17010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 -instret:52 PC:0x1ffff00000000000000000000800006d2 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1701 -calling cycle - 17020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } -instret:53 PC:0x1ffff00000000000000000000800006d4 instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 1702 -instret:54 PC:0x1ffff00000000000000000000800006d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 17150 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f28, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a2 } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } - 17170 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 17170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } -calling cycle - 17180 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 - 17180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } - 17180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a6 } - 17190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x00000000 -After delta: vaddr = 0x00000000 - 17190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } -calling cycle - 17200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 17200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } - 17200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 17200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 17210 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86d4 } - 17210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } -calling cycle - 17220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } - 17220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 17770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ed8, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 17780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 17780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 17780 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 17780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 -calling cycle - 17790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000000000001fffff44000000 - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 17790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 17790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 17800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 -calling cycle - 17810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff924 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18470 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } - 18470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h86dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h37d }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 00000000200405b9000000001fffff44000000 - 18480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 18480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 18480 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 18480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 18480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000020040402000000001fffff44000000 - 18490 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000182000000001fffff44000000 - 18490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 18490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000007c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 18500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 18510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f08, shiftedBE: tagged DataMemAccess , pcHash: 'h86f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000608 o: 'h0000000000000608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:55 PC:0x1ffff00000000000000000000800006dc instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 1851 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 00000000200003cc000000001fffff44000000 - 18520 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 18520 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000020040402000000001fffff44000000 - 18520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h026 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 000000002004020e800000001fffff44000000 - 18530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 18530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:56 PC:0x1ffff00000000000000000000800006e0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1853 -instret:57 PC:0x1ffff00000000000000000000800006e4 instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 1853 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000020040400000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86e0 } - 18540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 18540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } -instret:58 PC:0x1ffff00000000000000000000800006e8 instr:0x92450513 iType:Alu [doCommitNormalInst [0]] 1854 -instret:59 PC:0x1ffff00000000000000000000800006ec instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1854 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f08, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18550 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 18550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h86f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } - 18550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 18550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } -instret:60 PC:0x1ffff00000000000000000000800006f0 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1855 -calling cycle - 18560 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f08, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86ec } - 18560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8842 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 18560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 18560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } -instret:61 PC:0x1ffff00000000000000000000800006f4 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1856 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000079e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h002 } - 18570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8848 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 18570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 - 18570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8848 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080101008, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8848 } - 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8848 } - 18580 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18590 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000182000000001fffff44000000 - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 0000000020040218800000001fffff44000000 - 18600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 18600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000020040400000000001fffff44000000 - 18610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 18610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18620 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } - 18620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h886a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 18620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } -calling cycle - 18630 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } - 18630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8870 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 18630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 - 18630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } -calling cycle - 18640 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h003 } - 18640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8872 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 18640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 - 18640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8872 } -calling cycle - 18650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8872 } - 18650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8872 } - 18650 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 18650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 18660 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000182000000001fffff44000000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 19390 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080101008, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 19400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19400 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 19400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 19400 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 19400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 -calling cycle - 19410 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000000000001fffff44000000 - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 19410 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19420 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000400000000001fffff44000000 - 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 19420 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 19420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19430 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000020000400000000001fffff44000000 - 19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 19430 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:62 PC:0x1ffff00000000000000000000800006f8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1943 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19440 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000020000400000000001fffff44000000 - 19440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 -calling cycle -[RFile] wr_ 1: r 01 <= 3fffffffffffffcc0fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:63 PC:0x1ffff00000000000000000000800006fa instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 1945 -instret:64 PC:0x1ffff00000000000000000000800006fc instr:0x13c0006f iType:J [doCommitNormalInst [1]] 1945 -calling cycle -[RFile] wr_ 1: r 43 <= 3fffffffffffffc40fff00001fffff44000000 - 19460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h001 } - 19460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 -instret:65 PC:0x1ffff0000000000000000000080000838 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 1946 -instret:66 PC:0x1ffff000000000000000000008000083a instr:0x00100597 iType:Auipc [doCommitNormalInst [1]] 1946 -calling cycle -[RFile] wr_ 0: r 42 <= 0000000020000582000000001fffff44000000 - 19470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:67 PC:0x1ffff000000000000000000008000083e instr:0x7c658593 iType:Alu [doCommitNormalInst [0]] 1947 -instret:68 PC:0x1ffff0000000000000000000080000842 instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 1947 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19480 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h000 } -instret:69 PC:0x1ffff0000000000000000000080000844 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 1948 -instret:70 PC:0x1ffff0000000000000000000080000846 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 1948 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:71 PC:0x1ffff0000000000000000000080000848 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1949 -instret:72 PC:0x1ffff000000000000000000008000084c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 1949 -calling cycle -instret:73 PC:0x1ffff0000000000000000000080000850 instr:0x0120006f iType:J [doCommitNormalInst [0]] 1950 -instret:74 PC:0x1ffff0000000000000000000080000862 instr:0x00100517 iType:Auipc [doCommitNormalInst [1]] 1950 -calling cycle -instret:75 PC:0x1ffff0000000000000000000080000866 instr:0x79e50593 iType:Alu [doCommitNormalInst [0]] 1951 -instret:76 PC:0x1ffff000000000000000000008000086a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 1951 -calling cycle -instret:77 PC:0x1ffff000000000000000000008000086c instr:0xfca43823 iType:St [doCommitNormalInst [0]] 1952 -instret:78 PC:0x1ffff0000000000000000000080000870 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 1952 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h886c } - 19530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } -instret:79 PC:0x1ffff0000000000000000000080000872 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 1953 -instret:80 PC:0x1ffff0000000000000000000080000876 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 1953 -calling cycle - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:81 PC:0x1ffff0000000000000000000080000878 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1954 -instret:82 PC:0x1ffff000000000000000000008000087a instr:0x0040006f iType:J [doCommitNormalInst [1]] 1954 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080101000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8878 } - 19550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } -calling cycle - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 20430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20440 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 20440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h887e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h887e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 20450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8882 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h887e } - 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h887e } - 20450 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 20450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 20450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8882 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20460 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000182000000001fffff44000000 - 20460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8882 } - 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8882 } - 20460 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 20460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 20470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8888 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20470 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 - 20470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 20470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8888 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8888 } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8888 } - 20480 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001000 -After delta: vaddr = 0x80001000 - 20480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:83 PC:0x1ffff000000000000000000008000087e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2048 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8896 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20490 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000400000000001fffff44000000 - 20490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000608 o: 'h0000000000000608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 20490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } -instret:84 PC:0x1ffff0000000000000000000080000882 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2049 -calling cycle - 20500 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } - 20500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 20500 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 20500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 20500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 00000000200003cc000000001fffff44000000 - 20510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 20510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h889a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20510 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000000000001fffff44000000 - 20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 20510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } -instret:85 PC:0x1ffff0000000000000000000080000886 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2051 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000020000402000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8886 } - 20520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h889c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 20520 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 20530 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000020000178000000001fffff44000000 - 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 20530 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } -instret:86 PC:0x1ffff0000000000000000000080000888 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2053 -instret:87 PC:0x1ffff000000000000000000008000088c instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2053 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20540 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 00000000200003dc000000001fffff44000000 - 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } - 20540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 20540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:88 PC:0x1ffff000000000000000000008000088e instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2054 -instret:89 PC:0x1ffff0000000000000000000080000892 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2054 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 40000000000000000000ffff1fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 20550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 20550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 20560 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001000, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 20560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 20570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 20570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 20570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 20580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 20580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 20580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000003000000001fffff44000000 - 20590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 20590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h85ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 20590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 20590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 20600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h85f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20600 : [doRespLdForward] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 62 <= 40000000000000000000ffff1fffff44000000 - 20600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 20600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000034 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 20610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 20610 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000000000001fffff44000000 - 20610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 21040 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } -calling cycle - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h888e } - 21060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } -calling cycle - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 21420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 21430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 21440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8896 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 21440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } -calling cycle - 21450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 21450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h889a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 21450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 21450 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 21450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } -calling cycle -[RFile] wr_ 1: r 5c <= 00000000200003cc000000001fffff44000000 - 21460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 21460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h889c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21460 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000020000402000000001fffff44000000 - 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 21460 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21470 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000020000178000000001fffff44000000 - 21470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 21470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 21470 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 21470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21480 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 00000000200003dc000000001fffff44000000 - 21480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:90 PC:0x1ffff0000000000000000000080000896 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2148 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:91 PC:0x1ffff000000000000000000008000089a instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2149 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800005e0; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } - 21500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 21500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:92 PC:0x1ffff000000000000000000008000089c instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2150 -instret:93 PC:0x1ffff000000000000000000008000089e instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2150 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:94 PC:0x1ffff00000000000000000000800008a0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2152 -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 21580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 40000000000000000000ffff1fffff44000000 - 21600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 21600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 21600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 21610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 -instret:95 PC:0x1ffff00000000000000000000800005e0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2161 -instret:96 PC:0x1ffff00000000000000000000800005e4 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 2161 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85e0 } - 21620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h85ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 21620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } -instret:97 PC:0x1ffff00000000000000000000800005e8 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2162 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 21630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h85f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21630 : [doRespLdForward] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 62 <= 40000000000000000000ffff1fffff44000000 - 21630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } - 21630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 21630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h85e8 } - 21640 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000020000402000000001fffff44000000 - 21640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 21640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 21650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } - 21650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:98 PC:0x1ffff00000000000000000000800005ec instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2165 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000034 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 21660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f3c, shiftedBE: tagged DataMemAccess , pcHash: 'h8602 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:99 PC:0x1ffff00000000000000000000800005f0 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2166 -calling cycle -[RFile] wr_ 1: r 5d <= 40000000200004020000ffff1fffff44000000 - 21670 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 21670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 21670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000000000001fffff44000000 - 21680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 21680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc -instret:100 PC:0x1ffff00000000000000000000800005f4 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 2168 -calling cycle -[RFile] wr_ 1: r 6e <= 0000000020000185000000001fffff44000000 - 21690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 21690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h860e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 21690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:101 PC:0x1ffff00000000000000000000800005f8 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2169 -instret:102 PC:0x1ffff00000000000000000000800005fc instr:0x00004531 iType:Alu [doCommitNormalInst [1]] 2169 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000006c00000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h85f8 } - 21700 : [doRespLdForward] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200004020000ffff1fffff44000000 - 21700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 21700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } -instret:103 PC:0x1ffff00000000000000000000800005fe instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2170 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000004000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000020000187000000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000648; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } - 21720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85fe } - 21720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 21720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } -instret:104 PC:0x1ffff0000000000000000000080000602 instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2172 -instret:105 PC:0x1ffff0000000000000000000080000606 instr:0x0000253d iType:Alu [doCommitNormalInst [1]] 2172 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 21740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } - 21740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:106 PC:0x1ffff0000000000000000000080000608 instr:0x00009941 iType:Alu [doCommitNormalInst [0]] 2174 -instret:107 PC:0x1ffff000000000000000000008000060a instr:0xfca42623 iType:St [doCommitNormalInst [1]] 2174 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h860a } - 21750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } -calling cycle - 21760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } - 21760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:108 PC:0x1ffff000000000000000000008000060e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2176 -instret:109 PC:0x1ffff0000000000000000000080000612 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2176 -calling cycle -instret:110 PC:0x1ffff0000000000000000000080000614 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2177 -instret:111 PC:0x1ffff0000000000000000000080000618 instr:0x034080e7 iType:Jr [doCommitNormalInst [1]] 2177 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 21800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 00000000200003bc000000001fffff44000000 - 21810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000061c o: 'h000000008000061c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 21810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 00000000200003cc000000001fffff44000000 - 21820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 21820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 21820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:112 PC:0x1ffff0000000000000000000080000648 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2182 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 21830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 21830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f0c -After delta: vaddr = 0x80000f0c - 21830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:113 PC:0x1ffff000000000000000000008000064a instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2183 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h864a } - 21840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 21840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } -instret:114 PC:0x1ffff000000000000000000008000064c instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2184 -instret:115 PC:0x1ffff000000000000000000008000064e instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2184 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 21850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f0c -After delta: vaddr = 0x80000f0c - 21850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:116 PC:0x1ffff0000000000000000000080000650 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2185 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h864c } - 21860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8658 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 21860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 - 21860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } -instret:117 PC:0x1ffff0000000000000000000080000654 instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 2186 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 21870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h865c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21870 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 76 <= 40000000200004020000ffff1fffff44000000 - 21870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 21870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 21880 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8650 } - 21880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8668 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21880 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 - 21880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 21880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 21890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h866c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 21890 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } -instret:118 PC:0x1ffff0000000000000000000080000658 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2189 -calling cycle -[RFile] wr_ 0: r 7a <= 00000000200003cc000000001fffff44000000 - 21900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 21900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h866e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21900 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff48000608 - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 21900 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 - 21900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } -instret:119 PC:0x1ffff000000000000000000008000065c instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2190 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 40000000200004020000ffff1fffff44000000 - 21910 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000020000187000000001fffff44000000 - 21910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 21910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 21910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 21910 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 21910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21920 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 21920 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 00000000200003dc000000001fffff44000000 - 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } - 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:120 PC:0x1ffff0000000000000000000080000660 instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2192 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8654 } - 21930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } -instret:121 PC:0x1ffff0000000000000000000080000664 instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2193 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } - 21940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h9f80000000000000 b: 'h6080000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } - 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 21940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8664 } - 21950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 21960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8620 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } - 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 21960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 21960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 21970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h862c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 21970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 21970 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 21970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 21980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21980 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000180000000001fffff44000000 - 21980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 21980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21990 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff48000608 - 21990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 21990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 21990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 21990 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 21990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 21990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22000 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 - 22000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 22000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 22020 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 - 22090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 22100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 22100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22110 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 22110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8668 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 22110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } -calling cycle - 22120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 22120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h866c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 22120 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } -calling cycle -[RFile] wr_ 1: r 7a <= 00000000200003cc000000001fffff44000000 - 22130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 22130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h866e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22130 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004020000ffff1fffff44000000 - 22130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 22130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 22130 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 22130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 22140 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000020000187000000001fffff44000000 - 22140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 22140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 22140 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 22140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22150 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 00000000200003dc000000001fffff44000000 -instret:122 PC:0x1ffff0000000000000000000080000668 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2215 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:123 PC:0x1ffff000000000000000000008000066c instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2216 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000020000402000000001fffff44000000 -[ALU redirect - 1] 'h1ffff000000000000000000008000061c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } - 22170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x00000000 -After delta: vaddr = 0x00000000 - 22170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:124 PC:0x1ffff000000000000000000008000066e instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2217 -instret:125 PC:0x1ffff0000000000000000000080000670 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2217 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:126 PC:0x1ffff0000000000000000000080000672 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2219 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 22250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 22270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8620 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } -instret:127 PC:0x1ffff000000000000000000008000061c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2227 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h861c } - 22280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 22280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 22280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 22280 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 22280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 22280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h862c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 22290 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000180000000001fffff44000000 - 22290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } - 22290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 22290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 22300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22300 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004020000ffff1fffff44000000 - 22300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 22310 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 22310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:128 PC:0x1ffff0000000000000000000080000620 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2231 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000180000000001fffff44000000 - 22320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22320 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 - 22320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000600 o: 'h0000000000000600 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 22320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle - 22330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 22330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22330 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 22330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:129 PC:0x1ffff0000000000000000000080000624 instr:0xfe85055b iType:Cap [doCommitNormalInst [0]] 2233 -calling cycle -[RFile] wr_ 1: r 43 <= 00000000200003dc000000001fffff44000000 - 22340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 22340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22340 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004020000ffff1fffff44000000 - 22340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -instret:130 PC:0x1ffff0000000000000000000080000628 instr:0xfca43023 iType:St [doCommitNormalInst [0]] 2234 -calling cycle -[RFile] wr_ 0: r 0b <= 40000000200004021008ffff1ffff804021008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 22350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8628 } - 22350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22350 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 22360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22360 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000020000147000000001fffff44000000 - 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22360 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 22360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } -instret:131 PC:0x1ffff000000000000000000008000062c instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2236 -calling cycle - 22370 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000020000400000000001fffff44000000 - 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } - 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 22490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 22500 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 22500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 22500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22510 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000180000000001fffff44000000 - 22510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 22510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 22520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22520 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -calling cycle -[RFile] wr_ 0: r 43 <= 00000000200003dc000000001fffff44000000 - 22530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 22530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22530 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004020000ffff1fffff44000000 - 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22530 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 22530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -instret:132 PC:0x1ffff0000000000000000000080000630 instr:0xfc043583 iType:Ld [doCommitNormalInst [0]] 2253 -calling cycle -[RFile] wr_ 1: r 0b <= 40000000200004021008ffff1ffff805821008 - 22540 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000020000147000000001fffff44000000 - 22540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22540 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 22540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 22550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22550 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000020000400000000001fffff44000000 -instret:133 PC:0x1ffff0000000000000000000080000634 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 2255 -calling cycle -instret:134 PC:0x1ffff0000000000000000000080000638 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2256 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } -[ALU redirect - 0] 'h1ffff000000000000000000008000051c; 'h0; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8638 } - 22570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } - 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 22590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 22680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 22690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 22690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 22700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 22700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle - 22710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 22710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 22710 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -calling cycle -[RFile] wr_ 1: r 43 <= 00000000200003dc000000001fffff44000000 - 22720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 22720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22720 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004021008ffff1ffff805821008 - 22720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 22720 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 22720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 22730 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000020000147000000001fffff44000000 - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 22730 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22740 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000020000400000000001fffff44000000 -instret:135 PC:0x1ffff000000000000000000008000063c instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2274 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:136 PC:0x1ffff0000000000000000000080000640 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2275 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000051c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:137 PC:0x1ffff0000000000000000000080000642 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2276 -instret:138 PC:0x1ffff0000000000000000000080000644 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2276 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:139 PC:0x1ffff0000000000000000000080000646 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000300 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000a4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 -calling cycle - 22860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc -calling cycle -[RFile] wr_ 1: r 4d <= 00000000000000c0000000001fffff44000000 - 22870 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000020000149000000001fffff44000000 -instret:140 PC:0x1ffff000000000000000000008000051c instr:0xfaa44823 iType:St [doCommitNormalInst [0]] 2288 -instret:141 PC:0x1ffff0000000000000000000080000520 instr:0x30000513 iType:Alu [doCommitNormalInst [1]] 2288 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h155 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 000000002000014b000000001fffff44000000 -[ALU redirect - 0] 'h1ffff00000000000000000000800005c8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h851c } - 22890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h851c } -instret:142 PC:0x1ffff0000000000000000000080000524 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2289 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 22910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h851c } - 22910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:143 PC:0x1ffff0000000000000000000080000528 instr:0x0a4080e7 iType:Jr [doCommitNormalInst [0]] 2291 -calling cycle -calling cycle - 22930 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h851c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 22970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 00000000200003cc000000001fffff44000000 - 22980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000052c o: 'h000000008000052c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 22980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 00000000200003dc000000001fffff44000000 - 22990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 22990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 22990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:144 PC:0x1ffff00000000000000000000800005c8 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2299 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 23000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000300 o: 'h0000000000000300 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 23000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:145 PC:0x1ffff00000000000000000000800005ca instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2300 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000020000176000000001fffff44000000 - 23010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 23010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 23010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:146 PC:0x1ffff00000000000000000000800005cc instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2301 -instret:147 PC:0x1ffff00000000000000000000800005ce instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2301 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 00000000200003b4000000001fffff44000000 -[RFile] wr_ 1: r 54 <= 0000000020000178000000001fffff44000000 - 23020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 23020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h85d4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005e0 o: 'h00000000800005e0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 -instret:148 PC:0x1ffff00000000000000000000800005d0 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2302 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 23030 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 00000000000000c0000000001fffff44000000 - 23030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h359 }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 23040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 23040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000300 o: 'h0000000000000300 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 23050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:149 PC:0x1ffff00000000000000000000800005d4 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2305 -instret:150 PC:0x1ffff00000000000000000000800005d8 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2305 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000001c00000001fffff44000000 - 23060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 23060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 -instret:151 PC:0x1ffff00000000000000000000800005dc instr:0x0c6080e7 iType:Jr [doCommitNormalInst [0]] 2306 -instret:152 PC:0x1ffff000000000000000000008000069e instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2306 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 23070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 23070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h86aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:153 PC:0x1ffff00000000000000000000800006a0 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2307 -instret:154 PC:0x1ffff00000000000000000000800006a2 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2307 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h003 } - 23080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h86c6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23080 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 00000000000000c0000000001fffff44000000 -instret:155 PC:0x1ffff00000000000000000000800006a4 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2308 -instret:156 PC:0x1ffff00000000000000000000800006a6 instr:0xfea43023 iType:St [doCommitNormalInst [1]] 2308 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23090 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 00000000000000c0000000001fffff44000000 - 23090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 -instret:157 PC:0x1ffff00000000000000000000800006aa instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2310 -instret:158 PC:0x1ffff00000000000000000000800006ae instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2310 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff924 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 3fffffffffffff400fff00001fffff44000000 - 23120 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h004 } - 23120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h86dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } -instret:159 PC:0x1ffff00000000000000000000800006b0 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2312 -instret:160 PC:0x1ffff00000000000000000000800006b4 instr:0x0120006f iType:J [doCommitNormalInst [1]] 2312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h37e }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 0000000000000000000000001fffff44000000 - 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86dc } - 23130 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 23130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:161 PC:0x1ffff00000000000000000000800006c6 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2313 -instret:162 PC:0x1ffff00000000000000000000800006ca instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2313 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 00000000200405b9000000001fffff44000000 -[RFile] wr_ 1: r 64 <= 00000000000000c0000000001fffff44000000 - 23140 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000182000000001fffff44000000 - 23140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 - 23140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:163 PC:0x1ffff00000000000000000000800006cc instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2314 -instret:164 PC:0x1ffff00000000000000000000800006ce instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2314 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000007c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 00000000000000c2000000001fffff44000000 -[RFile] wr_ 1: r 6a <= 0000000020040402000000001fffff44000000 - 23150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h002 } - 23150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f08, shiftedBE: tagged DataMemAccess , pcHash: 'h86f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000308 o: 'h0000000000000308 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } -instret:165 PC:0x1ffff00000000000000000000800006d0 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2315 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23160 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } - 23160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000608 o: 'h0000000000000608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } - 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f4 } - 23160 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 23160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 -instret:166 PC:0x1ffff00000000000000000000800006d2 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2316 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 00000000200003cc000000001fffff44000000 - 23170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 23170 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000020040402000000001fffff44000000 - 23170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:167 PC:0x1ffff00000000000000000000800006d4 instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2317 -instret:168 PC:0x1ffff00000000000000000000800006d8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2317 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h026 }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 000000002004020e800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 23180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 23180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 23180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000020040400000000001fffff44000000 - 23190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000079e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23200 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 23200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h86f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f08, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 23210 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h001 } - 23210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8842 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 23210 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000020040218800000001fffff44000000 - 23220 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h001 } - 23220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8848 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23220 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000000000001fffff44000000 - 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 23220 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 23220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000020040400000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23230 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000020000582000000001fffff44000000 - 23230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23240 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } - 23240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h886a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23240 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000182000000001fffff44000000 - 23240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23250 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } - 23250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8870 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 23250 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 3ffffffffffffe4a0fff00001fffff44000000 - 23260 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h002 } - 23260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8872 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23260 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000020000582000000001fffff44000000 - 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 23260 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 23260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 3ffffffffffffe420fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23270 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000020000582000000001fffff44000000 - 23270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23280 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h002 } - 23280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h887e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23280 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000182000000001fffff44000000 - 23280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 23290 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000182000000001fffff44000000 - 23290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 23300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8882 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000020000704000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23310 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000020000582000000001fffff44000000 - 23310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001c10 o: 'h0000000080001c10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23320 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h000 } - 23320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001608 -After delta: vaddr = 0x80001608 - 23320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 23330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8888 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000608 o: 'h0000000000000608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001608, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 23330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 23350 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 23410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h851c } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85ca } - 23430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ed8 -After delta: vaddr = 0x80000ed8 - 23430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff924 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ed8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } - 23440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ca } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23450 : [doFinishMem] DTlbResp { resp: <'h0000000080000ed8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ed8 o: 'h0000000080000ed8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ed8, check_high: 'h00000000080000ee0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85cc } - 23450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000ed8, shiftedBE: tagged DataMemAccess , pcHash: 'h86dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h37d }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 00000000200405b9000000001fffff44000000 - 23460 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 00000000000000c2000000001fffff44000000 - 23460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } - 23460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85cc } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 - 23460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000020040402000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85d0 } - 23470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000007c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 23480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000308 o: 'h0000000000000308 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85d0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f08 -After delta: vaddr = 0x80000f08 -instret:169 PC:0x1ffff00000000000000000000800006dc instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2348 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23490 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a0 } - 23490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f08, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003cc000000001fffff44000000 - 23500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f08,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f08 o: 'h0000000080000f08 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f08, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 23500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f08, shiftedBE: tagged DataMemAccess , pcHash: 'h86f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } - 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:170 PC:0x1ffff00000000000000000000800006e0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2350 -instret:171 PC:0x1ffff00000000000000000000800006e4 instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2350 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h026 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 000000002004020e800000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a2 } - 23510 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000020040402000000001fffff44000000 - 23510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } -instret:172 PC:0x1ffff00000000000000000000800006e8 instr:0x92450513 iType:Alu [doCommitNormalInst [0]] 2351 -instret:173 PC:0x1ffff00000000000000000000800006ec instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2351 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000020040400000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f08, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } - 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 23520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:174 PC:0x1ffff00000000000000000000800006f0 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2352 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000079e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23530 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86a6 } - 23530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8842 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } -instret:175 PC:0x1ffff00000000000000000000800006f4 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2353 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23540 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 23540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h86f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8842 } - 23540 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 23540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 0000000020040218800000001fffff44000000 - 23550 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h002 } - 23550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8848 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23550 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000020000582000000001fffff44000000 - 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86f8 } - 23550 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 23550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000020040400000000001fffff44000000 - 23560 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000000000001fffff44000000 - 23560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } - 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23570 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ed8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86d4 } - 23570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h886a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23570 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 00000000000000c2000000001fffff44000000 - 23570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 3ffffffffffffe4a0fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23580 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h003 } - 23580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080101000, shiftedBE: tagged DataMemAccess , pcHash: 'h8870 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886a } - 23580 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } -instret:176 PC:0x1ffff00000000000000000000800006f8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2358 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 3ffffffffffffe420fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23590 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h003 } - 23590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h8872 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23590 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000020000582000000001fffff44000000 - 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080101000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8870 } - 23590 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef8 -After delta: vaddr = 0x80000ef8 - 23590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23600 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000020000582000000001fffff44000000 - 23600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } - 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86d4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:177 PC:0x1ffff00000000000000000000800006fa instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2360 -instret:178 PC:0x1ffff00000000000000000000800006fc instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2360 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23610 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86e0 } - 23610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h887e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23610 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 00000000000000c2000000001fffff44000000 - 23610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } -instret:179 PC:0x1ffff0000000000000000000080000838 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2361 -instret:180 PC:0x1ffff000000000000000000008000083a instr:0x00100597 iType:Auipc [doCommitNormalInst [1]] 2361 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 23620 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 00000000000000c2000000001fffff44000000 - 23620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } - 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86e0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:181 PC:0x1ffff000000000000000000008000083e instr:0x7c658593 iType:Alu [doCommitNormalInst [0]] 2362 -instret:182 PC:0x1ffff0000000000000000000080000842 instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2362 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f08, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h86ec } - 23630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8882 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101000 -After delta: vaddr = 0x80101000 - 23630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } -instret:183 PC:0x1ffff0000000000000000000080000844 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2363 -instret:184 PC:0x1ffff0000000000000000000080000846 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2363 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000020000644000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080101000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23640 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000020000582000000001fffff44000000 - 23640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001910 o: 'h0000000080001910 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } - 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h86ec } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:185 PC:0x1ffff0000000000000000000080000848 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2364 -instret:186 PC:0x1ffff000000000000000000008000084c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2364 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23650 : [doFinishMem] DTlbResp { resp: <'h0000000080101000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101000 o: 'h0000000080101000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101000, check_high: 'h00000000080101008, check_inclusive: True } }, specBits: 'h000 } - 23650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f00, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001608 -After delta: vaddr = 0x80001608 - 23650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:187 PC:0x1ffff0000000000000000000080000850 instr:0x0120006f iType:J [doCommitNormalInst [0]] 2365 -instret:188 PC:0x1ffff0000000000000000000080000862 instr:0x00100517 iType:Auipc [doCommitNormalInst [1]] 2365 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f00,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f00 o: 'h0000000080000f00 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f00, check_high: 'h00000000080000f08, check_inclusive: True } }, specBits: 'h000 } - 23660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f00, shiftedBE: tagged DataMemAccess , pcHash: 'h8888 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000308 o: 'h0000000000000308 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001608, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 23660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:189 PC:0x1ffff0000000000000000000080000866 instr:0x79e50593 iType:Alu [doCommitNormalInst [0]] 2366 -instret:190 PC:0x1ffff000000000000000000008000086a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2366 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23670 : [doFinishMem] DTlbResp { resp: <'h0000000080001608,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001608, check_high: 'h00000000080001610, check_inclusive: True } }, specBits: 'h000 } - 23670 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000020000582000000001fffff44000000 - 23670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 23670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:191 PC:0x1ffff000000000000000000008000086c instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2367 -instret:192 PC:0x1ffff0000000000000000000080000870 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2367 -calling cycle -[RFile] wr_ 0: r 49 <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h886c } - 23680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8896 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 23680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } -instret:193 PC:0x1ffff0000000000000000000080000872 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2368 -instret:194 PC:0x1ffff0000000000000000000080000876 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2368 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 23690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 23690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h889a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8896 } - 23690 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 23690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 23690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } -instret:195 PC:0x1ffff0000000000000000000080000878 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2369 -instret:196 PC:0x1ffff000000000000000000008000087a instr:0x0040006f iType:J [doCommitNormalInst [1]] 2369 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff90, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000020000584000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f00, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 23700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h889c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23700 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 3fffc000000000000fff00001fffff44000000 - 23700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 23700 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 23700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } -instret:197 PC:0x1ffff000000000000000000008000087e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2370 -instret:198 PC:0x1ffff0000000000000000000080000882 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2370 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff80, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 23710 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000178000000001fffff44000000 - 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 23710 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 23710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } -instret:199 PC:0x1ffff0000000000000000000080000886 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2371 -instret:200 PC:0x1ffff0000000000000000000080000888 instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 2371 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h2a0 }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000000000000001fffff44000000 - 23720 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 00000000200003dc000000001fffff44000000 - 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } - 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h886c } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:201 PC:0x1ffff000000000000000000008000088c instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2372 -instret:202 PC:0x1ffff000000000000000000008000088e instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2372 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080101000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8878 } - 23730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 23730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff90, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } -instret:203 PC:0x1ffff0000000000000000000080000892 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2373 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff00000000000000000000800005e0; 'h1; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } - 23740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffff000000000000 o: 'hffff000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } - 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8878 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 23740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff90, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f00 -After delta: vaddr = 0x80000f00 - 23740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff80, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001608, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8886 } - 23750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } - 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 23780 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001608, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 23850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 23870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 23870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8896 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 -calling cycle - 23880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 23880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h889a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23880 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000020000584000000001fffff44000000 - 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000ed0 o: 'h0000000080000ed0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } -calling cycle -[RFile] wr_ 1: r 49 <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 23890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h889c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889a } - 23890 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } -calling cycle - 23900 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000178000000001fffff44000000 - 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h889c } - 23900 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:204 PC:0x1ffff0000000000000000000080000896 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2390 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23910 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 00000000200003dc000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:205 PC:0x1ffff000000000000000000008000089a instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2392 -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800005e0; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:206 PC:0x1ffff000000000000000000008000089c instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2393 -instret:207 PC:0x1ffff000000000000000000008000089e instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2393 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:208 PC:0x1ffff00000000000000000000800008a0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 24020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 40000000000000000000ffff1fffff44000000 - 24040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 24040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 -instret:209 PC:0x1ffff00000000000000000000800005e0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2405 -instret:210 PC:0x1ffff00000000000000000000800005e4 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 2405 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h85ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 24060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:211 PC:0x1ffff00000000000000000000800005e8 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2406 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f58, check_inclusive: True } }, specBits: 'h000 } - 24070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h85f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24070 : [doRespLdForward] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000000000000000ffff1fffff44000000 - 24070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 24070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 24080 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000020000584000000001fffff44000000 - 24080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 24090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:212 PC:0x1ffff00000000000000000000800005ec instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2409 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000034 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 24100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f3c, shiftedBE: tagged DataMemAccess , pcHash: 'h8602 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:213 PC:0x1ffff00000000000000000000800005f0 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2410 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 40000000200005840000ffff1fffff44000000 - 24110 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000000000001fffff44000000 - 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:214 PC:0x1ffff00000000000000000000800005f4 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 2412 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000020000185000000001fffff44000000 - 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h860e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 24130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:215 PC:0x1ffff00000000000000000000800005f8 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2413 -instret:216 PC:0x1ffff00000000000000000000800005fc instr:0x00004531 iType:Alu [doCommitNormalInst [1]] 2413 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000006c00000001fffff44000000 -[RFile] wr_ 1: r 66 <= 00000000200003bc000000001fffff44000000 - 24140 : [doRespLdForward] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200005840000ffff1fffff44000000 - 24140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f3c -After delta: vaddr = 0x80000f3c - 24140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:217 PC:0x1ffff00000000000000000000800005fe instr:0xfca42623 iType:St [doCommitNormalInst [0]] 2414 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000004000000001fffff44000000 -[RFile] wr_ 1: r 4f <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } - 24150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f3c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 24150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000020000187000000001fffff44000000 - 24160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f3c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f3c o: 'h0000000080000f3c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f3c, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 24160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000061c o: 'h000000008000061c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 24160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:218 PC:0x1ffff0000000000000000000080000602 instr:0xfcc42503 iType:Ld [doCommitNormalInst [0]] 2416 -instret:219 PC:0x1ffff0000000000000000000080000606 instr:0x0000253d iType:Alu [doCommitNormalInst [1]] 2416 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 24170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f0c -After delta: vaddr = 0x80000f0c - 24170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:220 PC:0x1ffff0000000000000000000080000608 instr:0x00009941 iType:Alu [doCommitNormalInst [0]] 2417 -instret:221 PC:0x1ffff000000000000000000008000060a instr:0xfca42623 iType:St [doCommitNormalInst [1]] 2417 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 24180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 24180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 24180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 24190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f0c -After delta: vaddr = 0x80000f0c - 24190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:222 PC:0x1ffff000000000000000000008000060e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2419 -instret:223 PC:0x1ffff0000000000000000000080000612 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2419 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 24200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8658 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 24200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 - 24200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:224 PC:0x1ffff0000000000000000000080000614 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2420 -instret:225 PC:0x1ffff0000000000000000000080000618 instr:0x034080e7 iType:Jr [doCommitNormalInst [1]] 2420 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 24210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 } - 24210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess , pcHash: 'h865c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24210 : [doRespLdForward] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200005840000ffff1fffff44000000 - 24210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 24210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:226 PC:0x1ffff0000000000000000000080000648 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2421 -instret:227 PC:0x1ffff000000000000000000008000064a instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 2421 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24220 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 24220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8668 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24220 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000000000001fffff44000000 - 24220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 24220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } -instret:228 PC:0x1ffff000000000000000000008000064c instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2422 -instret:229 PC:0x1ffff000000000000000000008000064e instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2422 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 24230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 24230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h866c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 24230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8668 } - 24230 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 24230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:230 PC:0x1ffff0000000000000000000080000650 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2423 -instret:231 PC:0x1ffff0000000000000000000080000654 instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 2423 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 24240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h866e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24240 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000402000000001fffff48000308 - 24240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 -instret:232 PC:0x1ffff0000000000000000000080000658 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2424 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 40000000200005840000ffff1fffff44000000 - 24250 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000020000187000000001fffff44000000 - 24250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:233 PC:0x1ffff000000000000000000008000065c instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2425 -calling cycle - 24260 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001608, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 24260 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 24260 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 00000000200003dc000000001fffff44000000 -instret:234 PC:0x1ffff0000000000000000000080000660 instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2426 -calling cycle - 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8886 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:235 PC:0x1ffff0000000000000000000080000664 instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2427 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h888e } - 24280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'hcf80000080001008 b: 'h3080000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h888e } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85e0 } - 24300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8620 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h862c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 24310 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 24320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24320 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 00000000000000c0000000001fffff44000000 - 24320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } - 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 24320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h85e8 } - 24330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24330 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000020000402000000001fffff48000308 - 24330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24330 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 24330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } -calling cycle -calling cycle - 24350 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 24350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } - 24350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85e8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h85f8 } - 24360 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 24360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } -calling cycle - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85f8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85fe } - 24380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } -calling cycle - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85fe } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f3c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h860a } - 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } -calling cycle - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f3c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h860a } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h864a } - 24420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ef0 -After delta: vaddr = 0x80000ef0 - 24430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h864c } - 24440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 24440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24450 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } - 24450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess , pcHash: 'h8668 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 24450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h864c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 -calling cycle - 24460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8650 } - 24460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h866c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24460 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200005840000ffff1fffff44000000 - 24460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } -calling cycle -[RFile] wr_ 1: r 6a <= 00000000200003cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 24470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 24470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h866e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866c } - 24470 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } -calling cycle - 24480 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000020000187000000001fffff44000000 - 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h866e } - 24480 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 24480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } -instret:236 PC:0x1ffff0000000000000000000080000668 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2448 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24490 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 00000000200003dc000000001fffff44000000 - 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } - 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8650 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8654 } - 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } -instret:237 PC:0x1ffff000000000000000000008000066c instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2450 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000061c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8654 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:238 PC:0x1ffff000000000000000000008000066e instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2451 -instret:239 PC:0x1ffff0000000000000000000080000670 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2451 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8664 } - 24520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8664 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:240 PC:0x1ffff0000000000000000000080000672 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 24630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h8620 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } -instret:241 PC:0x1ffff000000000000000000008000061c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2463 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h861c } - 24640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8620 } - 24640 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 24640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h862c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 24650 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 00000000000000c0000000001fffff44000000 - 24650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } - 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h861c } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 24660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24660 : [doRespLdForward] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200005840000ffff1fffff44000000 - 24660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24670 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 24670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:242 PC:0x1ffff0000000000000000000080000620 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2467 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 00000000000000c0000000001fffff44000000 - 24680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24680 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000180000000001fffff44000000 - 24680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000300 o: 'h0000000000000300 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 24680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle - 24690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 24690 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 24690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 24690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:243 PC:0x1ffff0000000000000000000080000624 instr:0xfe85055b iType:Cap [doCommitNormalInst [0]] 2469 -calling cycle -[RFile] wr_ 1: r 76 <= 00000000200003dc000000001fffff44000000 - 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24700 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200005840000ffff1fffff44000000 - 24700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -instret:244 PC:0x1ffff0000000000000000000080000628 instr:0xfca43023 iType:St [doCommitNormalInst [0]] 2470 -calling cycle -[RFile] wr_ 0: r 4b <= 40000000200005841610ffff1ffff807041610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 24710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8628 } - 24710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001c10 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 24710 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 24720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24720 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 000000002000014b000000001fffff44000000 - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 24720 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } -instret:245 PC:0x1ffff000000000000000000008000062c instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2472 -calling cycle - 24730 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000400000000001fffff44000000 - 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } - 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8628 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 24850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8630 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8630 } - 24860 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 24860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24870 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 00000000000000c0000000001fffff44000000 - 24870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 24870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 24880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 24880 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -calling cycle -[RFile] wr_ 0: r 76 <= 00000000200003dc000000001fffff44000000 - 24890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 24890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24890 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200005840000ffff1fffff44000000 - 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 24890 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 24890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -instret:246 PC:0x1ffff0000000000000000000080000630 instr:0xfc043583 iType:Ld [doCommitNormalInst [0]] 2489 -calling cycle -[RFile] wr_ 1: r 4b <= 40000000200005841610ffff1ffff806441610 - 24900 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 000000002000014b000000001fffff44000000 - 24900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 24900 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 24910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 24910 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000400000000001fffff44000000 -instret:247 PC:0x1ffff0000000000000000000080000634 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 2491 -calling cycle -instret:248 PC:0x1ffff0000000000000000000080000638 instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2492 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } -[ALU redirect - 0] 'h1ffff000000000000000000008000052c; 'h0; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8638 } - 24930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } - 24950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8638 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 24950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 25040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 25050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 25050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 25060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h863c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 25060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } -calling cycle - 25070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 25070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8640 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h863c } - 25070 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } -calling cycle -[RFile] wr_ 1: r 76 <= 00000000200003dc000000001fffff44000000 - 25080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 25080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8642 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25080 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200005841610ffff1ffff806441610 - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8640 } - 25080 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 25090 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 000000002000014b000000001fffff44000000 - 25090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 25090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8642 } - 25090 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 25090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25100 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000400000000001fffff44000000 -instret:249 PC:0x1ffff000000000000000000008000063c instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2510 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:250 PC:0x1ffff0000000000000000000080000640 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2511 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000052c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:251 PC:0x1ffff0000000000000000000080000642 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2512 -instret:252 PC:0x1ffff0000000000000000000080000644 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2512 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:253 PC:0x1ffff0000000000000000000080000646 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff90, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 25210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff90, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff80, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 25220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff90, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 25220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff80, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h2a0 }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000000000000001fffff44000000 - 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 25230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff90, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 25230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff80, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 25240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff80, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 -instret:254 PC:0x1ffff000000000000000000008000052c instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2524 -instret:255 PC:0x1ffff0000000000000000000080000530 instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 2524 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h852c } - 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 25250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } -instret:256 PC:0x1ffff0000000000000000000080000534 instr:0xf8b44823 iType:St [doCommitNormalInst [0]] 2525 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 25260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h853c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } - 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h852c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 25260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h853c } -instret:257 PC:0x1ffff0000000000000000000080000538 instr:0xf8b44023 iType:St [doCommitNormalInst [0]] 2526 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8534 } - 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h853c } - 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h853c } - 25270 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 25270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8534 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25280 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8534 } - 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8534 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8538 } - 25290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8538 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8538 } - 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8538 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:258 PC:0x1ffff000000000000000000008000053c instr:0xfb04250f iType:Ld [doCommitNormalInst [0]] 2530 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000548; 'h0; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:259 PC:0x1ffff0000000000000000000080000540 instr:0x00b51463 iType:Br [doCommitNormalInst [0]] 2533 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h800, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc -calling cycle - 25400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h001 } - 25400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h854c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h854c } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000000000001fffff44000000 - 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h854c } - 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h854c } - 25410 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:260 PC:0x1ffff0000000000000000000080000548 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2541 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25420 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200005841610ffff1ffff806441610 - 25420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff78, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 25430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaae }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 25440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff78, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:261 PC:0x1ffff000000000000000000008000054c instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2544 -instret:262 PC:0x1ffff0000000000000000000080000550 instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 2544 -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000004000000001fffff44000000 - 25450 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h002 } - 25450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8568 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff78, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8568 } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000003000000001fffff44000000 - 25460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff78, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8568 } - 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8568 } - 25460 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:263 PC:0x1ffff0000000000000000000080000554 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 2546 -instret:264 PC:0x1ffff0000000000000000000080000558 instr:0x0100006f iType:J [doCommitNormalInst [1]] 2546 -calling cycle -[RFile] wr_ 1: r 54 <= 000000002000015d000000001fffff44000000 - 25470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 25470 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200004021008ffff1ffff805821008 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[RFile] wr_ 0: r 65 <= 000000002000015f000000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle -instret:265 PC:0x1ffff0000000000000000000080000568 instr:0xfb04250f iType:Ld [doCommitNormalInst [0]] 2550 -instret:266 PC:0x1ffff000000000000000000008000056c instr:0x000045c1 iType:Alu [doCommitNormalInst [1]] 2550 -calling cycle -instret:267 PC:0x1ffff000000000000000000008000056e instr:0x00004631 iType:Alu [doCommitNormalInst [0]] 2551 -instret:268 PC:0x1ffff0000000000000000000080000570 instr:0xf6c43c23 iType:St [doCommitNormalInst [1]] 2551 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8570 } - 25520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8570 } -instret:269 PC:0x1ffff0000000000000000000080000574 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2552 -instret:270 PC:0x1ffff0000000000000000000080000578 instr:0xaae080e7 iType:Jr [doCommitNormalInst [1]] 2552 -calling cycle - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8570 } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8570 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 26000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 00000000200003cc000000001fffff44000000 - 26010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000057c o: 'h000000008000057c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 26010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 00000000200003dc000000001fffff44000000 - 26020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 26020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 26020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:271 PC:0x1ffff0000000000000000000080000022 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 2602 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 26030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 26030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 26030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:272 PC:0x1ffff0000000000000000000080000024 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2603 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } - 26040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 26040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -instret:273 PC:0x1ffff0000000000000000000080000026 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 2604 -instret:274 PC:0x1ffff0000000000000000000080000028 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 2604 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h400, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h10d }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000 - 26050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 26050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } - 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 26050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:275 PC:0x1ffff000000000000000000008000002a instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2605 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } - 26060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 26060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -instret:276 PC:0x1ffff000000000000000000008000002e instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 2606 -calling cycle - 26070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 26070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:277 PC:0x1ffff0000000000000000000080000032 instr:0xfcc42c23 iType:St [doCommitNormalInst [0]] 2607 -instret:278 PC:0x1ffff0000000000000000000080000036 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2607 -calling cycle - 26080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h802a } - 26080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -instret:279 PC:0x1ffff0000000000000000000080000038 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2608 -instret:280 PC:0x1ffff000000000000000000008000003c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2608 -calling cycle - 26090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 26090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26090 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000000000000001fffff44000000 - 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } - 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 26090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802e } - 26100 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 26100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } - 26110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:281 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2611 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8032 } - 26120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } -instret:282 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 2612 -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h1; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } - 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } - 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8038 } - 26140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 26150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } - 26150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:283 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 26920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'ha00, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000000000000001fffff44000000 - 26930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 26930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 26940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:284 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2694 -instret:285 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2694 -calling cycle - 26950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 26950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:286 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2695 -instret:287 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [1]] 2695 -calling cycle - 26960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 26960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26960 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 - 26960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 26970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 26970 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 26970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 26980 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:288 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2698 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -calling cycle - 27000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 27000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:289 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2700 -calling cycle -[ALU redirect - 0] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } - 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27010 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 27030 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:290 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2703 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 27080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 27090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 27100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 27110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 27110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27110 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 27110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:291 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2711 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27120 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 27120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27120 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 27130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27130 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27130 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27140 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27140 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:292 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2714 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27150 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000000000001fffff44000000 - 27150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:293 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2715 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:294 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2716 -calling cycle - 27170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 27170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27180 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 67 <= 0000000000000000000000001fffff44000000 - 27190 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 - 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hd00, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:295 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 2720 -instret:296 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 2720 -calling cycle - 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 - 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 27220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000000000001fffff44000000 - 27230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27230 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 0000000000000000000000001fffff44000000 - 27240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27240 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 - 27240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001008 -After delta: vaddr = 0x80001008 - 27240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:297 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2724 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 40000000200004021008ffff1ffff805821008 - 27250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27250 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:298 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 2725 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27260 : [doFinishMem] DTlbResp { resp: <'h0000000080001008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001008, check_high: 'h00000000080001010, check_inclusive: True } }, specBits: 'h000 } - 27260 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 27260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:299 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 2726 -instret:300 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 2726 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 27270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:301 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 2727 -instret:302 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 2727 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h680, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27280 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:303 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2728 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } - 27290 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 - 27290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:304 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2729 -instret:305 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 2729 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:306 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2731 -instret:307 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 2731 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 27320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -calling cycle -calling cycle - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he80, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle - 27430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27440 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27450 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 27450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27450 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 27450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27460 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 27460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:308 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2747 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 27480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:309 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2748 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h740, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27490 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 27490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 27510 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:310 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2751 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 27560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 27570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 27580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 27580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 27590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 27590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27590 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 27590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:311 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2759 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27600 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 27600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27600 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 27610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27610 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 - 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27610 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27620 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27620 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:312 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2762 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27630 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000400000001fffff44000000 - 27630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:313 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2763 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:314 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2764 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf40, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 27650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 27660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27660 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 27660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 59 <= 0000000000000000000000001fffff44000000 - 27670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 27670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27670 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000400000001fffff44000000 - 27670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 27680 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:315 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 2768 -instret:316 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 2768 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27690 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000400000001fffff44000000 - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 27690 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000000800000001fffff44000000 - 27700 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 27700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000000400000001fffff44000000 - 27710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000002000000001fffff44000000 - 27720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 27720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001010 -After delta: vaddr = 0x80001010 - 27720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:317 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2772 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7a0, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 40000000200004041010ffff1ffff805821008 - 27730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001010 o: 'h0000000000000008 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001010 o: 'h0000000000000008 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001010, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 27730 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 27730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:318 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 2773 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 27740 : [doFinishMem] DTlbResp { resp: <'h0000000080001010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001010 o: 'h0000000000000008 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001010, check_high: 'h00000000080001018, check_inclusive: True } }, specBits: 'h000 } - 27740 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 27740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 27740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:319 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 2774 -instret:320 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 2774 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:321 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 2776 -instret:322 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 2776 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001010, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 27770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:323 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2777 -calling cycle - 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:324 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2778 -instret:325 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 2778 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:326 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2779 -instret:327 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 2779 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 27800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 27810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 27820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 27820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 27830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 27830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 27840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 27840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 27840 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 27850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27850 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200004021008ffff1ffff805821008 - 27850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 27850 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 27860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 27860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27860 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 27860 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27870 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 27870 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 27870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27880 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000800000001fffff44000000 - 27880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfa0, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 27900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle -calling cycle - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 27920 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 27930 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7d0, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 27990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28020 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28030 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000800000001fffff44000000 - 28030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28030 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3e8, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 28040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28040 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 28040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28050 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 28050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 28050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:328 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2805 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h009 } - 28060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28060 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 28060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:329 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2806 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff78, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 28070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } - 28070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h013 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 28070 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 28070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 28070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 28090 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 28090 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 28090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:330 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2809 -calling cycle - 28100 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 28140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 28150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 28160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 28160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 28170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 28170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28170 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 28170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:331 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2817 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28180 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200004021008ffff1ffff805821008 - 28180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28180 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 28190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28190 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 28190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28190 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 28190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28200 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 28200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28200 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 28200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:332 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2820 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28210 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000800000001fffff44000000 - 28210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:333 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2821 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:334 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2822 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbe8, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 28230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 28240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28240 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 76 <= 0000000000000000000000001fffff44000000 - 28250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 28250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28250 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 - 28250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28260 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:335 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 2826 -instret:336 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 2826 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28270 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000800000001fffff44000000 - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28270 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000000c00000001fffff44000000 - 28280 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 28280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000800000001fffff44000000 - 28290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000004000000001fffff44000000 - 28300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 28300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001018 -After delta: vaddr = 0x80001018 - 28300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:337 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2830 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5f4, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 40000000200004061018ffff1ffff805821008 - 28310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001018 o: 'h0000000000000010 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001018 o: 'h0000000000000010 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001018, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28310 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:338 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 2831 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 28320 : [doFinishMem] DTlbResp { resp: <'h0000000080001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001018 o: 'h0000000000000010 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001018, check_high: 'h00000000080001020, check_inclusive: True } }, specBits: 'h000 } - 28320 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 28320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 28320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:339 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 2832 -instret:340 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 2832 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:341 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 2834 -instret:342 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 2834 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001018, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 28350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:343 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2835 -calling cycle - 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:344 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2836 -instret:345 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 2836 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:346 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2837 -instret:347 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 2837 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 28380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 28390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001058, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001058, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 28400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 28410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 28410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 28410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 28420 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001058, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001058, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 28420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 28420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28420 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001098, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 28430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28430 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 28430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28430 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 28430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 28440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28440 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28440 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28450 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28450 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28460 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 - 28460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdf4, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 28480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle -calling cycle - 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28500 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 28510 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6fa, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28600 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28610 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000c00000001fffff44000000 - 28610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28610 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h37d, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 28620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28620 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 28620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28630 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 28630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:348 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2863 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h009 } - 28640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28640 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 28640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 28640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:349 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2864 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 28650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } - 28650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h013 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 28650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 28650 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 28650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 28650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 28670 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 28670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 28670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 28670 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 28670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:350 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2867 -calling cycle - 28680 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 28720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 28730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 28740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 28740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 28750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 28750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 28750 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 28750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:351 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2875 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28760 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 28760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 28760 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 28760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 28770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28770 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 28770 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 28770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28780 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 28780 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:352 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2878 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28790 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 - 28790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:353 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2879 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:354 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2880 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb7d, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 28810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 28820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 28820 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 60 <= 0000000000000000000000001fffff44000000 - 28830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 28830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28830 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000c00000001fffff44000000 - 28830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 28840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 28840 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 28840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:355 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 2884 -instret:356 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 2884 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28850 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000c00000001fffff44000000 - 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 28850 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 28850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 28850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000001000000001fffff44000000 - 28860 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 28860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000c00000001fffff44000000 - 28870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 28870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000006000000001fffff44000000 - 28880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 28880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001020 -After delta: vaddr = 0x80001020 - 28880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:357 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2888 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5be, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 40000000200004081020ffff1ffff805821008 - 28890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001020 o: 'h0000000000000018 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001020 o: 'h0000000000000018 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001020, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 28890 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 28890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:358 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 2889 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28900 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001058, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 28900 : [doFinishMem] DTlbResp { resp: <'h0000000080001020,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001020 o: 'h0000000000000018 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001020, check_high: 'h00000000080001028, check_inclusive: True } }, specBits: 'h000 } - 28900 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 28900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 28900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:359 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 2890 -instret:360 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 2890 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001058, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 28920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:361 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 2892 -instret:362 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 2892 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001020, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 28930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:363 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2893 -calling cycle - 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:364 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2894 -instret:365 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 2894 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:366 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2895 -instret:367 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 2895 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 28960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 28970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 28980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 28980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 28990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 28990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 29000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 29000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29000 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 29000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29010 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200004021008ffff1ffff805821008 - 29010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29010 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 29010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 29020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29020 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29020 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 29020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29030 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 29030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29030 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 29030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29040 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001000000001fffff44000000 - 29040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdbe, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 29060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle -calling cycle - 29080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29080 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 29080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 29090 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6df, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 29180 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 29180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29190 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001000000001fffff44000000 - 29190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29190 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h36f, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 29200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29200 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 29200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29210 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001098, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29210 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 29210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:368 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2921 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h009 } - 29220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29220 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 29220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 29220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:369 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2922 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 29230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } - 29230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h013 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 29230 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 29230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 29250 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 29250 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:370 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2925 -calling cycle - 29260 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 29300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 29310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 29320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 29320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 29330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 29330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29330 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 29330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:371 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2933 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29340 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200004021008ffff1ffff805821008 - 29340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29340 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 29340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 29350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29350 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29350 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 29350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29360 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29360 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:372 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2936 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29370 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001000000001fffff44000000 - 29370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:373 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2937 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:374 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb6f, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 29390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 29400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29400 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 29400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 73 <= 0000000000000000000000001fffff44000000 - 29410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 29410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29410 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001000000001fffff44000000 - 29410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fcc, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } + 29380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fcc +After delta: vaddr = 0x80000fcc + 29380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fcc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fcc, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h001 } + 29390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000000c00000001fffff44000000 + 29390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fcc, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe8 +After delta: vaddr = 0x80000fe8 +instret:488 PC:0x1ffff0000000000000000000080001186 instr:0xfe442503 iType:Ld [doCommitNormalInst [0]] 2939 +instret:489 PC:0x1ffff000000000000000000008000118a instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2939 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fcc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fcc, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h001 } + 29400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fcc, shiftedBE: tagged DataMemAccess , pcHash: 'h9212 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:490 PC:0x1ffff000000000000000000008000118e instr:0xe7658593 iType:Alu [doCommitNormalInst [0]] 2940 +calling cycle + 29410 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe8, check_high: 'h00000000080000fec, check_inclusive: True } }, specBits: 'h001 } + 29410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fe8, shiftedBE: tagged DataMemAccess , pcHash: 'h9216 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29410 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 + 29410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } +instret:491 PC:0x1ffff0000000000000000000080001192 instr:0x0000418c iType:Ld [doCommitNormalInst [0]] 2941 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe08 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fcc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff000000000000000000008000119c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 29420 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:375 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 2942 -instret:376 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 2942 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } + 29420 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 29430 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001000000001fffff44000000 - 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29430 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 29430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 29440 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +instret:492 PC:0x1ffff0000000000000000000080001194 instr:0x00b54463 iType:Br [doCommitNormalInst [0]] 2944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe80 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1f}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003ff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 0000000020040868000000001fffff44000000 + 29980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80102020 +After delta: vaddr = 0x80102020 + 29980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000034 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000001400000001fffff44000000 - 29440 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 - 29440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 64 <= 0000000020040808000000001fffff44000000 + 29990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102020, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 29440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } + 29990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000fe4 +After delta: vaddr = 0x80000fe4 +instret:493 PC:0x1ffff000000000000000000008000119c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2999 +instret:494 PC:0x1ffff00000000000000000000800011a0 instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2999 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000001000000001fffff44000000 - 29450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } + 30000 : [doFinishMem] DTlbResp { resp: <'h0000000080102020,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102020, check_high: 'h00000000080102028, check_inclusive: True } }, specBits: 'h000 } + 30000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080102020, shiftedBE: tagged DataMemAccess , pcHash: 'h91a8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 29450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } +instret:495 PC:0x1ffff00000000000000000000800011a4 instr:0xe8050513 iType:Alu [doCommitNormalInst [0]] 3000 calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000008000000001fffff44000000 - 29460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 29460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001028 -After delta: vaddr = 0x80001028 - 29460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:377 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2946 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5b7, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 400000002000040a1028ffff1ffff805821008 - 29470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001028 o: 'h0000000000000020 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001028 o: 'h0000000000000020 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001028, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29470 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 29470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:378 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 2947 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 29480 : [doFinishMem] DTlbResp { resp: <'h0000000080001028,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001028 o: 'h0000000000000020 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001028, check_high: 'h00000000080001030, check_inclusive: True } }, specBits: 'h000 } - 29480 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 29480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 29480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:379 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 2948 -instret:380 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 2948 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:381 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 2950 -instret:382 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 2950 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001028, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 29510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:383 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2951 -calling cycle - 29520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 29520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 29520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:384 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2952 -instret:385 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 2952 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:386 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2953 -instret:387 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 2953 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 29540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 29550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 29550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 29550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 29560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 29570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 29570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 29580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 29580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29580 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 29580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29590 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 29590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 29590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 29600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 29600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 29600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29610 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 - 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29610 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 29610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29620 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001400000001fffff44000000 - 29620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdb7, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 29640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle -calling cycle - 29660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29660 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 29660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 29670 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6db, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 29760 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29770 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 29770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 29770 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 29770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h36d, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 29780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29780 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 - 29780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 29790 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 29790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 29790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:388 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2979 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h009 } - 29800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29800 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 29800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 29800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:389 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 2980 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff90, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 29810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } - 29810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h013 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 29810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 29810 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 29810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 29810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 29830 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 29830 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:390 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 2983 -calling cycle - 29840 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 29880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 29890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 29890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 29900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 29900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 29910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 29910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 29910 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 29910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:391 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 2991 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 29920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 29920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29920 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 29920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 29920 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 29920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 29930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 29930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29930 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 29930 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29940 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 - 29940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 29940 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 29940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:392 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2994 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29950 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001400000001fffff44000000 - 29950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:393 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2995 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:394 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 2996 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hb6d, localHist: 'h3ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 29970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 29970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -calling cycle - 29980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 29980 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 29980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 05 <= 0000000000000000000000001fffff44000000 - 29990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 29990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29990 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000001400000001fffff44000000 - 29990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 30000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30000 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 30000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:395 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3000 -instret:396 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30010 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001400000001fffff44000000 - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } +[RFile] wr_ 1: r 67 <= 00000000000000ffc00000001fffff44000000 + 30010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } + 30010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h91aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30010 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000001800000001fffff44000000 - 30020 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 30020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000001400000001fffff44000000 - 30030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 30030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } + 30010 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } calling cycle -[RFile] wr_ 0: r 6a <= 000000000000000a000000001fffff44000000 - 30040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 30040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001030 -After delta: vaddr = 0x80001030 - 30040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:397 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3004 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5b6, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 400000002000040c1030ffff1ffff805821008 - 30050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001030 o: 'h0000000000000028 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001030 o: 'h0000000000000028 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001030, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 30050 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 30050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:398 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3005 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 30060 : [doFinishMem] DTlbResp { resp: <'h0000000080001030,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001030 o: 'h0000000000000028 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001030, check_high: 'h00000000080001038, check_inclusive: True } }, specBits: 'h000 } - 30060 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 30060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 30060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:399 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3006 -instret:400 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3006 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:401 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3008 -instret:402 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3008 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001030, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 30090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:403 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3009 -calling cycle - 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:404 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3010 -instret:405 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3010 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -instret:406 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3011 -instret:407 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3011 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 30120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[RFile] wr_ 0: r 65 <= 0ffc00000000000003ff00001fffff44000000 + 30020 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000020000836000000001fffff44000000 + 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } + 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } + 30020 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } + 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 30140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 30150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 30160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 30160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30160 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 30160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 30170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 30170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30170 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200004021008ffff1ffff805821008 - 30170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30170 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 30170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 30180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 30180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30180 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30180 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 30180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30190 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 30190 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 30190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30200 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001800000001fffff44000000 - 30200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdb6, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[RFile] wr_ 0: r 70 <= 000000002000046e800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080102020, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30030 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 calling cycle - 30220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 30220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 30230 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 30230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4d <= 0000000000000000000000001fffff44000000 - 30240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 30240 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001800000001fffff44000000 - 30240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 30250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 30260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30260 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 30260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000001c00000001fffff44000000 - 30270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 30270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30270 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 30270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30270 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 30270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000001800000001fffff44000000 - 30280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 30280 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 40000000200004021008ffff1ffff805821008 - 30280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30280 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 30280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 000000000000000c000000001fffff44000000 - 30290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 30290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30290 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 - 30290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001038 -After delta: vaddr = 0x80001038 - 30290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 400000002000040e1038ffff1ffff805821008 - 30300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 30300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001038, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30300 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 30300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 30310 : [doFinishMem] DTlbResp { resp: <'h0000000080001038,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001038, check_high: 'h00000000080001040, check_inclusive: True } }, specBits: 'h000 } - 30310 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 30310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 1000000000000000040000001fffff44000000 - 30320 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001c00000001fffff44000000 - 30320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hedb, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 30330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30340 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001c00000001fffff44000000 - 30340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 30350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 0000000000000000000000001fffff44000000 - 30360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 30360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000002000000001fffff44000000 - 30370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 30370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30370 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 30370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 30380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 30380 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 30380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30380 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 30380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 30390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 30390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30390 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 30390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000001c00000001fffff44000000 - 30400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 30400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30400 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 30400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 000000000000000e000000001fffff44000000 - 30410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 30410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30410 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 - 30410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30410 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 30410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001040 -After delta: vaddr = 0x80001040 - 30410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 40000000200004101040ffff1ffff805821008 - 30420 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 30420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001040, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000400000001fffff44000000 - 30430 : [doFinishMem] DTlbResp { resp: <'h0000000080001040,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001040, check_high: 'h00000000080001048, check_inclusive: True } }, specBits: 'h004 } - 30430 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 30430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf6d, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 1000000000000000040000001fffff44000000 - 30440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 30440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:496 PC:0x1ffff00000000000000000000800011a8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3004 +calling cycle + 30050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:497 PC:0x1ffff00000000000000000000800011aa instr:0xfe442583 iType:Ld [doCommitNormalInst [0]] 3005 +calling cycle +[RFile] wr_ 1: r 62 <= 0000000000000000000000001fffff44000000 + 30060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30450 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 30450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +Before delta: vaddr = 0x800020d8 +After delta: vaddr = 0x800020d8 +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000836000000001fffff44000000 + 30070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h3ff0000000000000 o: 'h3ff0000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 30450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 +instret:498 PC:0x1ffff00000000000000000000800011ae instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3007 calling cycle + 30080 : [doFinishMem] DTlbResp { resp: <'h00000000800020d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020d8, check_high: 'h000000000800020e0, check_inclusive: True } }, specBits: 'h000 } +instret:499 PC:0x1ffff00000000000000000000800011b0 instr:0x000095aa iType:Alu [doCommitNormalInst [0]] 3008 +instret:500 PC:0x1ffff00000000000000000000800011b2 instr:0x3ff00513 iType:Alu [doCommitNormalInst [1]] 3008 calling cycle +instret:501 PC:0x1ffff00000000000000000000800011b6 instr:0x00001552 iType:Alu [doCommitNormalInst [0]] 3009 +instret:502 PC:0x1ffff00000000000000000000800011b8 instr:0x0000e188 iType:St [doCommitNormalInst [1]] 3009 calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h91b8 } + 30100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } +instret:503 PC:0x1ffff00000000000000000000800011ba instr:0x00000517 iType:Auipc [doCommitNormalInst [0]] 3010 calling cycle + 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } + 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 30530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfb6, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 30540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 30560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 30570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30570 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 30570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h003 } - 30580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30580 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001800000001fffff44000000 - 30580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30580 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h001 } - 30590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30590 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 30590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30590 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 30590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h001 } - 30600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30600 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200004021008ffff1ffff805821008 - 30600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30600 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 30600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:408 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3060 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 30610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 30610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30610 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30610 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } -instret:409 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3061 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30620 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 30620 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 30620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30630 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001800000001fffff44000000 - 30630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:410 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3063 -instret:411 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3063 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:412 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3064 -instret:413 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3064 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdb, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 30650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:414 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 30660 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 30660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4d <= 0000000000000000000000001fffff44000000 - 30670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 30670 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001800000001fffff44000000 - 30670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 30680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:415 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3068 -instret:416 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3068 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 30690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30690 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 30690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000001c00000001fffff44000000 - 30700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 30700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30700 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 30700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30700 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 30700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000001800000001fffff44000000 - 30710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 30710 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 40000000200004021008ffff1ffff805821008 - 30710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30710 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 30710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000000000000c000000001fffff44000000 - 30720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 30720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30720 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 - 30720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001038 -After delta: vaddr = 0x80001038 - 30720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:417 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3072 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000040e1038ffff1ffff805821008 - 30730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 30730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001038, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30730 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 30730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:418 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3073 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 30740 : [doFinishMem] DTlbResp { resp: <'h0000000080001038,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001038 o: 'h0000000000000030 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001038, check_high: 'h00000000080001040, check_inclusive: True } }, specBits: 'h000 } - 30740 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 30740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:419 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3074 -instret:420 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3074 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 - 30750 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001c00000001fffff44000000 - 30750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:421 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3075 -instret:422 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3075 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfed, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001038, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 30760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:423 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3076 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30770 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001c00000001fffff44000000 - 30770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:424 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3077 -instret:425 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3077 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 30780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:426 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3078 -instret:427 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3078 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 0000000000000000000000001fffff44000000 - 30790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 30790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000002000000001fffff44000000 - 30800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 30800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30800 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 30810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 30810 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 30810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30810 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 30810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 30820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30820 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 30820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000001c00000001fffff44000000 - 30830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 30830 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30830 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 30830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 000000000000000e000000001fffff44000000 - 30840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 30840 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30840 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 - 30840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 30840 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 30840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001040 -After delta: vaddr = 0x80001040 - 30840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 40000000200004101040ffff1ffff805821008 -[RFile] wr_ 1: r 6b <= 0000000000000000400000001fffff44000000 - 30850 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30850 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000001c00000001fffff44000000 - 30850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001040, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30850 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 30850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30860 : [doFinishMem] DTlbResp { resp: <'h0000000080001040,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001040 o: 'h0000000000000038 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001040, check_high: 'h00000000080001048, check_inclusive: True } }, specBits: 'h004 } - 30860 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 30860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff6, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 30870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30870 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 30870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:428 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3087 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 30880 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 30880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:429 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3088 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 30890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 30890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:430 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3089 -instret:431 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3089 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 30900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 30900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:432 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3090 -instret:433 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3090 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 0b <= 0000000000000000000000001fffff44000000 - 30910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 30910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 30910 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 30910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 30910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:434 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3091 -instret:435 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3091 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 30920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 30920 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 30920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 30920 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 30920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:436 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3092 -instret:437 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3092 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 30930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30930 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200004021008ffff1ffff805821008 - 30930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:438 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3093 -instret:439 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3093 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 30940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 30940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 30940 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 30940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:440 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3094 -instret:441 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3094 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000002000000001fffff44000000 - 30950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 30950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30950 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 30950 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 30950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:442 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3095 -instret:443 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3095 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000010000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001040, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 30960 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 30960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001048 -After delta: vaddr = 0x80001048 - 30960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:444 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3096 -instret:445 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3096 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200004121048ffff1ffff805821008 -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 30970 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002400000001fffff44000000 - 30970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001048 o: 'h0000000000000040 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001048 o: 'h0000000000000040 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001048, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:446 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3097 -instret:447 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3097 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 - 30980 : [doFinishMem] DTlbResp { resp: <'h0000000080001048,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001048 o: 'h0000000000000040 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001048, check_high: 'h00000000080001050, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 30980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 30980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 30990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 30990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 30990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 30990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 30990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800010c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 31000 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31000 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002400000001fffff44000000 - 31000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800010c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 31000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 31000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 31000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 57 <= 0000000000000000000000001fffff44000000 - 31010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 31010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31010 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 31010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31020 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800010c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800010c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 31020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 31020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31020 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002000000001fffff44000000 - 31020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31020 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 31020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 31030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31030 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 31030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31030 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 31030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 31040 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 64 <= 40000000200004021008ffff1ffff805821008 - 31040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:448 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3104 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 31050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 31050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 31050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:449 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3105 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000012000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 31060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31060 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 31060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001050 -After delta: vaddr = 0x80001050 - 31060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:450 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3106 -instret:451 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3106 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 40000000200004141050ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31070 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 31070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001050 o: 'h0000000000000048 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001050 o: 'h0000000000000048 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001050, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:452 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3107 -instret:453 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3107 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31080 : [doFinishMem] DTlbResp { resp: <'h0000000080001050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001050 o: 'h0000000000000048 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001050, check_high: 'h00000000080001058, check_inclusive: True } }, specBits: 'h010 } - 31080 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002800000001fffff44000000 - 31080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:454 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3108 -instret:455 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3108 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 1000000000000000040000001fffff44000000 - 31090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 31090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:456 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3109 -instret:457 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3109 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31100 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002800000001fffff44000000 - 31100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h017 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:458 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3110 -instret:459 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3110 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 31110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 31110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:460 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3111 -instret:461 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3111 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 66 <= 0000000000000000000000001fffff44000000 - 31120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 31120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 31120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:462 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3112 -instret:463 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3112 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 0000000000000002c00000001fffff44000000 - 31130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001048, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 31130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31130 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 31130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:464 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3113 -instret:465 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3113 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 31140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 31140 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 - 31140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31140 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 31140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:466 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3114 -instret:467 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3114 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 31150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 31150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31150 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 31150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000002800000001fffff44000000 - 31160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 31160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31160 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 31160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000014000000001fffff44000000 - 31170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 31170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31170 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 31170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31170 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 31170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001058 -After delta: vaddr = 0x80001058 - 31170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 47 <= 40000000200004161058ffff1ffff805821008 - 31180 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 31180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001058 o: 'h0000000000000050 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001058 o: 'h0000000000000050 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001058, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 - 31190 : [doFinishMem] DTlbResp { resp: <'h0000000080001058,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001058 o: 'h0000000000000050 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001058, check_high: 'h00000000080001060, check_inclusive: True } }, specBits: 'h014 } - 31190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31190 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002c00000001fffff44000000 - 31190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 31200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31200 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 31200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31210 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000002400000001fffff44000000 - 31210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 31220 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002c00000001fffff44000000 - 31220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 7e <= 0000000000000000000000001fffff44000000 - 31230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 31230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:468 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3123 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 31240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31240 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 31240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:469 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3124 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31250 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 31250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:470 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3125 -instret:471 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3125 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 31260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 31260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:472 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3126 -instret:473 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3126 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 31270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:474 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3127 -instret:475 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3127 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000016000000001fffff44000000 - 31280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 31280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001060 -After delta: vaddr = 0x80001060 - 31280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:476 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3128 -instret:477 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3128 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 40000000200004181060ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 31290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001060 o: 'h0000000000000058 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001060 o: 'h0000000000000058 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001060, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31290 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 31290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:478 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3129 -instret:479 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3129 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31300 : [doFinishMem] DTlbResp { resp: <'h0000000080001060,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001060 o: 'h0000000000000058 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001060, check_high: 'h00000000080001068, check_inclusive: True } }, specBits: 'h00c } - 31300 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 31300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31300 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 31300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:480 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3130 -instret:481 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3130 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 31310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 31310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31310 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 31310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:482 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3131 -instret:483 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3131 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001050, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 31320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31320 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 31320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:484 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3132 -instret:485 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3132 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000000400000001fffff44000000 - 31330 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 31330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 31330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:486 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3133 -instret:487 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3133 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 31340 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 31340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 31350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 31350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31360 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31360 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 - 31360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 31370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 31370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31370 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 31370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000000000000001fffff44000000 - 31380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 31380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31380 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002800000001fffff44000000 - 31380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31390 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 31390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 31400 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 -instret:488 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3140 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:489 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3141 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:490 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3142 -instret:491 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3142 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000018000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001068 -After delta: vaddr = 0x80001068 - 31430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:492 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3143 -instret:493 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3143 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 400000002000041a1068ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001068, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 31440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:494 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3144 -instret:495 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3144 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31450 : [doFinishMem] DTlbResp { resp: <'h0000000080001068,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001068, check_high: 'h00000000080001070, check_inclusive: True } }, specBits: 'h028 } - 31450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 31450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:496 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3145 -instret:497 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3145 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 31460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:498 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3146 -instret:499 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3146 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 31470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31470 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 31470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:500 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3147 -instret:501 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3147 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 31480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 31480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31480 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 49 <= 40000000200004021008ffff1ffff805821008 - 31480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31480 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 31480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:502 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3148 -instret:503 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3148 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001058, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 31490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31490 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31490 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 31490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:504 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3149 -instret:505 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3149 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 31500 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800010c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 - 31500 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 31500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 31500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:506 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3150 -instret:507 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3150 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 31510 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003400000001fffff44000000 - 31510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800010c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 31510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 31520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31530 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31530 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003400000001fffff44000000 - 31530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 31540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 31540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31540 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5e <= 0000000000000000000000001fffff44000000 - 31550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 31550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31550 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002c00000001fffff44000000 - 31550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31560 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 31570 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 -instret:508 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3157 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:509 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3158 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:510 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3159 -instret:511 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3159 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 000000000000001a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001070 -After delta: vaddr = 0x80001070 - 31600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:512 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3160 -instret:513 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3160 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000041c1070ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001070, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 31610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:514 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3161 -instret:515 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3161 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31620 : [doFinishMem] DTlbResp { resp: <'h0000000080001070,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001070, check_high: 'h00000000080001078, check_inclusive: True } }, specBits: 'h030 } - 31620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 31620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:516 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3162 -instret:517 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3162 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 31630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:518 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3163 -instret:519 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3163 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 31640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 31640 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:520 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3164 -instret:521 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3164 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 31650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 31650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31650 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200004021008ffff1ffff805821008 - 31650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 31650 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 31650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:522 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3165 -instret:523 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3165 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001060, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 31660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31660 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 - 31660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 31660 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 31660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:524 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3166 -instret:525 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3166 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000000400000001fffff44000000 - 31670 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 31670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 31670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:526 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3167 -instret:527 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3167 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 31680 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003800000001fffff44000000 - 31680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 31690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 31690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 31690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31700 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003800000001fffff44000000 - 31700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 31700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 31710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 31710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 31710 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 31710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6f <= 0000000000000000000000001fffff44000000 - 31720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 31720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31720 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 31720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 31720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 31730 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 31730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 31740 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 -instret:528 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3174 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006a; 'h5; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } -instret:529 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3175 calling cycle -[ROB incorrectSpec] 'h5 ; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:530 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3177 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 31840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 31850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 31860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 31870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 31870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:531 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 3187 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 31880 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 31880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 31880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:532 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3188 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 31890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 31890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31890 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 31890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 31890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff80, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 31900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 31900 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 31900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 31900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 31910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h009 } - 31910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31910 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 - 31910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 31910 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 31910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 31910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:533 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 3191 -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 0a <= 00000000200003dc000000001fffff44000000 - 31920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h008 } - 31920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 31920 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 31920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 31920 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 31920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 31920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle - 31930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 31930 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 000000002000015f000000001fffff44000000 - 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 31930 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 31930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:534 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 3193 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 000000002000016d800000001fffff44000000 - 31940 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000020000400000000001fffff44000000 - 31940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff80, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:535 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 3194 -instret:536 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 3194 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h3; InstTag { way: 'h1, ptr: 'h01, t: 'h03 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 31950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff80, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 31950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 31950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } calling cycle -[ROB incorrectSpec] 'h3 ; InstTag { way: 'h1, ptr: 'h01, t: 'h03 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 31970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle @@ -12849,84876 +10560,61065 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h3aa, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c calling cycle - 32080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 32080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 32090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32090 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 32090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32100 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000400000001fffff44000000 - 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32100 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32110 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 32110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 32110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:537 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 3212 -calling cycle - 32130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } - 32130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:538 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 3213 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 32140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h001 } - 32140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 32140 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 32160 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 32160 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 32160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:539 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3216 calling cycle - 32170 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000005c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[RFile] wr_ 1: r 73 <= 00000000200005e0000000001fffff44000000 calling cycle - 32220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000000000000001fffff44000000 - 32230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:540 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3224 -instret:541 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 3224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:542 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3225 -instret:543 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [1]] 3225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 32260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 32260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32270 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6ff, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 32280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32280 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 32280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -calling cycle - 32290 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 32290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 32290 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 32290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 32290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 32300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 32300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32300 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 32300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 32300 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 32300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } - 32310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32310 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 - 32310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32310 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 32310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32320 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000400000001fffff44000000 - 32320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32320 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 32320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32330 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000004000000001fffff44000000 - 32330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 32330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:544 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3233 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } - 32340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 32340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:545 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3234 +instret:504 PC:0x1ffff00000000000000000000800011be instr:0x5c650513 iType:Alu [doCommitNormalInst [0]] 3055 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:546 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3236 +instret:505 PC:0x1ffff00000000000000000000800011c2 instr:0x0000210c iType:Ld [doCommitTrap] 3057 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 32410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 32420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 32430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 32430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 32440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 32440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 32440 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:547 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3244 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 32450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 32450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32450 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200004021008ffff1ffff805821008 - 32450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 32450 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 32460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32460 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 32460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 32470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 32470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 32470 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 32470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:548 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3247 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32480 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 - 32480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:549 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3248 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:550 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3249 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 32500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 32510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 32510 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 32510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 46 <= 0000000000000003000000001fffff44000000 - 32520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 32520 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 - 32520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 32530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:551 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3253 -instret:552 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3253 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32540 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000400000001fffff44000000 - 32550 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 32550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000003000000001fffff44000000 - 32560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000018000000001fffff44000000 - 32570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 32570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001068 -After delta: vaddr = 0x80001068 - 32570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:553 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3257 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h77f, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 400000002000041a1068ffff1ffff805821008 - 32580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001068, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 32580 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:554 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3258 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32590 : [doFinishMem] DTlbResp { resp: <'h0000000080001068,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001068 o: 'h0000000000000060 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001068, check_high: 'h00000000080001070, check_inclusive: True } }, specBits: 'h000 } - 32590 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 - 32590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 32590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:555 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3259 -instret:556 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3259 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 32600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 32600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:557 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3260 -instret:558 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3260 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001068, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 32610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 32610 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 32610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:559 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3261 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000800000001fffff44000000 - 32620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h015 } - 32620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32620 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000400000001fffff44000000 - 32620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 32620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 32620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 32620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:560 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3262 -instret:561 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3262 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 00000000200003dc000000001fffff44000000 - 32630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 32630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000004000000001fffff44000000 - 32630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 32630 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 32630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 32630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:562 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3263 -instret:563 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3263 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000000000001fffff44000000 - 32640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h005 } - 32640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32640 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 000000002000015f000000001fffff44000000 - 32640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 32640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 32640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle - 32650 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h007 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 32650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 32650 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 32650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[RFile] wr_ 1: r 5b <= 0000000020000400000000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h0; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } - 32660 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h007 } - 32660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32660 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000020000400000000001fffff44000000 - 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 32660 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 32660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } +instret:506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3066 calling cycle - 32670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 32680 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 32680 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 32680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 32690 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 32690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 32700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 32710 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 32710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 32720 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000400000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:564 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3274 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } -instret:565 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3275 +instret:507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3075 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:566 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3277 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 32840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 32840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 32850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 32850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 32860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 32860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 32870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 32870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 32870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 32870 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 32870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:567 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3287 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 32880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 32880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32880 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 32880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 32880 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 32890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32890 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 - 32890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 32890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 32890 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 32890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32900 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 32900 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:568 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3290 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32910 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000400000001fffff44000000 - 32910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:569 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3291 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 32920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:570 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3292 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } +instret:508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3084 calling cycle - 32940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 32940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 32940 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 32940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 55 <= 0000000000000003000000001fffff44000000 - 32950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32950 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000400000001fffff44000000 - 32950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 32960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 32960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 32960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 32960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:571 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3296 -instret:572 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3296 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 32970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 32970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 32970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 32970 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 32970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 32970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 32970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000800000001fffff44000000 - 32980 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 32980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000000000003400000001fffff44000000 - 32990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 32990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 32990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7bf, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 000000000000001a000000001fffff44000000 - 33000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 33000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001070 -After delta: vaddr = 0x80001070 - 33000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:573 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3300 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000041c1070ffff1ffff805821008 - 33010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001070, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33010 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 33010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:574 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3301 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33020 : [doFinishMem] DTlbResp { resp: <'h0000000080001070,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001070 o: 'h0000000000000068 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001070, check_high: 'h00000000080001078, check_inclusive: True } }, specBits: 'h000 } - 33020 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 33020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 33020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:575 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3302 -instret:576 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3302 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 33030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:577 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3303 -instret:578 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3303 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001070, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 33040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33040 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:579 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3304 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 72 <= 0000000000000000800000001fffff44000000 - 33050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 33050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33050 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000400000001fffff44000000 - 33050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33050 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 33050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 33050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:580 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3305 -instret:581 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3305 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000000000001fffff44000000 - 33060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33060 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000004000000001fffff44000000 - 33060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33060 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 33060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:582 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3306 -instret:583 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3306 -calling cycle - 33070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 33070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33070 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 000000002000015f000000001fffff44000000 - 33070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 33070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000020000400000000001fffff44000000 - 33080 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 33080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33080 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } - 33090 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 33090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33090 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000020000400000000001fffff44000000 - 33090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33090 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 33090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 33100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 33110 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 33110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 33120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 33130 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 33140 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 33150 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000800000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3093 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:584 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3317 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } -instret:585 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3318 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:586 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3320 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3102 calling cycle - 33260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 33270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 33270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 33280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 33290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 33290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 33300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 33300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 33300 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 33300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:587 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3330 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 33310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33310 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0b <= 40000000200004021008ffff1ffff805821008 - 33310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 33310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 33310 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 33310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 33320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33320 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 33320 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 33320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33330 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 33330 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:588 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3333 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33340 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000800000001fffff44000000 - 33340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:589 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3334 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:590 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3335 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3bf, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 33370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 33370 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6a <= 0000000000000003000000001fffff44000000 - 33380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33380 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000800000001fffff44000000 - 33380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 33390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:591 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3339 -instret:592 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3339 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 33400 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000c00000001fffff44000000 - 33410 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 33410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000003800000001fffff44000000 - 33420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7df, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 000000000000001c000000001fffff44000000 - 33430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 33430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001078 -After delta: vaddr = 0x80001078 - 33430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:593 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3343 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 400000002000041e1078ffff1ffff805821008 - 33440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001078 o: 'h0000000000000070 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001078 o: 'h0000000000000070 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001078, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33440 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:594 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3344 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33450 : [doFinishMem] DTlbResp { resp: <'h0000000080001078,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001078 o: 'h0000000000000070 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001078, check_high: 'h00000000080001080, check_inclusive: True } }, specBits: 'h000 } - 33450 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000400000001fffff44000000 - 33450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 33450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:595 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3345 -instret:596 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3345 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 33460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:597 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3346 -instret:598 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3346 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001078, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 33470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33470 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 33470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:599 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3347 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 56 <= 0000000000000000800000001fffff44000000 - 33480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 33480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33480 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 33480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33480 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 33480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 33480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:600 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3348 -instret:601 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3348 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000000000000001fffff44000000 - 33490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33490 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000004000000001fffff44000000 - 33490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33490 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 33490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 33490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:602 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3349 -instret:603 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3349 -calling cycle - 33500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 33500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33500 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 000000002000015f000000001fffff44000000 - 33500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 33500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000020000400000000001fffff44000000 - 33510 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 33510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33510 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 33510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } - 33520 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 33520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33520 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000020000400000000001fffff44000000 - 33520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33520 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 33520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 33530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 33540 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33540 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 33540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 33550 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 33550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 33560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 33570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 33570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 33570 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 33570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3111 calling cycle - 33580 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000000c00000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:604 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3360 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h02, t: 'h05 } -instret:605 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3361 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h02, t: 'h05 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:606 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3363 calling cycle calling cycle calling cycle +instret:512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3120 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 33690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 33700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 33700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 33710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 33720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 33720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 33730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 33730 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 33730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:607 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3373 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 33740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33740 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200004021008ffff1ffff805821008 - 33740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 33740 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 33740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 33750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33750 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000400000001fffff44000000 - 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 33750 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 33750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33760 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 33760 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 33760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:608 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3376 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33770 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000c00000001fffff44000000 - 33770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:609 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3377 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:610 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3378 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 33800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 33800 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 33800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 43 <= 0000000000000003000000001fffff44000000 - 33810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33810 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000c00000001fffff44000000 - 33810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 33820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:611 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3382 -instret:612 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3382 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 33830 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 33830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 33830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000001000000001fffff44000000 - 33840 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 33840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000003c00000001fffff44000000 - 33850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 33850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ef, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 000000000000001e000000001fffff44000000 - 33860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 33860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001080 -After delta: vaddr = 0x80001080 - 33860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:613 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3386 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 40000000200004201080ffff1ffff805821008 - 33870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001080 o: 'h0000000000000078 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001080 o: 'h0000000000000078 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001080, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 33870 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 33870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:614 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3387 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 33880 : [doFinishMem] DTlbResp { resp: <'h0000000080001080,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001080 o: 'h0000000000000078 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001080, check_high: 'h00000000080001088, check_inclusive: True } }, specBits: 'h000 } - 33880 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 33880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 33880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:615 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3388 -instret:616 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3388 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 33890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 33890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:617 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3389 -instret:618 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3389 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 33900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001080, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 33900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 33900 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 33900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 33900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:619 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3390 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 6e <= 0000000000000000800000001fffff44000000 - 33910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 33910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33910 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000400000001fffff44000000 - 33910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 33910 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 33910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 33910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:620 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3391 -instret:621 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3391 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000000000000001fffff44000000 - 33920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 33920 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000004000000001fffff44000000 - 33920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 33920 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 33920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 33920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 33920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:622 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3392 -instret:623 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3392 -calling cycle - 33930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 33930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33930 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 000000002000015f000000001fffff44000000 - 33930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 33930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 33930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000020000400000000001fffff44000000 - 33940 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 33940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 33940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 33940 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 33940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } - 33950 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 33950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33950 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000020000400000000001fffff44000000 - 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 33950 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 33950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } -calling cycle - 33960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 33970 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 33970 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 33980 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 33980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -calling cycle - 33990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 33990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34000 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 34010 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001100, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 34010 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:624 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3403 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } -instret:625 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3404 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -instret:626 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 34130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 34140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 34150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 34150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 34160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 34160 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 34160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:627 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3416 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 34170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34170 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 66 <= 40000000200004021008ffff1ffff805821008 - 34170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 34170 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 34170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 34180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34180 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 34180 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 34180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34190 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 34190 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 34190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:628 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3419 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34200 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001000000001fffff44000000 - 34200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:629 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3420 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:630 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3421 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 34230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 34230 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 34230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 44 <= 0000000000000003000000001fffff44000000 - 34240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34240 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001000000001fffff44000000 - 34240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 34250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:631 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3425 -instret:632 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3425 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 34260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 34260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 34260 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 34260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000001400000001fffff44000000 - 34270 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 34270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000004000000001fffff44000000 - 34280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7f7, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000020000000001fffff44000000 - 34290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 34290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001088 -After delta: vaddr = 0x80001088 - 34290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:633 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3429 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200004221088ffff1ffff805821008 - 34300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001088 o: 'h0000000000000080 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001088 o: 'h0000000000000080 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001088, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 34300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 34300 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 34300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:634 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3430 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34310 : [doFinishMem] DTlbResp { resp: <'h0000000080001088,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001088 o: 'h0000000000000080 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001088, check_high: 'h00000000080001090, check_inclusive: True } }, specBits: 'h000 } - 34310 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 - 34310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 34310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:635 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3431 -instret:636 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3431 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 34320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 34320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:637 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3432 -instret:638 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3432 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001088, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 34330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 34330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 34330 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 34330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:639 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3433 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 74 <= 0000000000000000800000001fffff44000000 - 34340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 34340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34340 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000400000001fffff44000000 - 34340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 34340 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 34340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 34340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:640 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3434 -instret:641 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3434 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000000000001fffff44000000 - 34350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 34350 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000004000000001fffff44000000 - 34350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 34350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 34350 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 34350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 34350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:642 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3435 -instret:643 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3435 -calling cycle - 34360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 34360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34360 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 000000002000015f000000001fffff44000000 - 34360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 34360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 34360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000400000000001fffff44000000 - 34370 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 34370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 34370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 34370 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 34370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h1b, t: 'h36 } - 34380 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 34380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34380 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000020000400000000001fffff44000000 - 34380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 34380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 34380 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 34380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } -calling cycle - 34390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h1b, t: 'h36 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 34400 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 34400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 34400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 34400 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 34400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 34410 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 34410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 34420 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 34430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34430 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 34430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 34440 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001400000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:644 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3446 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } -instret:645 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3447 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 34490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001100, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -instret:646 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3449 -calling cycle - 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 34500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 34560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 34570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 34580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 34580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 34590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 34590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 34590 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 34590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:647 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3459 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 34600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34600 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 34600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 34600 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 34600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 34610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34610 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 - 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 34610 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 34610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34620 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 - 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 34620 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 34620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:648 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3462 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34630 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001400000001fffff44000000 - 34630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:649 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3463 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:650 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3464 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 34660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 34660 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 34660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 62 <= 0000000000000003000000001fffff44000000 - 34670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34670 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001400000001fffff44000000 - 34670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 34680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:651 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3468 -instret:652 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3468 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 34690 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 34690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 34690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000001800000001fffff44000000 - 34700 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 34700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000004400000001fffff44000000 - 34710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 34710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fb, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000022000000001fffff44000000 - 34720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 34720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001090 -After delta: vaddr = 0x80001090 - 34720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:653 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3472 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 40000000200004241090ffff1ffff805821008 - 34730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001090 o: 'h0000000000000088 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001090 o: 'h0000000000000088 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001090, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 34730 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 34730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:654 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3473 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 34740 : [doFinishMem] DTlbResp { resp: <'h0000000080001090,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001090 o: 'h0000000000000088 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001090, check_high: 'h00000000080001098, check_inclusive: True } }, specBits: 'h000 } - 34740 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 - 34740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 34740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:655 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3474 -instret:656 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3474 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 34750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 34750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 34750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:657 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3475 -instret:658 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3475 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 34760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001090, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 34760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 34760 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 34760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:659 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3476 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 0c <= 0000000000000000800000001fffff44000000 - 34770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 34770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34770 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000400000001fffff44000000 - 34770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 34770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 34770 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 34770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 34770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:660 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3477 -instret:661 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3477 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000000000000001fffff44000000 - 34780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 34780 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000004000000001fffff44000000 - 34780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 34780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 34780 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 34780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 34780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 34780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:662 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3478 -instret:663 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3478 -calling cycle - 34790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 34790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34790 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 000000002000015f000000001fffff44000000 - 34790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 34790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 34790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000020000400000000001fffff44000000 - 34800 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 34800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 34800 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 34800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } - 34810 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 34810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34810 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000020000400000000001fffff44000000 - 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 34810 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 34810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 34810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 34820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +instret:513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3129 calling cycle - 34830 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 34830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 34830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 34830 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 34830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 34840 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 34840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 34850 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 34850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 34860 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 34860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 34870 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000001800000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:664 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3489 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } -instret:665 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3490 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +instret:514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3138 calling cycle -instret:666 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3492 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 34980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 34990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 34990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 35000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 35010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 35010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 35020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35020 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 35020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:667 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3502 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35030 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200004021008ffff1ffff805821008 - 35030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35030 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 35030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 35040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35040 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 - 35040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 35040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 35050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35050 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 35050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:668 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3505 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35060 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001800000001fffff44000000 - 35060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:669 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3506 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:670 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3507 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 35090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35090 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 35090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0a <= 0000000000000003000000001fffff44000000 - 35100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35100 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001800000001fffff44000000 - 35100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:671 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3511 -instret:672 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3511 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35120 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 35120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000001c00000001fffff44000000 - 35130 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 35130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000004800000001fffff44000000 - 35140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000024000000001fffff44000000 - 35150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 35150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001098 -After delta: vaddr = 0x80001098 - 35150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:673 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3515 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200004261098ffff1ffff805821008 - 35160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001098 o: 'h0000000000000090 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001098 o: 'h0000000000000090 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001098, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 35160 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 35160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:674 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3516 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35170 : [doFinishMem] DTlbResp { resp: <'h0000000080001098,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001098 o: 'h0000000000000090 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001098, check_high: 'h000000000800010a0, check_inclusive: True } }, specBits: 'h000 } - 35170 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 35170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 35170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:675 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3517 -instret:676 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3517 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 35180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 35180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:677 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3518 -instret:678 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3518 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001098, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 35190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 35190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 35190 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 35190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:679 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3519 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 52 <= 0000000000000000800000001fffff44000000 - 35200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 35200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35200 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 - 35200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 35200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 35200 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 35200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 35200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:680 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3520 -instret:681 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3520 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000000000001fffff44000000 - 35210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 35210 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000004000000001fffff44000000 - 35210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 35210 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 35210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 35210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:682 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3521 -instret:683 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3521 -calling cycle - 35220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 35220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35220 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000015f000000001fffff44000000 - 35220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 35220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 35220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 35220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000020000400000000001fffff44000000 - 35230 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 35230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 35230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 35230 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 35230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } +instret:515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3147 calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } - 35240 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 35240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35240 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 - 35240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 35240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 35240 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 35240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 35250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 35260 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 35260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 35260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 35260 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 35260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35270 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 35270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35280 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 35290 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 35290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35300 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000001c00000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:684 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3532 +instret:516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3156 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } -instret:685 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3533 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:686 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3535 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 35410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3165 calling cycle - 35420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 35420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 35430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 35440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 35440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 35450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35450 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 35450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:687 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3545 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35460 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 60 <= 40000000200004021008ffff1ffff805821008 - 35460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35460 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 35460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 35470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35470 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35470 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 35470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35480 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35480 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 35480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:688 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3548 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35490 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001c00000001fffff44000000 - 35490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:689 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3549 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:690 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3550 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 35520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35520 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 35520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 42 <= 0000000000000003000000001fffff44000000 - 35530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35530 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 35530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:691 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3554 -instret:692 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3554 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35550 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 35550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000002000000001fffff44000000 - 35560 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 35560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000004c00000001fffff44000000 - 35570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fe, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000026000000001fffff44000000 - 35580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 35580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010a0 -After delta: vaddr = 0x800010a0 - 35580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:693 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3558 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 400000002000042810a0ffff1ffff805821008 - 35590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800010a0 o: 'h0000000000000098 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010a0 o: 'h0000000000000098 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 35590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 35590 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 35590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:694 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3559 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35600 : [doFinishMem] DTlbResp { resp: <'h00000000800010a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010a0 o: 'h0000000000000098 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010a0, check_high: 'h000000000800010a8, check_inclusive: True } }, specBits: 'h000 } - 35600 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 - 35600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 35600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:695 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3560 -instret:696 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3560 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 35610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 35610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:697 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3561 -instret:698 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3561 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 35620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 35620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 35620 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 35620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:699 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3562 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 6d <= 0000000000000000800000001fffff44000000 - 35630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 35630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35630 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000400000001fffff44000000 - 35630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 35630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 35630 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 35630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 35630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:700 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3563 -instret:701 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3563 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 - 35640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 35640 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000004000000001fffff44000000 - 35640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 35640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 35640 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 35640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 35640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:702 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3564 -instret:703 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3564 -calling cycle - 35650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 35650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35650 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 000000002000015f000000001fffff44000000 - 35650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 35650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 35650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 35650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000020000400000000001fffff44000000 - 35660 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 35660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 35660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 35660 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 35660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h19, t: 'h32 } - 35670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 35670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35670 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000020000400000000001fffff44000000 - 35670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 35670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 35670 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 35670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 35680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h19, t: 'h32 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 35690 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 35690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 35690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 35690 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 35690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35700 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 35700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 35720 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 35720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 35730 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002000000001fffff44000000 +instret:518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3174 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:704 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3575 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } -instret:705 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3576 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:706 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3578 calling cycle calling cycle calling cycle calling cycle +instret:519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3183 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 35840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 35850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 35850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 35860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 35860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 35870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 35870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 35880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 35880 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 35880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:707 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3588 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 35890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35890 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200004021008ffff1ffff805821008 - 35890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 35890 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 35890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 35900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35900 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000400000001fffff44000000 - 35900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 35900 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 35900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35910 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 35910 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 35910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:708 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3591 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35920 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 35920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:709 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3592 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 35930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:710 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3593 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 35950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 35950 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 35950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000003000000001fffff44000000 - 35960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 35960 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 35960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 35970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 35970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 35970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 35970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:711 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3597 -instret:712 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3597 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 35980 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 35980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 35980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 35980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000002400000001fffff44000000 - 35990 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 35990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 35990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000005000000001fffff44000000 - 36000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 36000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000028000000001fffff44000000 - 36010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 36010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010a8 -After delta: vaddr = 0x800010a8 - 36010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:713 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3601 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000042a10a8ffff1ffff805821008 - 36020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800010a8 o: 'h00000000000000a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010a8 o: 'h00000000000000a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 36020 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 36020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:714 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3602 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36030 : [doFinishMem] DTlbResp { resp: <'h00000000800010a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010a8 o: 'h00000000000000a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010a8, check_high: 'h000000000800010b0, check_inclusive: True } }, specBits: 'h000 } - 36030 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 36030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 36030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:715 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3603 -instret:716 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3603 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 36040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 36040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:717 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3604 -instret:718 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3604 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 36050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 36050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 36050 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 36050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:719 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3605 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 79 <= 0000000000000000800000001fffff44000000 - 36060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 36060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36060 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000400000001fffff44000000 - 36060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 36060 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 36060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 36060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:720 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3606 -instret:721 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3606 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000000000000001fffff44000000 - 36070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 36070 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000004000000001fffff44000000 - 36070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 36070 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 36070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 36070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:722 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3607 -instret:723 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3607 -calling cycle - 36080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 36080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36080 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000015f000000001fffff44000000 - 36080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 36080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 36080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 43 <= 0000000020000400000000001fffff44000000 - 36090 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 36090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 36090 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 36090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h03, t: 'h06 } - 36100 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 36100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36100 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000020000400000000001fffff44000000 - 36100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 36100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 36100 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 36100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 36110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h03, t: 'h06 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 36120 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 36120 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 36120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 36130 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 36130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 36130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 36140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3192 calling cycle - 36150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36150 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 36150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 36160 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002400000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:724 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3618 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } -instret:725 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3619 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:726 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3621 calling cycle calling cycle +instret:521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3201 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 36270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 36280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 36300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 36310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36310 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 36310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:727 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3631 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 36320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36320 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 36320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36320 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 36330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 36330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36330 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36330 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 36330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36340 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 36340 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:728 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3634 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36350 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002400000001fffff44000000 - 36350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:729 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3635 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:730 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3636 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 36370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 36380 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 78 <= 0000000000000003000000001fffff44000000 - 36390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 36390 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002400000001fffff44000000 - 36390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 36400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:731 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3640 -instret:732 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3640 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 36410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36410 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 36410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000002800000001fffff44000000 - 36420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 36420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36420 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 36420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36420 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000005400000001fffff44000000 - 36430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 36430 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5a <= 40000000200004021008ffff1ffff805821008 - 36430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36430 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 36430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 000000000000002a000000001fffff44000000 - 36440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 36440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36440 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000400000001fffff44000000 - 36440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010b0 -After delta: vaddr = 0x800010b0 - 36440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:733 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3644 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 400000002000042c10b0ffff1ffff805821008 - 36450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 36450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800010b0 o: 'h00000000000000a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010b0 o: 'h00000000000000a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36450 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 36450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:734 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3645 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000000400000001fffff44000000 - 36460 : [doFinishMem] DTlbResp { resp: <'h00000000800010b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010b0 o: 'h00000000000000a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010b0, check_high: 'h000000000800010b8, check_inclusive: True } }, specBits: 'h000 } - 36460 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 36460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:735 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3646 -instret:736 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3646 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 1000000000000000040000001fffff44000000 - 36470 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002800000001fffff44000000 - 36470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:737 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3647 -instret:738 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3647 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 36480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800010b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:739 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3648 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36490 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002800000001fffff44000000 - 36490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800010b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 36490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800010b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:740 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3649 -instret:741 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3649 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 36500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:742 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3650 -instret:743 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3650 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4e <= 0000000000000003000000001fffff44000000 - 36510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 36510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000002c00000001fffff44000000 - 36520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 36520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36520 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 36530 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003000000001fffff44000000 - 36530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36530 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 36530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 36540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36540 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 36540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000005800000001fffff44000000 - 36550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 36550 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36550 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 36550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 000000000000002c000000001fffff44000000 - 36560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 36560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36560 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 36560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36560 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 36560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010b8 -After delta: vaddr = 0x800010b8 - 36560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 400000002000042e10b8ffff1ffff805821008 - 36570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36570 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002800000001fffff44000000 - 36570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800010b8 o: 'h00000000000000b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010b8 o: 'h00000000000000b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36570 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 36570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36580 : [doFinishMem] DTlbResp { resp: <'h00000000800010b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010b8 o: 'h00000000000000b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010b8, check_high: 'h000000000800010c0, check_inclusive: True } }, specBits: 'h004 } - 36580 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 - 36580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 36590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36590 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002c00000001fffff44000000 - 36590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:744 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3659 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 36600 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002c00000001fffff44000000 - 36600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:745 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3660 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 36610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:746 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3661 -instret:747 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3661 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 36620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:748 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3662 -instret:749 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3662 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 68 <= 0000000000000003000000001fffff44000000 - 36630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h019 } - 36630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36630 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 36630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:750 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3663 -instret:751 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3663 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 36640 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 36640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36640 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 36640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:752 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3664 -instret:753 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3664 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 36650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36650 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 36650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:754 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3665 -instret:755 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3665 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 36660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 36660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36660 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 36660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:756 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3666 -instret:757 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3666 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000005c00000001fffff44000000 - 36670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 36670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36670 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 - 36670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36670 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 36670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:758 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3667 -instret:759 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3667 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 000000000000002e000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 36680 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 36680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010c0 -After delta: vaddr = 0x800010c0 - 36680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800010b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:760 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3668 -instret:761 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3668 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 400000002000043010c0ffff1ffff805821008 -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 - 36690 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 36690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800010c0 o: 'h00000000000000b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010c0 o: 'h00000000000000b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800010b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 36690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800010b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:762 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3669 -instret:763 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3669 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 1000000000000000040000001fffff44000000 - 36700 : [doFinishMem] DTlbResp { resp: <'h00000000800010c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010c0 o: 'h00000000000000b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010c0, check_high: 'h000000000800010c8, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 36700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 36710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 36710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 36720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36720 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 36720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000003000000001fffff44000000 - 36730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 36730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36730 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 36730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 36740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36740 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002c00000001fffff44000000 - 36740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36740 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 36740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 36750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36750 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 36750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36750 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 36750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 36760 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 56 <= 40000000200004021008ffff1ffff805821008 - 36760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36760 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 36760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:764 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3676 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000006000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 36770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 36770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36770 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 - 36770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:765 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3677 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000030000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 36780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36780 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 36780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010c8 -After delta: vaddr = 0x800010c8 - 36780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:766 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3678 -instret:767 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 3678 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 400000002000043210c8ffff1ffff805821008 -[RFile] wr_ 1: r 01 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36790 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 36790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:768 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3679 -instret:769 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 3679 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36800 : [doFinishMem] DTlbResp { resp: <'h00000000800010c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010c8, check_high: 'h000000000800010d0, check_inclusive: True } }, specBits: 'h010 } - 36800 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003400000001fffff44000000 - 36800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:770 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3680 -instret:771 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 3680 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 36810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:772 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 3681 -instret:773 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 3681 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36820 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003400000001fffff44000000 - 36820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:774 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3682 -instret:775 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 3682 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 36830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 36830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:776 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 3683 -instret:777 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 3683 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5f <= 0000000000000003000000001fffff44000000 - 36840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 36840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 36840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:778 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 3684 -instret:779 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 3684 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000003800000001fffff44000000 - 36850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01d } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 36850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 36850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 36850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:780 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3685 -instret:781 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3685 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 36860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 36860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 - 36860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 36860 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 36860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 36860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800010c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:782 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3686 -instret:783 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3686 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 36870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36870 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6e <= 40000000200004021008ffff1ffff805821008 - 36870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800010c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 36870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800010c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000006400000001fffff44000000 - 36880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 36880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 36880 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 36880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000032000000001fffff44000000 - 36890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 36890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36890 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 36890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 36890 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 36890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010d0 -After delta: vaddr = 0x800010d0 - 36890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 400000002000043410d0ffff1ffff805821008 -[RFile] wr_ 1: r 67 <= 0000000000000000400000001fffff44000000 - 36900 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 36900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 36900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 36900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 1000000000000000040000001fffff44000000 - 36910 : [doFinishMem] DTlbResp { resp: <'h00000000800010d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010d0, check_high: 'h000000000800010d8, check_inclusive: True } }, specBits: 'h014 } - 36910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36910 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003800000001fffff44000000 - 36910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 36910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 36910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 36910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 36920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 36920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 36920 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 36920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 36920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 36930 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001140, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 36930 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 36930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 36940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 36940 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003800000001fffff44000000 - 36940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 36940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 77 <= 0000000000000003000000001fffff44000000 - 36950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 36950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 36950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:784 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3695 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } - 36960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 36960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 36960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 36960 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 36960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 36960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:785 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3696 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 36980 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:786 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3698 calling cycle calling cycle +instret:522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3210 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 37060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3d5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 37080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:787 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 3708 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37090 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 37090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:788 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3709 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 37100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37100 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000000400000001fffff44000000 - 37100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 37100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 37110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37110 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 37110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h009 } - 37120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37120 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000400000001fffff44000000 - 37120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37120 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 37120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:789 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 3712 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 5b <= 00000000200003dc000000001fffff44000000 - 37130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h008 } - 37130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37130 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 37130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 37130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000000000000001fffff44000000 - 37140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 37140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 000000002000015f000000001fffff44000000 - 37140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37140 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 37140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 -instret:790 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 3714 -calling cycle - 37150 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h00a } - 37150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37150 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000020000400000000001fffff44000000 - 37150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -instret:791 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 3715 -instret:792 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 3715 calling cycle -[RFile] wr_ 0: r 0a <= 0000000020000400000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h3; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 37160 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h00a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 37160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 37160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 37160 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 37160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } +instret:523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3219 calling cycle - 37170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[ROB incorrectSpec] 'h3 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37180 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 37180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 37180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 37180 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 37180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle - 37200 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 37200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 37200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 37200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3228 calling cycle - 37260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h3ea, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c calling cycle - 37290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 37290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 37300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37300 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 37300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37310 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 - 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 37310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37320 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 37320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 37320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:793 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 3733 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } - 37340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:794 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 3734 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h0; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 37350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h001 } - 37350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37350 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 37350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 37350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 37370 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 37370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37370 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 37370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:795 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3737 calling cycle - 37380 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle +instret:525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3237 calling cycle - 37410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001140, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 37420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 37420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 37440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 0000000000000000000000001fffff44000000 - 37450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 37450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 37460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:796 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3746 -instret:797 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 3746 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 37470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:798 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3747 -instret:799 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [1]] 3747 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 37480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 37480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 37490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 37490 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 37490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h6ff, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h005 } - 37500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37500 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 37500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 37500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 37500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -calling cycle - 37510 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37510 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 37510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 37510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 37520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 37520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37520 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 - 37520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 37520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 37520 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 37520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } - 37530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37530 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 - 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37530 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 37530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37540 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000800000001fffff44000000 - 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37540 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 37540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37550 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000004000000001fffff44000000 - 37550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 37550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:800 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3755 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } - 37560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 37560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 -instret:801 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3756 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:802 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3758 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3246 calling cycle - 37620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 37630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 37640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 37640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 37650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 37650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 37660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 37660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 37660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 37660 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 37660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 37660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:803 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3766 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 37670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 37670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37670 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004021008ffff1ffff805821008 - 37670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 37670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 37670 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 37670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 37680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 37680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37680 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 - 37680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 37680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 37680 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 37680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37690 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 37690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 37690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 37690 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 37690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:804 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3769 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37700 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000000000000001fffff44000000 - 37700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:805 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3770 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:806 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3771 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 37720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 37720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 37730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 37730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 37730 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 37730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[RFile] wr_ 2: r 59 <= 0000000000000006000000001fffff44000000 - 37740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 37740 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 37740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 37750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:807 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3775 -instret:808 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3775 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 37760 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 37760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000000400000001fffff44000000 - 37770 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 37770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000006000000001fffff44000000 - 37780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 37780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000030000000001fffff44000000 - 37790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 37790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010c8 -After delta: vaddr = 0x800010c8 - 37790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:809 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3779 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h77f, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 400000002000043210c8ffff1ffff805821008 - 37800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 37800 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:810 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3780 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37810 : [doFinishMem] DTlbResp { resp: <'h00000000800010c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010c8 o: 'h00000000000000c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010c8, check_high: 'h000000000800010d0, check_inclusive: True } }, specBits: 'h000 } - 37810 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000800000001fffff44000000 - 37810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 37810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:811 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3781 -instret:812 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3781 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 37820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 37820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 37820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:813 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3782 -instret:814 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3782 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 37830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 37830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 37830 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 37830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 37830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:815 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3783 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000c00000001fffff44000000 - 37840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h015 } - 37840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37840 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000800000001fffff44000000 - 37840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 37840 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 37840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:816 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3784 -instret:817 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3784 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 00000000200003dc000000001fffff44000000 - 37850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 37850 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000004000000001fffff44000000 - 37850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 37850 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 37850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 37850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 37850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:818 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3785 -instret:819 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3785 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000000000001fffff44000000 - 37860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h005 } - 37860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37860 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 000000002000015f000000001fffff44000000 - 37860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 37860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle - 37870 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h007 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 37870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 37870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 37870 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 37870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[RFile] wr_ 1: r 5c <= 0000000020000400000000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h0; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } - 37880 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h007 } - 37880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37880 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000020000400000000001fffff44000000 - 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 37880 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 37880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 37890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 37900 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 37900 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 37910 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 37910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 37910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 37910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3255 calling cycle - 37920 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 37920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 37930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 37930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 37930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 37930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 37930 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 37930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 37940 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:820 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3796 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } -instret:821 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3797 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0e, t: 'h1d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:822 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3799 calling cycle +instret:528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3264 calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 38050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 38060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 38060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 38070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 38080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 38080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 38090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38090 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 38090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:823 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3809 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 38100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38100 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 38100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38100 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 38100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 38110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38110 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000800000001fffff44000000 - 38110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38110 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 38110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38120 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 38120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38120 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 38120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:824 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3812 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38130 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000400000001fffff44000000 - 38130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:825 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3813 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:826 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3814 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 38160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 38160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 38160 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 38160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 49 <= 0000000000000006000000001fffff44000000 - 38170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38170 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000400000001fffff44000000 - 38170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 38180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:827 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3818 -instret:828 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3818 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 38190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 38190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 38190 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 38190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000800000001fffff44000000 - 38200 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 38200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000006400000001fffff44000000 - 38210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7bf, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000000000032000000001fffff44000000 - 38220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 38220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010d0 -After delta: vaddr = 0x800010d0 - 38220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:829 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3822 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 400000002000043410d0ffff1ffff805821008 - 38230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 38230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 38230 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 38230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:830 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3823 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38240 : [doFinishMem] DTlbResp { resp: <'h00000000800010d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010d0 o: 'h00000000000000c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010d0, check_high: 'h000000000800010d8, check_inclusive: True } }, specBits: 'h000 } - 38240 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000800000001fffff44000000 - 38240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 38240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:831 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3824 -instret:832 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3824 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 38250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 38250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:833 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3825 -instret:834 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3825 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 38260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 38260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 38260 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 38260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:835 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3826 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 7f <= 0000000000000000c00000001fffff44000000 - 38270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 38270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38270 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000800000001fffff44000000 - 38270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 38270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 38270 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 38270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 38270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:836 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3827 -instret:837 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3827 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000000000001fffff44000000 - 38280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 38280 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000004000000001fffff44000000 - 38280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 38280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 38280 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 38280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 38280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:838 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3828 -instret:839 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3828 -calling cycle - 38290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 38290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38290 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 000000002000015f000000001fffff44000000 - 38290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 38290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 38290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 38290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000020000400000000001fffff44000000 - 38300 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 38300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 38300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 38300 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 38300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } - 38310 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 38310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38310 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000020000400000000001fffff44000000 - 38310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 38310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 38310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 38310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 38320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h1d, t: 'h3a } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +instret:529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3273 calling cycle - 38330 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 38330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 38330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 38330 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 38330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38340 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 38340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 38340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 38340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 38360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 38360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 38360 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 38360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38370 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000800000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:840 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3839 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } -instret:841 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3840 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h18, t: 'h31 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +instret:530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3282 calling cycle -instret:842 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3842 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 38480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 38490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 38490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 38500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 38510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 38510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 38520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38520 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 38520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:843 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3852 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 38530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38530 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 40000000200004021008ffff1ffff805821008 - 38530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38530 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 38530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 38540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38540 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000800000001fffff44000000 - 38540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38540 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 38540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38550 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 38550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38550 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 38550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:844 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3855 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38560 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000800000001fffff44000000 - 38560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:845 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3856 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:846 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3857 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3bf, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 38590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 38590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 38590 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 38590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5d <= 0000000000000006000000001fffff44000000 - 38600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38600 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000800000001fffff44000000 - 38600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 38610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:847 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3861 -instret:848 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3861 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 38620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 38620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 38620 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 38620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000c00000001fffff44000000 - 38630 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 38630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000006800000001fffff44000000 - 38640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7df, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000034000000001fffff44000000 - 38650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 38650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010d8 -After delta: vaddr = 0x800010d8 - 38650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:849 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3865 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 400000002000043610d8ffff1ffff805821008 - 38660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800010d8 o: 'h00000000000000d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010d8 o: 'h00000000000000d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 38660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 38660 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 38660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:850 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3866 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38670 : [doFinishMem] DTlbResp { resp: <'h00000000800010d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010d8 o: 'h00000000000000d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010d8, check_high: 'h000000000800010e0, check_inclusive: True } }, specBits: 'h000 } - 38670 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000800000001fffff44000000 - 38670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 38670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:851 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3867 -instret:852 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3867 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 38680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 38680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:853 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3868 -instret:854 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3868 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 38690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 38690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 38690 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 38690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:855 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3869 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 7c <= 0000000000000000c00000001fffff44000000 - 38700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 38700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38700 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 - 38700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 38700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 38700 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 38700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 38700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:856 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3870 -instret:857 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3870 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 0000000000000000000000001fffff44000000 - 38710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 38710 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000004000000001fffff44000000 - 38710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 38710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 38710 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 38710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 38710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:858 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3871 -instret:859 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3871 -calling cycle - 38720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 38720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38720 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 000000002000015f000000001fffff44000000 - 38720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 38720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 38720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 38720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000020000400000000001fffff44000000 - 38730 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 38730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 38730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 38730 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 38730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } +instret:531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3291 calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } - 38740 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 38740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38740 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000400000000001fffff44000000 - 38740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 38740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 38740 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 38740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 38750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h07, t: 'h0e } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 38760 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 38760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 38760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 38760 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 38760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38770 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 38770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 38770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 38770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 38790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 38790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 38790 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 38790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 38800 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000c00000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:860 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3882 +instret:532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3300 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h02, t: 'h05 } -instret:861 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3883 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h02, t: 'h05 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:862 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3885 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 38910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3309 calling cycle - 38920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 38920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 38930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 38930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 38940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 38940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 38940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 38940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 38950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 38950 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 38950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 38950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:863 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3895 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 38960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 38960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38960 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 78 <= 40000000200004021008ffff1ffff805821008 - 38960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 38960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 38960 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 38960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 38970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 38970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 38970 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000800000001fffff44000000 - 38970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 38970 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 38970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38980 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 38980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 38980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 38980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 38980 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 38980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 38980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:864 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3898 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 38990 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000c00000001fffff44000000 - 38990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:865 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3899 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:866 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3900 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 39020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39020 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 39020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6b <= 0000000000000006000000001fffff44000000 - 39030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39030 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000c00000001fffff44000000 - 39030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 39040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:867 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3904 -instret:868 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3904 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 39050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39050 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 39050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 0000000000000001000000001fffff44000000 - 39060 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 39060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000006c00000001fffff44000000 - 39070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ef, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000036000000001fffff44000000 - 39080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 39080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010e0 -After delta: vaddr = 0x800010e0 - 39080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:869 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3908 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 400000002000043810e0ffff1ffff805821008 - 39090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800010e0 o: 'h00000000000000d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010e0 o: 'h00000000000000d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39090 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 39090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:870 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3909 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39100 : [doFinishMem] DTlbResp { resp: <'h00000000800010e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010e0 o: 'h00000000000000d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010e0, check_high: 'h000000000800010e8, check_inclusive: True } }, specBits: 'h000 } - 39100 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000800000001fffff44000000 - 39100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 39100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:871 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3910 -instret:872 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3910 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 39110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 39110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:873 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3911 -instret:874 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3911 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 39120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 39120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:875 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3912 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 4f <= 0000000000000000c00000001fffff44000000 - 39130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 39130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 - 39130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39130 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 39130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 39130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:876 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3913 -instret:877 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3913 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000000000000001fffff44000000 - 39140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 39140 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000004000000001fffff44000000 - 39140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 39140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 39140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 39140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 39140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:878 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3914 -instret:879 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3914 -calling cycle - 39150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 39150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000015f000000001fffff44000000 - 39150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 39150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 39150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 39150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000020000400000000001fffff44000000 - 39160 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 39160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 39160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 39160 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 39160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } - 39170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 39170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39170 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000020000400000000001fffff44000000 - 39170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 39170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 39170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 39170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 39180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h11, t: 'h22 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 39190 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 39190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 39190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 39190 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 39190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39200 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 39200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 39200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 39200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 39220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 39220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 39220 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 39220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39230 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001000000001fffff44000000 +instret:534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3318 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:880 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3925 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } -instret:881 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3926 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:882 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3928 calling cycle calling cycle calling cycle calling cycle +instret:535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3327 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 39340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 39350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 39350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 39360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 39370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 39370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 39380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 39380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 39380 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 39380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:883 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 39390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39390 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200004021008ffff1ffff805821008 - 39390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 39390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 39390 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 39390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 39400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39400 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000800000001fffff44000000 - 39400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 39400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 39400 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 39400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39410 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 39410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 39410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 39410 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 39410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:884 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39420 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001000000001fffff44000000 - 39420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:885 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3942 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:886 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3943 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 39450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39450 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 39450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 50 <= 0000000000000006000000001fffff44000000 - 39460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39460 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001000000001fffff44000000 - 39460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 39470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:887 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3947 -instret:888 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3947 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 39480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39480 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 39480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000001400000001fffff44000000 - 39490 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 - 39490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000007000000001fffff44000000 - 39500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7f7, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000038000000001fffff44000000 - 39510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 39510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010e8 -After delta: vaddr = 0x800010e8 - 39510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:889 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3951 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 400000002000043a10e8ffff1ffff805821008 - 39520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800010e8 o: 'h00000000000000e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010e8 o: 'h00000000000000e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39520 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 39520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:890 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3952 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39530 : [doFinishMem] DTlbResp { resp: <'h00000000800010e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010e8 o: 'h00000000000000e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010e8, check_high: 'h000000000800010f0, check_inclusive: True } }, specBits: 'h000 } - 39530 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 - 39530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 39530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:891 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3953 -instret:892 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3953 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 39540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 39540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:893 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3954 -instret:894 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3954 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 39550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39550 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 39550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:895 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3955 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 63 <= 0000000000000000c00000001fffff44000000 - 39560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 39560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39560 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000800000001fffff44000000 - 39560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39560 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 39560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 39560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:896 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3956 -instret:897 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3956 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 - 39570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 39570 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000004000000001fffff44000000 - 39570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 39570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 39570 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 39570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 39570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:898 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 3957 -instret:899 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 3957 -calling cycle - 39580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 39580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39580 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 000000002000015f000000001fffff44000000 - 39580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 39580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 39580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 39580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000020000400000000001fffff44000000 - 39590 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 39590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 39590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 39590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 39590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h1b, t: 'h36 } - 39600 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 39600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000020000400000000001fffff44000000 - 39600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 39600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 39600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 39600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 39610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h1b, t: 'h36 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 39620 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 39620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 39620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 39620 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 39620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39630 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 39630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 39630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 39630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3336 calling cycle - 39650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 39650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 39650 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 39650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 39660 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:900 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3968 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } -instret:901 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 3969 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h16, t: 'h2d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:902 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 3971 calling cycle calling cycle +instret:537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3345 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 39770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 39780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 39780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 39790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 39800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 39800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 39810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 39810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 39810 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 39810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:903 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 3981 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 39820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39820 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 39820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 39820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 39820 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 39820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 39830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39830 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 - 39830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 39830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 39830 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 39830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39840 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 39840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 39840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 39840 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 39840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:904 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 3984 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39850 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000001400000001fffff44000000 - 39850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:905 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 3985 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:906 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 3986 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 39880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 39880 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 39880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 64 <= 0000000000000006000000001fffff44000000 - 39890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39890 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001400000001fffff44000000 - 39890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 39900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:907 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 3990 -instret:908 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 3990 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 39910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 39910 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 39910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 39910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000001800000001fffff44000000 - 39920 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 39920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000007400000001fffff44000000 - 39930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 39930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fb, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 000000000000003a000000001fffff44000000 - 39940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 39940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010f0 -After delta: vaddr = 0x800010f0 - 39940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:909 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 3994 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 400000002000043c10f0ffff1ffff805821008 - 39950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800010f0 o: 'h00000000000000e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010f0 o: 'h00000000000000e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 39950 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 39950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:910 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3995 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 39960 : [doFinishMem] DTlbResp { resp: <'h00000000800010f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010f0 o: 'h00000000000000e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010f0, check_high: 'h000000000800010f8, check_inclusive: True } }, specBits: 'h000 } - 39960 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000800000001fffff44000000 - 39960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 39960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:911 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 3996 -instret:912 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 3996 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 39970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 39970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 39970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:913 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 3997 -instret:914 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 3997 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 39980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 39980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 39980 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 39980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 39980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:915 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3998 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 76 <= 0000000000000000c00000001fffff44000000 - 39990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 39990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 39990 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 - 39990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 39990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 39990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 39990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 39990 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 39990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 39990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 39990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 39990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:916 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 3999 -instret:917 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 3999 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000000000001fffff44000000 - 40000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 40000 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000004000000001fffff44000000 - 40000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40000 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 40000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 40000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:918 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4000 -instret:919 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4000 -calling cycle - 40010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 40010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40010 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 000000002000015f000000001fffff44000000 - 40010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 40010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 40010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000020000400000000001fffff44000000 - 40020 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 40020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40020 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 40020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } - 40030 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 40030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40030 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000020000400000000001fffff44000000 - 40030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40030 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 40030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } calling cycle - 40040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h05, t: 'h0a } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 40050 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40050 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 40050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3354 calling cycle - 40060 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 40060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 40070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 40080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40080 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 40080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 40090 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001800000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:920 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4011 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } -instret:921 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4012 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:922 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4014 +instret:539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3363 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 40200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 40210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 40210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 40220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 40230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 40230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 40240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 40240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 40240 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 40240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:923 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4024 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 40250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40250 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200004021008ffff1ffff805821008 - 40250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 40250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 40250 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 40250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 40260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40260 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000800000001fffff44000000 - 40260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 40260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 40260 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 40260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40270 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 40270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 40270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 40270 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 40270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:924 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4027 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40280 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001800000001fffff44000000 - 40280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:925 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4028 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:926 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4029 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 40310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 40310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 40310 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 40310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5b <= 0000000000000006000000001fffff44000000 - 40320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40320 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001800000001fffff44000000 - 40320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 40330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:927 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4033 -instret:928 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4033 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 40340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 40340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 40340 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 40340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000001c00000001fffff44000000 - 40350 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 40350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000007800000001fffff44000000 - 40360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 000000000000003c000000001fffff44000000 - 40370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 40370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800010f8 -After delta: vaddr = 0x800010f8 - 40370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:929 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4037 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 400000002000043e10f8ffff1ffff805821008 - 40380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800010f8 o: 'h00000000000000f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800010f8 o: 'h00000000000000f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800010f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 40380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 40380 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 40380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:930 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4038 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40390 : [doFinishMem] DTlbResp { resp: <'h00000000800010f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800010f8 o: 'h00000000000000f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800010f8, check_high: 'h00000000080001100, check_inclusive: True } }, specBits: 'h000 } - 40390 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 - 40390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 40390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:931 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4039 -instret:932 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4039 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 40400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 40400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:933 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4040 -instret:934 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4040 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800010f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 40410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 40410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 40410 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 40410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:935 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4041 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 4d <= 0000000000000000c00000001fffff44000000 - 40420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 40420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40420 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000800000001fffff44000000 - 40420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 40420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 40420 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 40420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 40420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:936 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4042 -instret:937 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4042 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000000000001fffff44000000 - 40430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 40430 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000004000000001fffff44000000 - 40430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40430 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 40430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 40430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:938 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4043 -instret:939 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4043 -calling cycle - 40440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 40440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40440 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 000000002000015f000000001fffff44000000 - 40440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 40440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800010f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 40440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 - 40450 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 40450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40450 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 40450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } - 40460 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 40460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40460 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 - 40460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40460 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 40460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } +instret:540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3372 calling cycle - 40470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle - 40480 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40480 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 40480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 40490 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 40490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 40500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 40510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40510 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 40510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 40520 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001c00000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:940 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4054 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } -instret:941 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4055 +instret:541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3381 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:942 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4057 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 40630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 40640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 40640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 40650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 40660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 40660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 40670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 40670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 40670 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 40670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:943 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4067 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 40680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40680 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 43 <= 40000000200004021008ffff1ffff805821008 - 40680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 40680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 40680 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 40680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 40690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40690 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 - 40690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 40690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 40690 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 40690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40700 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 40700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 40700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 40700 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 40700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:944 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4070 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40710 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001c00000001fffff44000000 - 40710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:945 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4071 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:946 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4072 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h3fd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } +instret:542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3390 calling cycle - 40740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 40740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 40740 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 40740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7a <= 0000000000000006000000001fffff44000000 - 40750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40750 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001c00000001fffff44000000 - 40750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 40760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:947 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4076 -instret:948 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4076 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 40770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 40770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 40770 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 40770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 40770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000002000000001fffff44000000 - 40780 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 40780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000007c00000001fffff44000000 - 40790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 40790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fe, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 000000000000003e000000001fffff44000000 - 40800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 40800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001100 -After delta: vaddr = 0x80001100 - 40800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:949 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4080 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 40000000200004401100ffff1ffff805821008 - 40810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001100 o: 'h00000000000000f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001100 o: 'h00000000000000f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001100, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 40810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 40810 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 40810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:950 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4081 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 40820 : [doFinishMem] DTlbResp { resp: <'h0000000080001100,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001100 o: 'h00000000000000f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001100, check_high: 'h00000000080001108, check_inclusive: True } }, specBits: 'h000 } - 40820 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000800000001fffff44000000 - 40820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 40820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:951 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4082 -instret:952 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4082 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 40830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 40830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 40830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:953 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4083 -instret:954 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4083 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 40840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001100, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 40840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 40840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 40840 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 40840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 40840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:955 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4084 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 00000000200003dc000000001fffff44000000 -[RFile] wr_ 1: r 71 <= 0000000000000000c00000001fffff44000000 - 40850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h014 } - 40850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40850 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000800000001fffff44000000 - 40850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 40850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 40850 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 40850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 40850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:956 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4085 -instret:957 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4085 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h016, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000000000001fffff44000000 - 40860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 40860 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000004000000001fffff44000000 - 40860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 40860 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 40860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 40860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 40860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:958 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4086 -instret:959 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4086 -calling cycle - 40870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h014 } - 40870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40870 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 000000002000015f000000001fffff44000000 - 40870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 40870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 40870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000020000400000000001fffff44000000 - 40880 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h016 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 40880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 40880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 40880 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 40880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -calling cycle -[ALU redirect - 0] 'h1ffff0000000000000000000080000050; 'h4; InstTag { way: 'h0, ptr: 'h19, t: 'h32 } - 40890 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h016 } - 40890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40890 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000020000400000000001fffff44000000 - 40890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 40890 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 40890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } -calling cycle - 40900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h19, t: 'h32 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 40910 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 40910 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 40910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 40920 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 40920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 40920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 40920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 40920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -calling cycle - 40930 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 40930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 40930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 40930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 40940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 40940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 40940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 40940 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 40940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 40950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001180, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 40950 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:960 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4097 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } -instret:961 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4098 -calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h14, t: 'h29 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -instret:962 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 41090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 41100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 41100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41100 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 41100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:963 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4110 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 41110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 41110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41110 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004021008ffff1ffff805821008 - 41110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41110 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 41120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41120 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000800000001fffff44000000 - 41120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41120 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 41120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41130 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 41130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:964 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4113 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002000000001fffff44000000 - 41140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:965 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4114 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:966 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4115 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } calling cycle - 41170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 41170 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 40 <= 0000000000000006000000001fffff44000000 - 41180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41180 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000002000000001fffff44000000 - 41180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 41190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:967 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4119 -instret:968 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4119 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 41200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41200 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 41200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000002400000001fffff44000000 - 41210 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 41210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000008000000001fffff44000000 - 41220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000040000000001fffff44000000 - 41230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 41230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001108 -After delta: vaddr = 0x80001108 - 41230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:969 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4123 -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200004421108ffff1ffff805821008 - 41240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001108 o: 'h0000000000000100 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001108 o: 'h0000000000000100 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001108, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 41240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 41240 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 41240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:970 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4124 -calling cycle - 41250 : [doFinishMem] DTlbResp { resp: <'h0000000080001108,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001108 o: 'h0000000000000100 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001108, check_high: 'h00000000080001110, check_inclusive: True } }, specBits: 'h000 } - 41250 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000800000001fffff44000000 - 41250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:971 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4125 -instret:972 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4125 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 41260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:973 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4126 -instret:974 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4126 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001108, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 41270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 41270 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:975 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4127 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000c00000001fffff44000000 - 41280 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000800000001fffff44000000 - 41280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 41280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 41280 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 41280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:976 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4128 -instret:977 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4128 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h3fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000 - 41290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 41290 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000004000000001fffff44000000 - 41290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:978 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4129 -instret:979 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4129 -calling cycle - 41300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 41300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } calling cycle - 41310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 41310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 41310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 41320 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41330 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 41330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41340 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000002400000001fffff44000000 - 41340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41340 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 41340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 41350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41350 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 41350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 41360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41360 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 41360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:980 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4136 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } - 41370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 41370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41370 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6b <= 40000000200004021008ffff1ffff805821008 - 41370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:981 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4137 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1e, t: 'h3d } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 41390 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 41390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41390 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 41390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:982 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4139 calling cycle - 41400 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 41430 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001180, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 41430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3399 calling cycle - 41440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 41440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 41440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 41450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 41460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 41470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 41470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41470 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 41470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:983 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4147 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 41480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 41480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41480 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 41480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41480 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 41480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 41490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41490 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000800000001fffff44000000 - 41490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41490 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 41490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41500 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 41500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 41500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 41500 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 41500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:984 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4150 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41510 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002400000001fffff44000000 - 41510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:985 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4151 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:986 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4152 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 41530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 41540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 41540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 41540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7d <= 0000000000000006000000001fffff44000000 - 41550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 41550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 41550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 41560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:987 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4156 -instret:988 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4156 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 41570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41570 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 41570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000002800000001fffff44000000 - 41580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 41580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41580 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 41580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41580 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 41580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000008400000001fffff44000000 - 41590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 41590 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 69 <= 40000000200004021008ffff1ffff805821008 - 41590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41590 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 41590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000042000000001fffff44000000 - 41600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 41600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41600 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000800000001fffff44000000 - 41600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001110 -After delta: vaddr = 0x80001110 - 41600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:989 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4160 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 40000000200004441110ffff1ffff805821008 - 41610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 41610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001110 o: 'h0000000000000108 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001110 o: 'h0000000000000108 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001110, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41610 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 41610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:990 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4161 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 - 41620 : [doFinishMem] DTlbResp { resp: <'h0000000080001110,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001110 o: 'h0000000000000108 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001110, check_high: 'h00000000080001118, check_inclusive: True } }, specBits: 'h000 } - 41620 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 41620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:991 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4162 -instret:992 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4162 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 - 41630 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002800000001fffff44000000 - 41630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:993 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4163 -instret:994 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4163 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001110, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 41640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:995 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4164 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41650 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002800000001fffff44000000 - 41650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 41650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:996 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4165 -instret:997 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4165 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 41660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:998 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4166 -instret:999 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4166 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 08 <= 0000000000000006000000001fffff44000000 - 41670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 41670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000002c00000001fffff44000000 - 41680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 41680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41680 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 41680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 41690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 41690 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 - 41690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41690 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 41690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 41700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 41700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41700 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 41700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 41700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000008800000001fffff44000000 - 41710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 41710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41710 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 41710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000044000000001fffff44000000 - 41720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 41720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41720 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000800000001fffff44000000 - 41720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41720 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 41720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001118 -After delta: vaddr = 0x80001118 - 41720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 40000000200004461118ffff1ffff805821008 - 41730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41730 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002800000001fffff44000000 - 41730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001118 o: 'h0000000000000110 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001118 o: 'h0000000000000110 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001118, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41730 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 41730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41740 : [doFinishMem] DTlbResp { resp: <'h0000000080001118,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001118 o: 'h0000000000000110 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001118, check_high: 'h00000000080001120, check_inclusive: True } }, specBits: 'h004 } - 41740 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003000000001fffff44000000 - 41740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 41750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41750 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002c00000001fffff44000000 - 41750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1000 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4175 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 41760 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002c00000001fffff44000000 - 41760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1001 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4176 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00b } - 41770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1002 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4177 -instret:1003 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4177 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 41780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1004 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4178 -instret:1005 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4178 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 5e <= 0000000000000006000000001fffff44000000 - 41790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 41790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41790 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 41790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1006 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4179 -instret:1007 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4179 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 41800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 41800 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 41800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41800 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 41800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1008 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4180 -instret:1009 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4180 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 41810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41810 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 41810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1010 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4181 -instret:1011 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4181 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 41820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 41820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41820 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 41820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1012 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4182 -instret:1013 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4182 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000008c00000001fffff44000000 - 41830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 41830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41830 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 - 41830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41830 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 41830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1014 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4183 -instret:1015 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4183 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000046000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001118, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 41840 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 41840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001120 -After delta: vaddr = 0x80001120 - 41840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1016 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4184 -instret:1017 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4184 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 60 <= 40000000200004481120ffff1ffff805821008 - 41850 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 41850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001120 o: 'h0000000000000118 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001120 o: 'h0000000000000118 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001120, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 41850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1018 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4185 -instret:1019 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4185 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 1000000000000000040000001fffff44000000 - 41860 : [doFinishMem] DTlbResp { resp: <'h0000000080001120,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001120 o: 'h0000000000000118 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001120, check_high: 'h00000000080001128, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 41860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 41870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 41870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 41870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 41880 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41880 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 41880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000006000000001fffff44000000 - 41890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 41890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 41890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 41890 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 41890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 41890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 41900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41900 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002c00000001fffff44000000 - 41900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 41900 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 41900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 41910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41910 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 41910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 41910 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 41910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 41920 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200004021008ffff1ffff805821008 - 41920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 41920 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 41920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1020 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4192 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000009000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 41930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 41930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 41930 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000800000001fffff44000000 - 41930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 41930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1021 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4193 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000048000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 41940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 41940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 41940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 41940 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 41940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 41940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001128 -After delta: vaddr = 0x80001128 - 41940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1022 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4194 -instret:1023 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4194 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 73 <= 400000002000044a1128ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41950 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 41950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001128, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1024 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4195 -instret:1025 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4195 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41960 : [doFinishMem] DTlbResp { resp: <'h0000000080001128,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001128, check_high: 'h00000000080001130, check_inclusive: True } }, specBits: 'h010 } - 41960 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003400000001fffff44000000 - 41960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1026 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4196 -instret:1027 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4196 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 41970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 41970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 41970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1028 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4197 -instret:1029 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4197 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 41980 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003400000001fffff44000000 - 41980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 41980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1030 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4198 -instret:1031 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4198 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 41990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 41990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 41990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 41990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1032 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4199 -instret:1033 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4199 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 02 <= 0000000000000006000000001fffff44000000 - 42000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 42000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1034 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4200 -instret:1035 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4200 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000003800000001fffff44000000 - 42010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001120, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 42010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42010 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 42010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1036 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4201 -instret:1037 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4201 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 42020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 42020 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003000000001fffff44000000 - 42020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42020 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 42020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1038 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4202 -instret:1039 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4202 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 42030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 42030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42030 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200004021008ffff1ffff805821008 - 42030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 42030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 42030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000009400000001fffff44000000 - 42040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 42040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42040 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 42040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 000000000000004a000000001fffff44000000 - 42050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 42050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42050 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000800000001fffff44000000 - 42050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42050 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 42050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001130 -After delta: vaddr = 0x80001130 - 42050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 70 <= 400000002000044c1130ffff1ffff805821008 - 42060 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 - 42060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001130, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 42060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 42060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 1000000000000000040000001fffff44000000 - 42070 : [doFinishMem] DTlbResp { resp: <'h0000000080001130,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001130, check_high: 'h00000000080001138, check_inclusive: True } }, specBits: 'h014 } - 42070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42070 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003800000001fffff44000000 - 42070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 42080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 42080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 42080 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 42080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42090 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 42090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 42100 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003800000001fffff44000000 - 42100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 47 <= 0000000000000006000000001fffff44000000 - 42110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 42110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1040 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4211 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } - 42120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42120 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 42120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1041 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4212 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 42140 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:1042 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4214 calling cycle calling cycle calling cycle calling cycle +instret:544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3408 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 42220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3f5, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 42240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:1043 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 4224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 42250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 42250 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 42250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:1044 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 42260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42260 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 - 42260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 42270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 42270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 42270 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 42270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000000000001fffff44000000 - 42280 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000800000001fffff44000000 - 42280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 42280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 42280 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 42280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1045 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4228 -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000000c00000001fffff44000000 - 42290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 42290 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 - 42290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 42300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:1046 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 4230 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 42310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1047 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 4231 -instret:1048 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 4231 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 42320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 42320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42330 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 42330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 42340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42340 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 42340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 42340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 42340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 42350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 42350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42350 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 42350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 42360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 42360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42360 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 42360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42360 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 42360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 42370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 42370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42370 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 42370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42370 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 42370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42380 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 42380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000400000001fffff44000000 - 42390 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 - 42390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 1000000000000000040000001fffff44000000 - 42400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 42410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42420 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000000000001fffff44000000 - 42420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 55 <= 0000000000000009000000001fffff44000000 - 42430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 42430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 42440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000400000001fffff44000000 - 42450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 42450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42450 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 42450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 42460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 42460 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 42460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42460 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 42460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000009000000001fffff44000000 - 42470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 42470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42470 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 42470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000048000000001fffff44000000 - 42480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 42480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42480 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 42480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001128 -After delta: vaddr = 0x80001128 - 42480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 400000002000044a1128ffff1ffff805821008 - 42490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 42490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42490 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 42490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001128, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42490 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 42490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000400000001fffff44000000 - 42500 : [doFinishMem] DTlbResp { resp: <'h0000000080001128,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001128, check_high: 'h00000000080001130, check_inclusive: True } }, specBits: 'h004 } - 42500 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 42500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 - 42510 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 - 42510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 42520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42530 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000000400000001fffff44000000 - 42530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 42540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 56 <= 0000000000000009000000001fffff44000000 - 42550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 42550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000800000001fffff44000000 - 42560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 42560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42560 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 42560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 42570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 42570 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 42570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42570 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 42570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 42580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 42580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42580 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 42580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000009400000001fffff44000000 - 42590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 42590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42590 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 42590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 000000000000004a000000001fffff44000000 - 42600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 42600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42600 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 - 42600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42600 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 42600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001130 -After delta: vaddr = 0x80001130 - 42600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3417 calling cycle calling cycle - 42620 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle - 42630 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3fa, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 42690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 42710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 42720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 42720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 42720 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 42720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000000000001fffff44000000 - 42730 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000c00000001fffff44000000 - 42730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 42730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 42730 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 42730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 42740 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 - 42740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 42750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1049 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4275 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h001 } - 42760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1050 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 4276 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h019 } - 42770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42770 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 42770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 42780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 42780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42780 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 42780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42780 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 42780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1051 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4278 -instret:1052 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4278 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 42790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42790 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 42790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42790 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 42790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1053 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 4279 -instret:1054 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 4279 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 42800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 42800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42800 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 42800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42800 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 42800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:1055 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 4280 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42810 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 42810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 42810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 42810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000400000001fffff44000000 - 42820 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42820 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 - 42820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 1000000000000000040000001fffff44000000 - 42830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 42830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 42830 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 42830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h1ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h009 } - 42840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42840 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 - 42840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 42850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 42850 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 42850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 55 <= 0000000000000009000000001fffff44000000 - 42860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 42860 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000000000001fffff44000000 - 42860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1056 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4286 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 42870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 42870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1057 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4287 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h014 } - 42880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42880 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 42880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1058 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4288 -instret:1059 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4288 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 42890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42890 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 42890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 42890 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 42890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1060 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4289 -instret:1061 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4289 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000009000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 42900 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 42900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 42900 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 42900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1062 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4290 -instret:1063 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4290 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000048000000001fffff44000000 - 42910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 42910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42910 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 42910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001128 -After delta: vaddr = 0x80001128 - 42910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1064 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4291 -instret:1065 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4291 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 400000002000044a1128ffff1ffff805821008 - 42920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 42920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001128, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 42920 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 42920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1066 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4292 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000400000001fffff44000000 - 42930 : [doFinishMem] DTlbResp { resp: <'h0000000080001128,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001128 o: 'h0000000000000120 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001128, check_high: 'h00000000080001130, check_inclusive: True } }, specBits: 'h000 } - 42930 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 42930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1067 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4293 -instret:1068 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4293 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 1000000000000000040000001fffff44000000 - 42940 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 - 42940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1069 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4294 -instret:1070 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4294 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 42950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001128, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 42950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 42950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1071 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4295 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42960 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000000400000001fffff44000000 - 42960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 42960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 42960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 42960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1072 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4296 -instret:1073 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4296 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 42970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 42970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 42970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1074 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4297 -instret:1075 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4297 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 56 <= 0000000000000009000000001fffff44000000 - 42980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 42980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 42980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 42980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 0000000000000000800000001fffff44000000 - 42990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 42990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 42990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 42990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 42990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 42990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 42990 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 42990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 42990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 42990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 42990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 43000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 43000 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 43000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43000 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 43000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 43010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43010 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 43010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000009400000001fffff44000000 - 43020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 43020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43020 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 43020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 000000000000004a000000001fffff44000000 - 43030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 43030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43030 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 - 43030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43030 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 43030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001130 -After delta: vaddr = 0x80001130 - 43030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 400000002000044c1130ffff1ffff805821008 - 43040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43040 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 43040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001130, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43040 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43050 : [doFinishMem] DTlbResp { resp: <'h0000000080001130,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001130 o: 'h0000000000000128 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001130, check_high: 'h00000000080001138, check_inclusive: True } }, specBits: 'h004 } - 43050 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 43050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h2ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 43060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43060 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000800000001fffff44000000 - 43060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1076 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4306 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 43070 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000800000001fffff44000000 - 43070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1077 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4307 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 43080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1078 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4308 -instret:1079 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4308 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 43090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1080 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4309 -instret:1081 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4309 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 6e <= 0000000000000009000000001fffff44000000 - 43100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 43100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43100 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 43100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1082 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4310 -instret:1083 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4310 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 43110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 43110 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 43110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43110 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 43110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1084 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4311 -instret:1085 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4311 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 43120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43120 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 43120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1086 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4312 -instret:1087 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 43130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 43130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43130 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 43130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1088 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4313 -instret:1089 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4313 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000009800000001fffff44000000 - 43140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 43140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43140 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000000c00000001fffff44000000 - 43140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43140 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 43140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1090 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4314 -instret:1091 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4314 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 000000000000004c000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001130, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 43150 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 43150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001138 -After delta: vaddr = 0x80001138 - 43150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1092 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4315 -instret:1093 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4315 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 400000002000044e1138ffff1ffff805821008 -[RFile] wr_ 1: r 0c <= 0000000000000000400000001fffff44000000 - 43160 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000c00000001fffff44000000 - 43160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001138 o: 'h0000000000000130 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001138 o: 'h0000000000000130 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001138, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 43160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1094 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4316 -instret:1095 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4316 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h2ff, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 1000000000000000040000001fffff44000000 - 43170 : [doFinishMem] DTlbResp { resp: <'h0000000080001138,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001138 o: 'h0000000000000130 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001138, check_high: 'h00000000080001140, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 43170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 43180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 43190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43190 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000c00000001fffff44000000 - 43190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 74 <= 0000000000000009000000001fffff44000000 - 43200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 43200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43200 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 43200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 43210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43210 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 - 43210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43210 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 43210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 43220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43220 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 43220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43220 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 43220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 43230 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200004021008ffff1ffff805821008 - 43230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43230 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 43230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1096 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4323 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 0000000000000009c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 43240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 43240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43240 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 - 43240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1097 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4324 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 000000000000004e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 43250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43250 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 43250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001140 -After delta: vaddr = 0x80001140 - 43250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1098 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4325 -instret:1099 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4325 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200004501140ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43260 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 43260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001140 o: 'h0000000000000138 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001140 o: 'h0000000000000138 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001140, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1100 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4326 -instret:1101 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4326 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43270 : [doFinishMem] DTlbResp { resp: <'h0000000080001140,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001140 o: 'h0000000000000138 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001140, check_high: 'h00000000080001148, check_inclusive: True } }, specBits: 'h010 } - 43270 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000001000000001fffff44000000 - 43270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1102 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4327 -instret:1103 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4327 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 1000000000000000040000001fffff44000000 - 43280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 43280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1104 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4328 -instret:1105 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4328 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43290 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001000000001fffff44000000 - 43290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h017 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1106 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4329 -instret:1107 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4329 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 43300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1108 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4330 -instret:1109 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4330 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 0000000000000009000000001fffff44000000 - 43310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 43310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1110 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4331 -instret:1111 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4331 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000001400000001fffff44000000 - 43320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001138, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 43320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43320 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 43320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1112 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4332 -instret:1113 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4332 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 43330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 43330 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003000000001fffff44000000 - 43330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43330 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 43330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1114 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4333 -instret:1115 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4333 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 43340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 43340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43340 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200004021008ffff1ffff805821008 - 43340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 43340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 000000000000000a000000001fffff44000000 - 43350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 43350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 43350 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 43350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000050000000001fffff44000000 - 43360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 43360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43360 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000c00000001fffff44000000 - 43360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43360 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 43360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001148 -After delta: vaddr = 0x80001148 - 43360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 43 <= 40000000200004521148ffff1ffff805821008 - 43370 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 - 43370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001148 o: 'h0000000000000140 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001148 o: 'h0000000000000140 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001148, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 1000000000000000040000001fffff44000000 - 43380 : [doFinishMem] DTlbResp { resp: <'h0000000080001148,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001148 o: 'h0000000000000140 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001148, check_high: 'h00000000080001150, check_inclusive: True } }, specBits: 'h014 } - 43380 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43380 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001400000001fffff44000000 - 43380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 43390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43390 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 43390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43400 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000c00000001fffff44000000 - 43400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 43410 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001400000001fffff44000000 - 43410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 5a <= 0000000000000009000000001fffff44000000 - 43420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 43420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1116 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4342 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 43430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43430 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 43430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1117 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4343 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43440 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 43440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:1118 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4344 -instret:1119 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4344 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 43450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1120 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4345 -instret:1121 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4345 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000000a400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1122 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4346 -instret:1123 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4346 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000052000000001fffff44000000 - 43470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001150 -After delta: vaddr = 0x80001150 - 43470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1124 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4347 -instret:1125 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4347 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3fd, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 40000000200004541150ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 43480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001150 o: 'h0000000000000148 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001150 o: 'h0000000000000148 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001150, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:1126 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4348 -instret:1127 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4348 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43490 : [doFinishMem] DTlbResp { resp: <'h0000000080001150,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001150 o: 'h0000000000000148 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001150, check_high: 'h00000000080001158, check_inclusive: True } }, specBits: 'h00c } - 43490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 43490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 43490 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 43490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:1128 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4349 -instret:1129 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4349 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02d } - 43500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43500 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 - 43500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:1130 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4350 -instret:1131 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4350 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001140, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 43510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 43510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 43510 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 43510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:1132 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4351 -instret:1133 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4351 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h07e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000000000000000000001fffff44000000 - 43520 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000c00000001fffff44000000 - 43520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 43520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 43520 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 43520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h07e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1134 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4352 -instret:1135 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4352 -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000001000000001fffff44000000 - 43530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 43530 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000004000000001fffff44000000 - 43530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 43530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 43540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 43550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800011c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 43560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800011c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 43560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 43560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 43570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h06d } - 43570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43570 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 43570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 43580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800011c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800011c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 43580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02d } - 43580 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43580 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001000000001fffff44000000 - 43580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43580 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 43580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02d } - 43590 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43590 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 43590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43590 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 43590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43600 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43600 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200004021008ffff1ffff805821008 - 43600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1136 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4360 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 43610 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001000000001fffff44000000 - 43610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43610 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 43610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:1137 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4361 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43620 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 43620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1138 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4362 -instret:1139 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4362 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h029 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1140 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4363 -instret:1141 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4363 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h029 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:1142 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4364 -instret:1143 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4364 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h029 } - 43650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:1144 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4365 -instret:1145 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4365 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h029, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43660 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 -instret:1146 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4366 -instret:1147 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4366 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 70 <= 000000000000000c000000001fffff44000000 - 43670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1148 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4367 -instret:1149 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4367 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000000400000001fffff44000000 - 43680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1150 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4368 -instret:1151 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4368 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001148, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 43690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1152 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4369 -instret:1153 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4369 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h37f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h029 } - 43700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 43700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1154 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4370 -instret:1155 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4370 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 000000000000000c000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 43710 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 43710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000060000000001fffff44000000 - 43720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h029 } - 43720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h029 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h029 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001188 -After delta: vaddr = 0x80001188 - 43720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h029, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 40000000200004621188ffff1ffff805821008 - 43730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h029 } - 43730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h029 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001188, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h029 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000000400000001fffff44000000 - 43740 : [doFinishMem] DTlbResp { resp: <'h0000000080001188,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001188, check_high: 'h00000000080001190, check_inclusive: True } }, specBits: 'h029 } - 43740 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h029 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43740 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 43740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 43750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h029 } - 43750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001400000001fffff44000000 - 43750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43750 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 43750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h039 } - 43760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43760 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 43760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h039 } - 43770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43770 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 43770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:1156 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4377 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 43780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h039 } - 43780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43780 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 56 <= 40000000200004021008ffff1ffff805821008 - 43780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1157 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4378 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43790 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001000000001fffff44000000 - 43790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43790 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 43790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1158 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4379 -instret:1159 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4379 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43800 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 43800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h031 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1160 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4380 -instret:1161 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4380 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:1162 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4381 -instret:1163 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4381 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h031 } - 43820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:1164 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4382 -instret:1165 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4382 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h031, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43830 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000400000001fffff44000000 -instret:1166 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4383 -instret:1167 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4383 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1168 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4384 -instret:1169 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4384 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h033, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h033, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 5f <= 000000000000000c000000001fffff44000000 - 43850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h033 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1170 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4385 -instret:1171 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4385 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001150, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 43860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h033 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1172 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4386 -instret:1173 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4386 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h3bf, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 43870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h031 } - 43870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 43870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1174 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4387 -instret:1175 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4387 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 43880 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000400000001fffff44000000 - 43880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 43880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 000000000000000c400000001fffff44000000 - 43890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h031 } - 43890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 43890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 43890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 43890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000062000000001fffff44000000 - 43900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h031 } - 43900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 43900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h031 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001190 -After delta: vaddr = 0x80001190 - 43900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h031, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 1: r 57 <= 40000000200004641190ffff1ffff805821008 - 43910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03b } - 43910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001190, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 43910 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 43910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h031 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 43910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000800000001fffff44000000 - 43920 : [doFinishMem] DTlbResp { resp: <'h0000000080001190,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001190, check_high: 'h00000000080001198, check_inclusive: True } }, specBits: 'h031 } - 43920 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43920 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001800000001fffff44000000 - 43920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h031 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 43920 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 43920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 43920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 43920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h031 } - 43930 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 43930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 43930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 43930 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 43930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 43930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 43940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h039 } - 43940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 43940 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6e <= 40000000200004021008ffff1ffff805821008 - 43940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:1176 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4394 +instret:546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3426 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h5; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } - 43950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h039 } - 43950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 43950 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001000000001fffff44000000 - 43950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1177 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4395 calling cycle -[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h00, t: 'h01 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 43970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 43970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 43970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 43970 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 43970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:1178 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4397 calling cycle - 43980 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 44030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3435 calling cycle - 44040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800011c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 44060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 44060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 44070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 44070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 44070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800011c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 44070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1179 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4407 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 44080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 44080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44080 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 44080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44090 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44090 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6f <= 40000000200004021008ffff1ffff805821008 - 44090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44090 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 44090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 44100 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44100 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 - 44100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44100 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 44100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44110 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 44110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 44110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 44110 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 44110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1180 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4411 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44120 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000001800000001fffff44000000 - 44120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1181 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4412 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bf, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:1182 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4413 -calling cycle - 44140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 44140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 44140 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 44140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44150 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001800000001fffff44000000 - 44150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5c <= 0000000000000009000000001fffff44000000 - 44160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 44160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 44170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44170 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 44170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1183 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4417 -instret:1184 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4417 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000001c00000001fffff44000000 - 44180 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 44180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 44190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3fd, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 000000000000000a800000001fffff44000000 - 44200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h006 } - 44200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000054000000001fffff44000000 - 44210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 44210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 44210 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 44210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001158 -After delta: vaddr = 0x80001158 - 44210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1185 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4421 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200004561158ffff1ffff805821008 - 44220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 44220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44220 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 44220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001158 o: 'h0000000000000150 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001158 o: 'h0000000000000150 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001158, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 44220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -instret:1186 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4422 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44230 : [doFinishMem] DTlbResp { resp: <'h0000000080001158,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001158 o: 'h0000000000000150 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001158, check_high: 'h00000000080001160, check_inclusive: True } }, specBits: 'h000 } - 44230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 44230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 44230 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 44230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1187 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4423 -instret:1188 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4423 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h3bf, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000000000000001fffff44000000 - 44240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h004 } - 44240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44240 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000c00000001fffff44000000 - 44240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:1189 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4424 -instret:1190 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4424 -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001158, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 44250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 44250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 44250 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 44250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h016, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1191 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4425 -calling cycle - 44260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 44260 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000004000000001fffff44000000 - 44260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 44260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:1192 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4426 -instret:1193 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4426 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 44270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1194 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4427 -instret:1195 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4427 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 44280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44290 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 44300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44300 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 44300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 44300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 44310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 44310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44310 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 44320 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44320 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 56 <= 40000000200004021008ffff1ffff805821008 - 44320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44320 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 44320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 44330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44330 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000001c00000001fffff44000000 - 44330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44340 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44340 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001000000001fffff44000000 - 44340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44340 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 44340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44350 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 44350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1196 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4435 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } - 44360 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 - 44360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1197 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4436 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:1198 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4438 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 44420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 44430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3444 calling cycle - 44440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 44450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 44460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44460 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 44460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1199 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 4446 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 44470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 44470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44470 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6b <= 40000000200004021008ffff1ffff805821008 - 44470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44470 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 44470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 44480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44480 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 44480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44480 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 44480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44490 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 44490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 44490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 44490 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 44490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1200 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4449 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44500 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001c00000001fffff44000000 - 44500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1201 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 4450 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1202 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4451 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 44520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 44530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 44530 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 44530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 79 <= 0000000000000009000000001fffff44000000 - 44540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 44540 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001c00000001fffff44000000 - 44540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 44550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1203 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 4455 -instret:1204 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 4455 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 44560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44560 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 44560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000002000000001fffff44000000 - 44570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 44570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44570 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 44570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44570 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 44570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 000000000000000ac00000001fffff44000000 - 44580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 44580 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200004021008ffff1ffff805821008 - 44580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44580 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 44580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000056000000001fffff44000000 - 44590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 44590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44590 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 44590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001160 -After delta: vaddr = 0x80001160 - 44590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1205 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 4459 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 40000000200004581160ffff1ffff805821008 - 44600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 44600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001160 o: 'h0000000000000158 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001160 o: 'h0000000000000158 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001160, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44600 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 44600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1206 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4460 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000000400000001fffff44000000 - 44610 : [doFinishMem] DTlbResp { resp: <'h0000000080001160,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001160 o: 'h0000000000000158 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001160, check_high: 'h00000000080001168, check_inclusive: True } }, specBits: 'h000 } - 44610 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 44610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1207 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4461 -instret:1208 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4461 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 1000000000000000040000001fffff44000000 - 44620 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 44620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1209 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4462 -instret:1210 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4462 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001160, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 44630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1211 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4463 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44640 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 44640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 44640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1212 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4464 -instret:1213 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4464 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 44650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1214 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4465 -instret:1215 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4465 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 57 <= 0000000000000009000000001fffff44000000 - 44660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 44660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000002400000001fffff44000000 - 44670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 44670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44670 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 44670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 44680 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 44680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44680 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 44680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 44690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 44690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44690 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 44690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 44690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 000000000000000b000000001fffff44000000 - 44700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 44700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44700 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 44700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000058000000001fffff44000000 - 44710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 44710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44710 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000c00000001fffff44000000 - 44710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44710 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 44710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001168 -After delta: vaddr = 0x80001168 - 44710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 400000002000045a1168ffff1ffff805821008 - 44720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44720 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000002000000001fffff44000000 - 44720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001168 o: 'h0000000000000160 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001168 o: 'h0000000000000160 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001168, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44720 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 44720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44730 : [doFinishMem] DTlbResp { resp: <'h0000000080001168,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001168 o: 'h0000000000000160 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001168, check_high: 'h00000000080001170, check_inclusive: True } }, specBits: 'h004 } - 44730 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 44730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 44740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44740 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000002400000001fffff44000000 - 44740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1216 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4474 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 44750 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002400000001fffff44000000 - 44750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1217 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4475 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00b } - 44760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1218 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4476 -instret:1219 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4476 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 44770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1220 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4477 -instret:1221 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4477 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 73 <= 0000000000000009000000001fffff44000000 - 44780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 44780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44780 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 44780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1222 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4478 -instret:1223 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4478 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 44790 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 44790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44790 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 44790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1224 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4479 -instret:1225 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4479 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 44800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44800 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0c <= 40000000200004021008ffff1ffff805821008 - 44800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1226 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4480 -instret:1227 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4480 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 44810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 44810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44810 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 44810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1228 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4481 -instret:1229 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4481 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 000000000000000b400000001fffff44000000 - 44820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 44820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44820 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000000c00000001fffff44000000 - 44820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44820 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 44820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1230 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4482 -instret:1231 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4482 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 000000000000005a000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001168, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 44830 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 44830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001170 -After delta: vaddr = 0x80001170 - 44830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1232 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4483 -instret:1233 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4483 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 4b <= 400000002000045c1170ffff1ffff805821008 - 44840 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 44840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001170 o: 'h0000000000000168 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001170 o: 'h0000000000000168 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001170, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 44840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1234 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4484 -instret:1235 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4484 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 1000000000000000040000001fffff44000000 - 44850 : [doFinishMem] DTlbResp { resp: <'h0000000080001170,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001170 o: 'h0000000000000168 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001170, check_high: 'h00000000080001178, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 44850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 44860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 44860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 44860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 44870 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44870 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002800000001fffff44000000 - 44870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 70 <= 0000000000000009000000001fffff44000000 - 44880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 44880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 44880 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 44880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 44880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 44890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44890 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002400000001fffff44000000 - 44890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 44890 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 44890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 44900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44900 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003000000001fffff44000000 - 44900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 44900 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 44900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 44910 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 44910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 44910 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 44910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1236 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4491 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 000000000000000b800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 44920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 44920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44920 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 - 44920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1237 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4492 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 000000000000005c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 44930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 44930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 44930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 44930 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 44930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 44930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001178 -After delta: vaddr = 0x80001178 - 44930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1238 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4493 -instret:1239 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4493 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 75 <= 400000002000045e1178ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44940 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 44940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001178 o: 'h0000000000000170 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001178 o: 'h0000000000000170 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001178, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1240 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4494 -instret:1241 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4494 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44950 : [doFinishMem] DTlbResp { resp: <'h0000000080001178,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001178 o: 'h0000000000000170 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001178, check_high: 'h00000000080001180, check_inclusive: True } }, specBits: 'h010 } - 44950 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000002c00000001fffff44000000 - 44950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1242 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4495 -instret:1243 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4495 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 44960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 44960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1244 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4496 -instret:1245 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4496 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 44970 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002c00000001fffff44000000 - 44970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 44970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1246 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4497 -instret:1247 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4497 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 44980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 44980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 44980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 44980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1248 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4498 -instret:1249 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4498 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5f <= 0000000000000009000000001fffff44000000 - 44990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 44990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 44990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 44990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 44990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 44990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1250 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4499 -instret:1251 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4499 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000003000000001fffff44000000 - 45000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001170, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 45000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45000 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 45000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1252 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4500 -instret:1253 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4500 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 45010 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 45010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45010 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 45010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1254 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4501 -instret:1255 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4501 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 45020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 45020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45020 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 45020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 45020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 000000000000000bc00000001fffff44000000 - 45030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 45030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45030 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 45030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 000000000000005e000000001fffff44000000 - 45040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 45040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45040 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000c00000001fffff44000000 - 45040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45040 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 45040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001180 -After delta: vaddr = 0x80001180 - 45040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 43 <= 40000000200004601180ffff1ffff805821008 - 45050 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 45050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001180 o: 'h0000000000000178 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001180 o: 'h0000000000000178 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001180, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 45050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 - 45060 : [doFinishMem] DTlbResp { resp: <'h0000000080001180,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001180 o: 'h0000000000000178 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001180, check_high: 'h00000000080001188, check_inclusive: True } }, specBits: 'h014 } - 45060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45060 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 45060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 45070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45070 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 45070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45080 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002800000001fffff44000000 - 45080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 45090 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 45090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 53 <= 0000000000000009000000001fffff44000000 - 45100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 45100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1256 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4510 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 45110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45110 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 45110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1257 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4511 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45120 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 45120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1258 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4512 -instret:1259 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4512 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 45130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 45130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1260 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4513 -instret:1261 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4513 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 000000000000000c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 45140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1262 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4514 -instret:1263 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4514 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000060000000001fffff44000000 - 45150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 45150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001188 -After delta: vaddr = 0x80001188 - 45150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1264 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4515 -instret:1265 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4515 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 40000000200004621188ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 45160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001188, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45160 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 45160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1266 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4516 -instret:1267 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4516 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45170 : [doFinishMem] DTlbResp { resp: <'h0000000080001188,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001188, check_high: 'h00000000080001190, check_inclusive: True } }, specBits: 'h00c } - 45170 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0b <= 40000000200004021008ffff1ffff805821008 - 45170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45170 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 45170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1268 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4517 -instret:1269 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4517 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 45180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45180 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 - 45180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1270 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4518 -instret:1271 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4518 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001178, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 45190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45190 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 45190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1272 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4519 -instret:1273 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4519 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000400000001fffff44000000 - 45200 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 45200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 45200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1274 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4520 -instret:1275 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4520 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 45210 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003400000001fffff44000000 - 45210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 45220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 45220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45230 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003400000001fffff44000000 - 45230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 45240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 45240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45240 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 45240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 0000000000000009000000001fffff44000000 - 45250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 45250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45250 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002c00000001fffff44000000 - 45250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45260 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 45260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 45270 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 -instret:1276 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4527 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1277 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4528 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 000000000000000c400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1278 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4529 -instret:1279 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4529 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000062000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001190 -After delta: vaddr = 0x80001190 - 45300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1280 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4530 -instret:1281 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4530 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 40000000200004641190ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001190, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 45310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1282 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4531 -instret:1283 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4531 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45320 : [doFinishMem] DTlbResp { resp: <'h0000000080001190,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001190, check_high: 'h00000000080001198, check_inclusive: True } }, specBits: 'h028 } - 45320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 45320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1284 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4532 -instret:1285 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4532 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 45330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1286 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4533 -instret:1287 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4533 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 45340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45340 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 45340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1288 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4534 -instret:1289 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4534 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 45350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45350 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 01 <= 40000000200004021008ffff1ffff805821008 - 45350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45350 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 45350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1290 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4535 -instret:1291 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4535 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001180, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 45360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45360 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 45360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45360 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 45360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1292 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4536 -instret:1293 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4536 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000000400000001fffff44000000 - 45370 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 45370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 45370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1294 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4537 -instret:1295 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4537 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 45380 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003800000001fffff44000000 - 45380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 45390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 45390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45400 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45400 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003800000001fffff44000000 - 45400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 45400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 45400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 45410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 45410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 45410 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 45410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45420 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001200, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 4a <= 0000000000000009000000001fffff44000000 - 45420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 45420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45420 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 45420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45430 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 45430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 45440 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 -instret:1296 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4544 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006a; 'h3; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:1297 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4545 calling cycle -[ROB incorrectSpec] 'h3 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:1298 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4547 calling cycle +instret:549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3453 calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 45540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 45550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 45560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3fd, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 45570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 45570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:1299 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 4557 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 45580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 45580 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 45580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:1300 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4558 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 45590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45590 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000c00000001fffff44000000 - 45590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 45600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 45600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 45600 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 45600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000000000000001fffff44000000 - 45610 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000c00000001fffff44000000 - 45610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 45610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 45610 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 45610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1301 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4561 -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000001000000001fffff44000000 - 45620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 45620 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 45620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3462 calling cycle - 45630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 45630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:1302 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 4563 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 45640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1303 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 4564 -instret:1304 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 4564 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 45650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 45650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 45650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 45660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 45660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45660 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 45660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 45670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45670 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 45670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 45670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 45670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 45680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45680 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 45680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 45690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 45690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45690 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 45690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45690 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 45690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 45700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45700 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001000000001fffff44000000 - 45700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45700 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 45700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45710 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 45710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000000400000001fffff44000000 - 45720 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 - 45720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 1000000000000000040000001fffff44000000 - 45730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 45740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 45740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45750 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 - 45750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 49 <= 000000000000000c000000001fffff44000000 - 45760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 45760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 45760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 45770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 45770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 - 45780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 45780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45780 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 45780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 45790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 45790 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 45790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45790 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 45790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 000000000000000c000000001fffff44000000 - 45800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 45800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45800 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 45800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000060000000001fffff44000000 - 45810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 45810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45810 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 45810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001188 -After delta: vaddr = 0x80001188 - 45810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 40000000200004621188ffff1ffff805821008 - 45820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 45820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45820 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001000000001fffff44000000 - 45820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001188, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45820 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 45820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 - 45830 : [doFinishMem] DTlbResp { resp: <'h0000000080001188,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001188, check_high: 'h00000000080001190, check_inclusive: True } }, specBits: 'h004 } - 45830 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 45830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 1000000000000000040000001fffff44000000 - 45840 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000400000001fffff44000000 - 45840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 45850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 45850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45860 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 - 45860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 45870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 45870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 45870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 000000000000000c000000001fffff44000000 - 45880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 45880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 45880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000800000001fffff44000000 - 45890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 45890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 45890 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 45890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 45890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 45900 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001200, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 45900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 45900 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 45900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 45900 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 45900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 45900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 45910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 45910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45910 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200004021008ffff1ffff805821008 - 45910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45910 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 45910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 45910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 45910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 000000000000000c400000001fffff44000000 - 45920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 45920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 45920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 45920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 45920 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 45920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 45920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000062000000001fffff44000000 - 45930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 45930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 45930 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001000000001fffff44000000 - 45930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 45930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 45930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 45930 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 45930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 45930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001190 -After delta: vaddr = 0x80001190 - 45930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - 45950 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle - 45960 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle +instret:551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3471 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 46010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3fe, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 46020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 46040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 46050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 46050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 46050 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 46050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h1f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000000000000001fffff44000000 - 46060 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001000000001fffff44000000 - 46060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 46060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 46060 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 46060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 46070 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 46070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 46080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1305 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4608 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h001 } - 46090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1306 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 4609 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h019 } - 46100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46100 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 46100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 46110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 46110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46110 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 46110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46110 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 46110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1307 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4611 -instret:1308 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4611 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 46120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46120 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 46120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46120 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 46120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1309 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 4612 -instret:1310 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 4612 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 46130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 46130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46130 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001000000001fffff44000000 - 46130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46130 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 46130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:1311 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 4613 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46140 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 46140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 46140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000000000000400000001fffff44000000 - 46150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46150 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000000000001fffff44000000 - 46150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 1000000000000000040000001fffff44000000 - 46160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46160 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 46160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h1f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h009 } - 46170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46170 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000000000001fffff44000000 - 46170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 46180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 46180 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 46180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 49 <= 000000000000000c000000001fffff44000000 - 46190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 46190 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 - 46190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1312 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4619 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 46200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 46200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1313 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4620 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h014 } - 46210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46210 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 46210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1314 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4621 -instret:1315 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4621 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 46220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46220 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 46220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46220 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 46220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1316 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4622 -instret:1317 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4622 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 000000000000000c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 46230 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 46230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46230 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 46230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1318 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4623 -instret:1319 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4623 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000060000000001fffff44000000 - 46240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 46240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46240 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001000000001fffff44000000 - 46240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001188 -After delta: vaddr = 0x80001188 - 46240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1320 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4624 -instret:1321 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4624 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 40000000200004621188ffff1ffff805821008 - 46250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 46250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001188, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46250 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 46250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1322 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4625 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 - 46260 : [doFinishMem] DTlbResp { resp: <'h0000000080001188,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001188 o: 'h0000000000000180 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001188, check_high: 'h00000000080001190, check_inclusive: True } }, specBits: 'h000 } - 46260 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 46260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1323 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4626 -instret:1324 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4626 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 - 46270 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000400000001fffff44000000 - 46270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1325 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4627 -instret:1326 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4627 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2fb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001188, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 46280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1327 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4628 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46290 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000400000001fffff44000000 - 46290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 46290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1328 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4629 -instret:1329 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4629 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 46300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1330 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4630 -instret:1331 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4630 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 000000000000000c000000001fffff44000000 - 46310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 46310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000000800000001fffff44000000 - 46320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 46320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46320 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 46320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 46330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 46330 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 46330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46330 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 46330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 46340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46340 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200004021008ffff1ffff805821008 - 46340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 46340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 000000000000000c400000001fffff44000000 - 46350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 46350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46350 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 46350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000062000000001fffff44000000 - 46360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 46360 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46360 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001000000001fffff44000000 - 46360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46360 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 46360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001190 -After delta: vaddr = 0x80001190 - 46360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 40000000200004641190ffff1ffff805821008 - 46370 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46370 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 - 46370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001190, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46370 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 46370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46380 : [doFinishMem] DTlbResp { resp: <'h0000000080001190,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001190 o: 'h0000000000000188 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001190, check_high: 'h00000000080001198, check_inclusive: True } }, specBits: 'h004 } - 46380 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 46380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h2fb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 46390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46390 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000800000001fffff44000000 - 46390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1332 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4639 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 46400 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 - 46400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1333 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4640 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 46410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1334 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4641 -instret:1335 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4641 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 46420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1336 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4642 -instret:1337 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4642 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 4f <= 000000000000000c000000001fffff44000000 - 46430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 46430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46430 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 46430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1338 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4643 -instret:1339 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4643 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 46440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 46440 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 46440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46440 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 46440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1340 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4644 -instret:1341 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4644 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 46450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46450 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200004021008ffff1ffff805821008 - 46450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1342 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4645 -instret:1343 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4645 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 46460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 46460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46460 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 46460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1344 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4646 -instret:1345 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4646 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 000000000000000c800000001fffff44000000 - 46470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 46470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46470 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001000000001fffff44000000 - 46470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46470 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 46470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1346 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4647 -instret:1347 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4647 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000064000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001190, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 46480 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 46480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001198 -After delta: vaddr = 0x80001198 - 46480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1348 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4648 -instret:1349 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4648 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200004661198ffff1ffff805821008 -[RFile] wr_ 1: r 76 <= 0000000000000000400000001fffff44000000 - 46490 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000c00000001fffff44000000 - 46490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001198 o: 'h0000000000000190 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001198 o: 'h0000000000000190 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001198, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 46490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1350 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4649 -instret:1351 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4649 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h2fb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 1000000000000000040000001fffff44000000 - 46500 : [doFinishMem] DTlbResp { resp: <'h0000000080001198,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001198 o: 'h0000000000000190 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001198, check_high: 'h000000000800011a0, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 46500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 46510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 46510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 46520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46520 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000c00000001fffff44000000 - 46520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 000000000000000c000000001fffff44000000 - 46530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 46530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46530 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 46530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 46540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46540 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 - 46540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46540 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 46540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 46550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46550 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 46550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46550 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 46550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 46560 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200004021008ffff1ffff805821008 - 46560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46560 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 46560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1352 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4656 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 000000000000000cc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 46570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 46570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46570 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001000000001fffff44000000 - 46570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1353 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4657 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000066000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 46580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46580 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 46580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011a0 -After delta: vaddr = 0x800011a0 - 46580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1354 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4658 -instret:1355 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4658 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000046811a0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46590 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 46590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800011a0 o: 'h0000000000000198 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011a0 o: 'h0000000000000198 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1356 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4659 -instret:1357 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4659 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46600 : [doFinishMem] DTlbResp { resp: <'h00000000800011a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011a0 o: 'h0000000000000198 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011a0, check_high: 'h000000000800011a8, check_inclusive: True } }, specBits: 'h010 } - 46600 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000001000000001fffff44000000 - 46600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1358 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4660 -instret:1359 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4660 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 1000000000000000040000001fffff44000000 - 46610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 46610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1360 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4661 -instret:1361 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4661 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46620 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001000000001fffff44000000 - 46620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h017 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1362 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4662 -instret:1363 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4662 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 46630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1364 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4663 -instret:1365 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4663 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 72 <= 000000000000000c000000001fffff44000000 - 46640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 46640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1366 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4664 -instret:1367 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4664 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000001400000001fffff44000000 - 46650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001198, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 46650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46650 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 46650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1368 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4665 -instret:1369 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4665 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 46660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 46660 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 46660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46660 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 46660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1370 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4666 -instret:1371 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4666 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 46670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 46670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46670 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200004021008ffff1ffff805821008 - 46670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 46670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 000000000000000d000000001fffff44000000 - 46680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 46680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46680 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 46680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000068000000001fffff44000000 - 46690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 46690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46690 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001000000001fffff44000000 - 46690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46690 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 46690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011a8 -After delta: vaddr = 0x800011a8 - 46690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 6b <= 400000002000046a11a8ffff1ffff805821008 - 46700 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003000000001fffff44000000 - 46700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800011a8 o: 'h00000000000001a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011a8 o: 'h00000000000001a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 46700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 1000000000000000040000001fffff44000000 - 46710 : [doFinishMem] DTlbResp { resp: <'h00000000800011a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011a8 o: 'h00000000000001a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011a8, check_high: 'h000000000800011b0, check_inclusive: True } }, specBits: 'h014 } - 46710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46710 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000001400000001fffff44000000 - 46710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 46720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46720 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 46720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46730 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000c00000001fffff44000000 - 46730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 46740 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001400000001fffff44000000 - 46740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 69 <= 000000000000000c000000001fffff44000000 - 46750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 46750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1372 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4675 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 46760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46760 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 46760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1373 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4676 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46770 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 46770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1374 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4677 -instret:1375 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4677 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 46780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1376 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4678 -instret:1377 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4678 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 000000000000000d400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1378 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4679 -instret:1379 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4679 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 000000000000006a000000001fffff44000000 - 46800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 46800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b0 -After delta: vaddr = 0x800011b0 - 46800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1380 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4680 -instret:1381 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4680 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 400000002000046c11b0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 46810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800011b0 o: 'h00000000000001a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b0 o: 'h00000000000001a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46810 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 46810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1382 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4681 -instret:1383 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4681 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46820 : [doFinishMem] DTlbResp { resp: <'h00000000800011b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b0 o: 'h00000000000001a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011b0, check_high: 'h000000000800011b8, check_inclusive: True } }, specBits: 'h00c } - 46820 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 77 <= 40000000200004021008ffff1ffff805821008 - 46820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 46820 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 46820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1384 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4682 -instret:1385 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4682 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 46830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 46830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46830 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001000000001fffff44000000 - 46830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1386 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4683 -instret:1387 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4683 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 46840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 46840 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 46840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1388 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4684 -instret:1389 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4684 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000000400000001fffff44000000 - 46850 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 46850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 46850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1390 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4685 -instret:1391 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4685 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 46860 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000001800000001fffff44000000 - 46860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 46870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 46870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 46870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 46870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46880 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46880 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001800000001fffff44000000 - 46880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 46890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 46890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 46890 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 46890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 41 <= 000000000000000c000000001fffff44000000 - 46900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 46900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46900 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001000000001fffff44000000 - 46900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 46910 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 46910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 46920 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 -instret:1392 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4692 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1393 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4693 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 000000000000000d800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1394 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4694 -instret:1395 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4694 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 000000000000006c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011b8 -After delta: vaddr = 0x800011b8 - 46950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1396 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4695 -instret:1397 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4695 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000046e11b8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800011b8 o: 'h00000000000001b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011b8 o: 'h00000000000001b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 46960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1398 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4696 -instret:1399 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4696 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46970 : [doFinishMem] DTlbResp { resp: <'h00000000800011b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011b8 o: 'h00000000000001b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011b8, check_high: 'h000000000800011c0, check_inclusive: True } }, specBits: 'h028 } - 46970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 46970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 46970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1400 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4697 -instret:1401 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4697 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 46980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 46980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 46980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 46980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1402 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4698 -instret:1403 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4698 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 46990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 46990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 46990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 46990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 46990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 46990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 46990 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 46990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 46990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 46990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1404 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4699 -instret:1405 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4699 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 47000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47000 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 74 <= 40000000200004021008ffff1ffff805821008 - 47000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47000 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 47000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1406 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4700 -instret:1407 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4700 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47010 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001000000001fffff44000000 - 47010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47010 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 47010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800011a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1408 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4701 -instret:1409 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4701 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000000400000001fffff44000000 - 47020 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 47020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800011a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800011a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1410 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4702 -instret:1411 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4702 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47030 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001c00000001fffff44000000 - 47030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h37d, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47050 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001c00000001fffff44000000 - 47050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 47060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47060 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 47060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7e <= 000000000000000c000000001fffff44000000 - 47070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 47070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47070 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 47070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47080 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 47080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47090 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 -instret:1412 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4709 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1413 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4710 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 000000000000000dc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1414 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4711 -instret:1415 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4711 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 000000000000006e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011c0 -After delta: vaddr = 0x800011c0 - 47120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1416 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4712 -instret:1417 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4712 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 400000002000047011c0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800011c0 o: 'h00000000000001b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c0 o: 'h00000000000001b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1418 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4713 -instret:1419 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4713 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47140 : [doFinishMem] DTlbResp { resp: <'h00000000800011c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c0 o: 'h00000000000001b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011c0, check_high: 'h000000000800011c8, check_inclusive: True } }, specBits: 'h030 } - 47140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1420 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4714 -instret:1421 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4714 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 47150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1422 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4715 -instret:1423 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4715 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 47160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47160 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 47160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1424 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4716 -instret:1425 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4716 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 47170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47170 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 47170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 47170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1426 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4717 -instret:1427 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4717 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001000000001fffff44000000 - 47180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47180 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 47180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1428 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4718 -instret:1429 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4718 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000000400000001fffff44000000 - 47190 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 47190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800011b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1430 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4719 -instret:1431 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4719 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47200 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 47200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47220 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 47220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 47230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47230 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 47230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 78 <= 000000000000000c000000001fffff44000000 - 47240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 47240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47240 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001800000001fffff44000000 - 47240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47250 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 47250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47260 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 -instret:1432 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4726 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1433 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4727 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 000000000000000e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1434 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4728 -instret:1435 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4728 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000070000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011c8 -After delta: vaddr = 0x800011c8 - 47290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1436 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4729 -instret:1437 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4729 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 400000002000047211c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800011c8 o: 'h00000000000001c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011c8 o: 'h00000000000001c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1438 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4730 -instret:1439 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4730 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47310 : [doFinishMem] DTlbResp { resp: <'h00000000800011c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011c8 o: 'h00000000000001c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011c8, check_high: 'h000000000800011d0, check_inclusive: True } }, specBits: 'h014 } - 47310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1440 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4731 -instret:1441 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4731 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 47320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1442 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4732 -instret:1443 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4732 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 47330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47330 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 47330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1444 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4733 -instret:1445 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4733 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 47340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47340 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 47340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47340 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 47340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1446 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4734 -instret:1447 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4734 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47350 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001000000001fffff44000000 - 47350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47350 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 47350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1448 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4735 -instret:1449 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4735 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 47360 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 47360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1450 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4736 -instret:1451 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4736 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47370 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002400000001fffff44000000 - 47370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 47380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47390 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47390 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002400000001fffff44000000 - 47390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 47400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 47400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47400 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 47400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 44 <= 000000000000000c000000001fffff44000000 - 47410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 47410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47410 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000001c00000001fffff44000000 - 47410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47420 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 47420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 47430 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 -instret:1452 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4743 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1453 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4744 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 000000000000000e400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1454 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4745 -instret:1455 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4745 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000072000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011d0 -After delta: vaddr = 0x800011d0 - 47460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1456 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4746 -instret:1457 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4746 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 400000002000047411d0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800011d0 o: 'h00000000000001c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011d0 o: 'h00000000000001c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1458 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4747 -instret:1459 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4747 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47480 : [doFinishMem] DTlbResp { resp: <'h00000000800011d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011d0 o: 'h00000000000001c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011d0, check_high: 'h000000000800011d8, check_inclusive: True } }, specBits: 'h00c } - 47480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1460 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4748 -instret:1461 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4748 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 47490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1462 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4749 -instret:1463 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4749 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 47500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47500 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 47500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1464 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4750 -instret:1465 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4750 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 47510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47510 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 76 <= 40000000200004021008ffff1ffff805821008 - 47510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47510 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 47510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1466 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4751 -instret:1467 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4751 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47520 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001000000001fffff44000000 - 47520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47520 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 47520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1468 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4752 -instret:1469 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4752 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000000400000001fffff44000000 - 47530 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1470 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4753 -instret:1471 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4753 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47540 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002800000001fffff44000000 - 47540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 47550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47560 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002800000001fffff44000000 - 47560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 47560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 47560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 47570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 47570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47570 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 47570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001240, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 66 <= 000000000000000c000000001fffff44000000 - 47580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 47580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47580 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002000000001fffff44000000 - 47580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47590 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 47590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 47600 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 -instret:1472 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4760 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1473 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4761 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 000000000000000e800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1474 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4762 -instret:1475 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4762 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000074000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011d8 -After delta: vaddr = 0x800011d8 - 47630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1476 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4763 -instret:1477 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4763 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000047611d8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800011d8 o: 'h00000000000001d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011d8 o: 'h00000000000001d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1478 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4764 -instret:1479 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4764 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47650 : [doFinishMem] DTlbResp { resp: <'h00000000800011d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011d8 o: 'h00000000000001d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011d8, check_high: 'h000000000800011e0, check_inclusive: True } }, specBits: 'h028 } - 47650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1480 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4765 -instret:1481 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4765 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 47660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1482 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4766 -instret:1483 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4766 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 47670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47670 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 47670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1484 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4767 -instret:1485 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4767 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 47680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47680 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200004021008ffff1ffff805821008 - 47680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47680 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 47680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1486 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4768 -instret:1487 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4768 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47690 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001000000001fffff44000000 - 47690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47690 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 47690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1488 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4769 -instret:1489 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4769 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000000400000001fffff44000000 - 47700 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003000000001fffff44000000 - 47700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1490 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4770 -instret:1491 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4770 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47710 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002c00000001fffff44000000 - 47710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3be, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47730 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002c00000001fffff44000000 - 47730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 47740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47740 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 47740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 02 <= 000000000000000c000000001fffff44000000 - 47750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 47750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47750 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002400000001fffff44000000 - 47750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47760 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 47760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 47770 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 -instret:1492 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4777 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1493 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4778 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 000000000000000ec00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1494 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4779 -instret:1495 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4779 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000076000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011e0 -After delta: vaddr = 0x800011e0 - 47800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1496 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4780 -instret:1497 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4780 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 400000002000047811e0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800011e0 o: 'h00000000000001d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e0 o: 'h00000000000001d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1498 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4781 -instret:1499 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4781 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47820 : [doFinishMem] DTlbResp { resp: <'h00000000800011e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e0 o: 'h00000000000001d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011e0, check_high: 'h000000000800011e8, check_inclusive: True } }, specBits: 'h030 } - 47820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1500 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4782 -instret:1501 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4782 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 47830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1502 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4783 -instret:1503 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4783 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 47840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 47840 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 47840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1504 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4784 -instret:1505 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4784 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 47850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 47850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47850 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 47850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 47850 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 47850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1506 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4785 -instret:1507 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4785 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 47860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47860 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001000000001fffff44000000 - 47860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 47860 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 47860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1508 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4786 -instret:1509 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4786 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 - 47870 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 47870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 47870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1510 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4787 -instret:1511 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4787 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 47880 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 47880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 47880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 47890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 47890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 47890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47900 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 47900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 47900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3480 calling cycle - 47910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 47910 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 47910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 47910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000000c000000001fffff44000000 - 47920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 47920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 47920 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002800000001fffff44000000 - 47920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 47920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 47930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 47930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 47930 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 47930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 47940 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 -instret:1512 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4794 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1513 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4795 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 000000000000000f000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1514 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4796 -instret:1515 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4796 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000078000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011e8 -After delta: vaddr = 0x800011e8 - 47970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1516 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4797 -instret:1517 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4797 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 400000002000047a11e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 47980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 47980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 47980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1518 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4798 -instret:1519 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4798 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 47990 : [doFinishMem] DTlbResp { resp: <'h00000000800011e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011e8, check_high: 'h000000000800011f0, check_inclusive: True } }, specBits: 'h014 } - 47990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 47990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 47990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1520 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4799 -instret:1521 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4799 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 48000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1522 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4800 -instret:1523 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4800 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 48010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48010 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 48010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1524 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4801 -instret:1525 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4801 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 48020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48020 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 40000000200004021008ffff1ffff805821008 - 48020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48020 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 48020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1526 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4802 -instret:1527 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4802 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 48030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48030 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001000000001fffff44000000 - 48030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48030 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 48030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1528 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4803 -instret:1529 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4803 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 48040 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1530 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4804 -instret:1531 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4804 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 48050 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003400000001fffff44000000 - 48050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001240, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 48060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 48060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48070 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003400000001fffff44000000 - 48070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 48080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 48080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 48080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 48080 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 48080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 51 <= 000000000000000c000000001fffff44000000 - 48090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 48090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48090 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002c00000001fffff44000000 - 48090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48100 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 48100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 48110 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 -instret:1532 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4811 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1533 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4812 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 000000000000000f400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1534 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4813 -instret:1535 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4813 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 000000000000007a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011f0 -After delta: vaddr = 0x800011f0 - 48140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1536 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4814 -instret:1537 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4814 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000047c11f0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 48150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1538 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4815 -instret:1539 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4815 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48160 : [doFinishMem] DTlbResp { resp: <'h00000000800011f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011f0, check_high: 'h000000000800011f8, check_inclusive: True } }, specBits: 'h00c } - 48160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 48160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1540 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4816 -instret:1541 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4816 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 48170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1542 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4817 -instret:1543 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4817 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 48180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48180 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 48180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1544 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4818 -instret:1545 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4818 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 48190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48190 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 05 <= 40000000200004021008ffff1ffff805821008 - 48190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48190 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 48190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1546 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4819 -instret:1547 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4819 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 48200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48200 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001000000001fffff44000000 - 48200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48200 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 48200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1548 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4820 -instret:1549 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4820 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000000400000001fffff44000000 - 48210 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 48210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 48210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800011e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1550 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4821 -instret:1551 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4821 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 48220 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003800000001fffff44000000 - 48220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 48230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 48230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48240 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48240 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003800000001fffff44000000 - 48240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 48250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 48250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 48250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 48250 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 48250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7b <= 000000000000000c000000001fffff44000000 - 48260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 48260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48260 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 48260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48270 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 48270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 48280 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 -instret:1552 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4828 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h2; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:1553 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4829 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:1554 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4831 calling cycle calling cycle +instret:553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3489 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 48390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 48410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:1555 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 4841 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 48420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 48420 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 48420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:1556 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4842 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 48430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48430 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001000000001fffff44000000 - 48430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 48440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 48440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 48440 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 48440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000000000000001fffff44000000 - 48450 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001000000001fffff44000000 - 48450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 48450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 48450 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 48450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1557 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4845 -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000001400000001fffff44000000 - 48460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 48460 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 48460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 48470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:1558 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 4847 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 48480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1559 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 4848 -instret:1560 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 4848 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 48490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 48490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 48490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 48500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48500 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 48500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 48510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48510 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 48510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 48510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 48520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48520 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 48520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 48530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 48530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48530 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 48530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48530 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 48530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 48540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48540 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001400000001fffff44000000 - 48540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48540 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 48540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48550 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 48550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000000400000001fffff44000000 - 48560 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 48560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 - 48570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3498 calling cycle - 48580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 48580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48590 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 - 48590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 56 <= 000000000000000f000000001fffff44000000 - 48600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 48600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 48600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 48610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 48610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000400000001fffff44000000 - 48620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 48620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 48620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 48630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 48630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 48630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48630 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 48630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 000000000000000f000000001fffff44000000 - 48640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 48640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48640 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 48640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000078000000001fffff44000000 - 48650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 48650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48650 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 48650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011e8 -After delta: vaddr = 0x800011e8 - 48650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 400000002000047a11e8ffff1ffff805821008 - 48660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 48660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48660 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001400000001fffff44000000 - 48660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48660 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 48660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000400000001fffff44000000 - 48670 : [doFinishMem] DTlbResp { resp: <'h00000000800011e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011e8, check_high: 'h000000000800011f0, check_inclusive: True } }, specBits: 'h004 } - 48670 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 48670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 1000000000000000040000001fffff44000000 - 48680 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000400000001fffff44000000 - 48680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 48690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48700 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 - 48700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 48710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 48710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0b <= 000000000000000f000000001fffff44000000 - 48720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 48720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 48720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000000800000001fffff44000000 - 48730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 48730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48730 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 48730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 48740 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 48740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48740 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 48740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 48750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 48750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48750 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 78 <= 40000000200004021008ffff1ffff805821008 - 48750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 000000000000000f400000001fffff44000000 - 48760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 48760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48760 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 48760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 000000000000007a000000001fffff44000000 - 48770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 48770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48770 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001400000001fffff44000000 - 48770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48770 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 48770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011f0 -After delta: vaddr = 0x800011f0 - 48770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - 48790 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle - 48800 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3507 calling cycle - 48850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 48860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 48880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 48890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 48890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 48890 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 48890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h1df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000000000000001fffff44000000 - 48900 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001400000001fffff44000000 - 48900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 48900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 48900 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 48900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 48910 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 48910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 48920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 48920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 48920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1561 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 4892 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h001 } - 48930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 48930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 48930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1562 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 4893 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h019 } - 48940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 48940 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 48940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 48940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 48940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 48950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 48950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 48950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 48950 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 48950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1563 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4895 -instret:1564 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4895 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 48960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48960 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 48960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 48960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 48960 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 48960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1565 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 4896 -instret:1566 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 4896 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 48970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 48970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 48970 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001400000001fffff44000000 - 48970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 48970 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 48970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:1567 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 4897 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 48980 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 48980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 48980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 48980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 48980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 48980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 48980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000000400000001fffff44000000 - 48990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 48990 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 48990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 48990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 1000000000000000040000001fffff44000000 - 49000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49000 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 49000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h1df, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h009 } - 49010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49010 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000 - 49010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 49020 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 56 <= 000000000000000f000000001fffff44000000 - 49030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 49030 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 - 49030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1568 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4903 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 49040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 49040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1569 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4904 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h014 } - 49050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49050 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1570 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4905 -instret:1571 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4905 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 49060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49060 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 49060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49060 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1572 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4906 -instret:1573 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4906 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 000000000000000f000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 49070 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 49070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49070 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1574 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4907 -instret:1575 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4907 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000078000000001fffff44000000 - 49080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 49080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49080 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001400000001fffff44000000 - 49080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011e8 -After delta: vaddr = 0x800011e8 - 49080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1576 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4908 -instret:1577 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4908 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 400000002000047a11e8ffff1ffff805821008 - 49090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 49090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49090 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 49090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1578 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4909 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000400000001fffff44000000 - 49100 : [doFinishMem] DTlbResp { resp: <'h00000000800011e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011e8 o: 'h00000000000001e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011e8, check_high: 'h000000000800011f0, check_inclusive: True } }, specBits: 'h000 } - 49100 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 49100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1579 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 4910 -instret:1580 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 4910 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 1000000000000000040000001fffff44000000 - 49110 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000400000001fffff44000000 - 49110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1581 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 4911 -instret:1582 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 4911 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 49120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1583 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 4912 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49130 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 - 49130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 49130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800011e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1584 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4913 -instret:1585 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4913 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 49140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1586 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4914 -instret:1587 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4914 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0b <= 000000000000000f000000001fffff44000000 - 49150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 49150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000000800000001fffff44000000 - 49160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 49160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49160 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 49170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 49170 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 49170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49170 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 49180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49180 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 78 <= 40000000200004021008ffff1ffff805821008 - 49180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 000000000000000f400000001fffff44000000 - 49190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 49190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49190 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 000000000000007a000000001fffff44000000 - 49200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 49200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49200 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001400000001fffff44000000 - 49200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49200 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 49200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011f0 -After delta: vaddr = 0x800011f0 - 49200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 400000002000047c11f0ffff1ffff805821008 - 49210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49210 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000400000001fffff44000000 - 49210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49210 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 49210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49220 : [doFinishMem] DTlbResp { resp: <'h00000000800011f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011f0 o: 'h00000000000001e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011f0, check_high: 'h000000000800011f8, check_inclusive: True } }, specBits: 'h004 } - 49220 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 49220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h2ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 49230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49230 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000000800000001fffff44000000 - 49230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1588 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4923 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 49240 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 - 49240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1589 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4924 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 49250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1590 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4925 -instret:1591 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4925 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 49260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1592 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4926 -instret:1593 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4926 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 01 <= 000000000000000f000000001fffff44000000 - 49270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 49270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49270 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 49270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1594 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4927 -instret:1595 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4927 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 49280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 49280 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 49280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49280 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1596 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4928 -instret:1597 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4928 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 49290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49290 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004021008ffff1ffff805821008 - 49290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1598 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4929 -instret:1599 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4929 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 49300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 49300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49300 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1600 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4930 -instret:1601 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4930 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 000000000000000f800000001fffff44000000 - 49310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 49310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49310 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49310 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1602 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4931 -instret:1603 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4931 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000000000007c000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 49320 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 49320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800011f8 -After delta: vaddr = 0x800011f8 - 49320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1604 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4932 -instret:1605 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4932 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 400000002000047e11f8ffff1ffff805821008 -[RFile] wr_ 1: r 6a <= 0000000000000000400000001fffff44000000 - 49330 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 - 49330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800011f8 o: 'h00000000000001f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800011f8 o: 'h00000000000001f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800011f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800011f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1606 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4933 -instret:1607 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4933 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h2ef, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 1000000000000000040000001fffff44000000 - 49340 : [doFinishMem] DTlbResp { resp: <'h00000000800011f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800011f8 o: 'h00000000000001f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800011f8, check_high: 'h00000000080001200, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 49340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 49350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 49360 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49360 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000c00000001fffff44000000 - 49360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 67 <= 000000000000000f000000001fffff44000000 - 49370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 49370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49370 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 49380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49380 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000800000001fffff44000000 - 49380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 49390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 49390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49390 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 49400 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 66 <= 40000000200004021008ffff1ffff805821008 - 49400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49400 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1608 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4940 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 000000000000000fc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 49410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 49410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49410 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001400000001fffff44000000 - 49410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1609 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 000000000000007e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 49420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49420 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001200 -After delta: vaddr = 0x80001200 - 49420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1610 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4942 -instret:1611 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4942 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200004801200ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49430 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 49430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001200 o: 'h00000000000001f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001200 o: 'h00000000000001f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001200, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1612 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4943 -instret:1613 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4943 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49440 : [doFinishMem] DTlbResp { resp: <'h0000000080001200,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001200 o: 'h00000000000001f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001200, check_high: 'h00000000080001208, check_inclusive: True } }, specBits: 'h010 } - 49440 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000001000000001fffff44000000 - 49440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1614 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4944 -instret:1615 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4944 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 - 49450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 49450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1616 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4945 -instret:1617 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4945 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49460 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000001000000001fffff44000000 - 49460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h017 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1618 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4946 -instret:1619 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4946 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 49470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1620 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4947 -instret:1621 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4947 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7f <= 000000000000000f000000001fffff44000000 - 49480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 49480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1622 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4948 -instret:1623 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4948 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000001400000001fffff44000000 - 49490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800011f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 49490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49490 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 49490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1624 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4949 -instret:1625 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4949 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 49500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 49500 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003000000001fffff44000000 - 49500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49500 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 49500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800011f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1626 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4950 -instret:1627 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4950 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 49510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 49510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49510 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 02 <= 40000000200004021008ffff1ffff805821008 - 49510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800011f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 49510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800011f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000010000000001fffff44000000 - 49520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 49520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49520 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 49520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000080000000001fffff44000000 - 49530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 49530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49530 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001400000001fffff44000000 - 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49530 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001208 -After delta: vaddr = 0x80001208 - 49530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 74 <= 40000000200004821208ffff1ffff805821008 - 49540 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 49540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001208 o: 'h0000000000000200 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001208 o: 'h0000000000000200 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001208, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 49540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 1000000000000000040000001fffff44000000 - 49550 : [doFinishMem] DTlbResp { resp: <'h0000000080001208,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001208 o: 'h0000000000000200 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001208, check_high: 'h00000000080001210, check_inclusive: True } }, specBits: 'h014 } - 49550 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49550 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001400000001fffff44000000 - 49550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 49560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49560 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 49560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49570 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000c00000001fffff44000000 - 49570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 49580 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001400000001fffff44000000 - 49580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 0c <= 000000000000000f000000001fffff44000000 - 49590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 49590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1628 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4959 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 49600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49600 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 49600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1629 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4960 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49610 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 49610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1630 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4961 -instret:1631 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4961 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 49620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1632 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4962 -instret:1633 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4962 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000010400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1634 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4963 -instret:1635 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4963 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000082000000001fffff44000000 - 49640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 49640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001210 -After delta: vaddr = 0x80001210 - 49640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1636 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4964 -instret:1637 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4964 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 40000000200004841210ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 49650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001210 o: 'h0000000000000208 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001210 o: 'h0000000000000208 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001210, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49650 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1638 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4965 -instret:1639 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4965 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49660 : [doFinishMem] DTlbResp { resp: <'h0000000080001210,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001210 o: 'h0000000000000208 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001210, check_high: 'h00000000080001218, check_inclusive: True } }, specBits: 'h00c } - 49660 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 47 <= 40000000200004021008ffff1ffff805821008 - 49660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49660 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 49660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1640 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4966 -instret:1641 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4966 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 49670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 49670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49670 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000001400000001fffff44000000 - 49670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1642 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4967 -instret:1643 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4967 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001200, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 49680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49680 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 49680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1644 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4968 -instret:1645 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4968 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 - 49690 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1646 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4969 -instret:1647 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4969 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 49700 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000001800000001fffff44000000 - 49700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 49710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 49710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49720 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001800000001fffff44000000 - 49720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 49720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 49720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 49730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 49730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49730 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49740 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001280, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 52 <= 000000000000000f000000001fffff44000000 - 49740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 49740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49740 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001000000001fffff44000000 - 49740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49750 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 49760 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 -instret:1648 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4976 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1649 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4977 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000010800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1650 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4978 -instret:1651 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4978 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000084000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001218 -After delta: vaddr = 0x80001218 - 49790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1652 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4979 -instret:1653 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4979 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200004861218ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001218 o: 'h0000000000000210 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001218 o: 'h0000000000000210 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001218, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1654 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4980 -instret:1655 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4980 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49810 : [doFinishMem] DTlbResp { resp: <'h0000000080001218,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001218 o: 'h0000000000000210 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001218, check_high: 'h00000000080001220, check_inclusive: True } }, specBits: 'h028 } - 49810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1656 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4981 -instret:1657 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4981 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 49820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1658 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4982 -instret:1659 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4982 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 49830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 49830 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 49830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1660 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 4983 -instret:1661 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 4983 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 49840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 49840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49840 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200004021008ffff1ffff805821008 - 49840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 49840 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 49840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1662 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 4984 -instret:1663 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 4984 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001208, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 49850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49850 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001400000001fffff44000000 - 49850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 49850 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 49850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1664 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4985 -instret:1665 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 4985 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000400000001fffff44000000 - 49860 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 49860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 49860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1666 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 4986 -instret:1667 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 4986 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 49870 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001c00000001fffff44000000 - 49870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 49880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 49880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 49880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 49880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49890 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49890 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 49890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 49900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 49900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 49900 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 49900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 49900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 68 <= 000000000000000f000000001fffff44000000 - 49910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 49910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49910 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001400000001fffff44000000 - 49910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 49910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 49920 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 49930 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 -instret:1668 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 4993 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1669 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 4994 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000010c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1670 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 4995 -instret:1671 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 4995 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000086000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001220 -After delta: vaddr = 0x80001220 - 49960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1672 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 4996 -instret:1673 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 4996 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 40000000200004881220ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001220 o: 'h0000000000000218 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001220 o: 'h0000000000000218 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001220, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 49970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1674 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 4997 -instret:1675 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 4997 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 49980 : [doFinishMem] DTlbResp { resp: <'h0000000080001220,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001220 o: 'h0000000000000218 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001220, check_high: 'h00000000080001228, check_inclusive: True } }, specBits: 'h030 } - 49980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 49980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 49980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1676 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 4998 -instret:1677 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 4998 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 49990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 49990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 49990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 49990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 49990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 49990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1678 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 4999 -instret:1679 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 4999 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 50000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50000 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1680 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5000 -instret:1681 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 50010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50010 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 50010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50010 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1682 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5001 -instret:1683 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5001 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001210, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50020 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001400000001fffff44000000 - 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50020 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1684 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5002 -instret:1685 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5002 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000000400000001fffff44000000 - 50030 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 50030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1686 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5003 -instret:1687 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5003 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50040 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 50040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50060 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000002000000001fffff44000000 - 50060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 50070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50070 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 50070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7d <= 000000000000000f000000001fffff44000000 - 50080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 50080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50080 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000001800000001fffff44000000 - 50080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50090 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 50090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50100 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 -instret:1688 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5010 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1689 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5011 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000011000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1690 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5012 -instret:1691 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5012 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000088000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001228 -After delta: vaddr = 0x80001228 - 50130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1692 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5013 -instret:1693 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5013 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 400000002000048a1228ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001228 o: 'h0000000000000220 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001228 o: 'h0000000000000220 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001228, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1694 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5014 -instret:1695 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5014 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50150 : [doFinishMem] DTlbResp { resp: <'h0000000080001228,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001228 o: 'h0000000000000220 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001228, check_high: 'h00000000080001230, check_inclusive: True } }, specBits: 'h014 } - 50150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 50150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 50150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1696 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5015 -instret:1697 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5015 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 50160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1698 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5016 -instret:1699 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5016 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 50170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50170 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 50170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1700 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5017 -instret:1701 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5017 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 50180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50180 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 50180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50180 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 50180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1702 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5018 -instret:1703 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5018 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001218, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50190 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001400000001fffff44000000 - 50190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50190 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 50190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1704 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5019 -instret:1705 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5019 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000000400000001fffff44000000 - 50200 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1706 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5020 -instret:1707 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5020 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50210 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002400000001fffff44000000 - 50210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50220 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001280, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 50220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50230 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002400000001fffff44000000 - 50230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50230 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 50230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 50230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 50240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50240 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 50 <= 000000000000000f000000001fffff44000000 - 50250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 50250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50250 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000001c00000001fffff44000000 - 50250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50260 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50270 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003000000001fffff44000000 -instret:1708 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5027 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1709 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5028 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000011400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1710 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5029 -instret:1711 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5029 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 000000000000008a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001230 -After delta: vaddr = 0x80001230 - 50300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1712 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5030 -instret:1713 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5030 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 400000002000048c1230ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001230 o: 'h0000000000000228 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001230 o: 'h0000000000000228 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001230, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1714 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5031 -instret:1715 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5031 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50320 : [doFinishMem] DTlbResp { resp: <'h0000000080001230,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001230 o: 'h0000000000000228 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001230, check_high: 'h00000000080001238, check_inclusive: True } }, specBits: 'h00c } - 50320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 50320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 50320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1716 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5032 -instret:1717 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5032 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 50330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1718 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5033 -instret:1719 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5033 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 50340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50340 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1720 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5034 -instret:1721 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5034 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 50350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50350 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6a <= 40000000200004021008ffff1ffff805821008 - 50350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50350 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1722 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5035 -instret:1723 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5035 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001220, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50360 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50360 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1724 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5036 -instret:1725 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5036 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000000400000001fffff44000000 - 50370 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1726 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5037 -instret:1727 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5037 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50380 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000002800000001fffff44000000 - 50380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 50390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50400 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50400 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002800000001fffff44000000 - 50400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 50410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 50410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50410 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4e <= 000000000000000f000000001fffff44000000 - 50420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 50420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50420 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002000000001fffff44000000 - 50420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50430 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 50440 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003000000001fffff44000000 -instret:1728 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5044 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1729 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5045 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000011800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1730 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5046 -instret:1731 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5046 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 000000000000008c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001238 -After delta: vaddr = 0x80001238 - 50470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1732 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5047 -instret:1733 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5047 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 400000002000048e1238ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001238 o: 'h0000000000000230 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001238 o: 'h0000000000000230 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001238, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1734 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5048 -instret:1735 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5048 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50490 : [doFinishMem] DTlbResp { resp: <'h0000000080001238,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001238 o: 'h0000000000000230 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001238, check_high: 'h00000000080001240, check_inclusive: True } }, specBits: 'h028 } - 50490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 50490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 50490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1736 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5049 -instret:1737 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5049 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 50500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1738 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5050 -instret:1739 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5050 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 50510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50510 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1740 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5051 -instret:1741 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5051 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 50520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50520 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004021008ffff1ffff805821008 - 50520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50520 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 50520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1742 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5052 -instret:1743 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5052 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001228, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50530 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001400000001fffff44000000 - 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50530 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1744 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5053 -instret:1745 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5053 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 - 50540 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 50540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1746 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5054 -instret:1747 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5054 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50550 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002c00000001fffff44000000 - 50550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 50560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50570 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002c00000001fffff44000000 - 50570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 50580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 50580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50580 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 50580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 000000000000000f000000001fffff44000000 - 50590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 50590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50590 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002400000001fffff44000000 - 50590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50600 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 50610 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 -instret:1748 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5061 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1749 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5062 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000011c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1750 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5063 -instret:1751 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5063 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 000000000000008e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001240 -After delta: vaddr = 0x80001240 - 50640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1752 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5064 -instret:1753 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5064 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 40000000200004901240ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001240 o: 'h0000000000000238 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001240 o: 'h0000000000000238 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001240, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1754 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5065 -instret:1755 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50660 : [doFinishMem] DTlbResp { resp: <'h0000000080001240,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001240 o: 'h0000000000000238 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001240, check_high: 'h00000000080001248, check_inclusive: True } }, specBits: 'h030 } - 50660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 50660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 50660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1756 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5066 -instret:1757 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5066 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 50670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1758 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5067 -instret:1759 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5067 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 50680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50680 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1760 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5068 -instret:1761 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5068 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 50690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50690 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 50690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50690 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1762 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5069 -instret:1763 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5069 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001230, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50700 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001400000001fffff44000000 - 50700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50700 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 50700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1764 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5070 -instret:1765 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5070 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 50710 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 - 50710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1766 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5071 -instret:1767 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5071 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50720 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 50720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50740 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50740 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 50740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 50750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50750 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 50750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000000f000000001fffff44000000 - 50760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 50760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50760 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002800000001fffff44000000 - 50760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50770 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 50770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 50780 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 -instret:1768 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5078 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1769 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5079 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000012000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1770 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5080 -instret:1771 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5080 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000090000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001248 -After delta: vaddr = 0x80001248 - 50810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1772 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5081 -instret:1773 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5081 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 40000000200004921248ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001248, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1774 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5082 -instret:1775 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5082 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50830 : [doFinishMem] DTlbResp { resp: <'h0000000080001248,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001248, check_high: 'h00000000080001250, check_inclusive: True } }, specBits: 'h014 } - 50830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 50830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 50830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1776 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5083 -instret:1777 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5083 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 50840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1778 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5084 -instret:1779 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5084 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 50850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 50850 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1780 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5085 -instret:1781 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5085 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 50860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 50860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50860 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 50860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 50860 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1782 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5086 -instret:1783 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5086 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001238, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 50870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50870 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000001400000001fffff44000000 - 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 50870 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1784 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5087 -instret:1785 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5087 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000400000001fffff44000000 - 50880 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 - 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1786 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5088 -instret:1787 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5088 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 50890 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003400000001fffff44000000 - 50890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 50890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 50910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50910 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003400000001fffff44000000 - 50910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 50910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3516 calling cycle - 50920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 50920 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 50920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 50920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4b <= 000000000000000f000000001fffff44000000 - 50930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 50930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 50930 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002c00000001fffff44000000 - 50930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 50930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 50940 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 50950 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 -instret:1788 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5095 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1789 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5096 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 0000000000000012400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1790 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5097 -instret:1791 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5097 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000092000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001250 -After delta: vaddr = 0x80001250 - 50980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1792 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5098 -instret:1793 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5098 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200004941250ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 50990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001250, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 50990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 50990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1794 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5099 -instret:1795 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5099 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51000 : [doFinishMem] DTlbResp { resp: <'h0000000080001250,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001250, check_high: 'h00000000080001258, check_inclusive: True } }, specBits: 'h00c } - 51000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1796 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5100 -instret:1797 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5100 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 51010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1798 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5101 -instret:1799 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5101 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 51020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51020 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 51020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1800 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5102 -instret:1801 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5102 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 51030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 51030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51030 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 62 <= 40000000200004021008ffff1ffff805821008 - 51030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51030 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1802 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5103 -instret:1803 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5103 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001240, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 51040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51040 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001400000001fffff44000000 - 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51040 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1804 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5104 -instret:1805 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5104 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000000400000001fffff44000000 - 51050 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1806 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5105 -instret:1807 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5105 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 51060 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003800000001fffff44000000 - 51060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 51070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800012c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51080 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51080 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003800000001fffff44000000 - 51080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800012c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 51080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 51090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 51090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 51090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 51090 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 51090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51100 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800012c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800012c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 75 <= 000000000000000f000000001fffff44000000 - 51100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 51100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51100 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 51100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51110 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 51110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 51120 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 -instret:1808 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5112 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h2; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:1809 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5113 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:1810 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5115 calling cycle calling cycle calling cycle +instret:557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3525 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 51230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 51250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:1811 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 5125 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 51260 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:1812 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 5126 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 51270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51270 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001400000001fffff44000000 - 51270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 51280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 51280 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 - 51290 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001400000001fffff44000000 - 51290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 51290 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1813 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5129 -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000001800000001fffff44000000 - 51300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 51300 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 51300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 51310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:1814 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 5131 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 51320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1815 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 5132 -instret:1816 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 5132 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 51330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 51330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51340 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 51340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 51350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51350 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 51350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 51350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 51350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 51360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 51360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51360 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 51360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 51370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 51370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51370 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 51370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51370 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 51370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 51380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 51380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51380 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001800000001fffff44000000 - 51380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51380 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 51380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51390 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 51390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000000400000001fffff44000000 - 51400 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 - 51400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 1000000000000000040000001fffff44000000 - 51410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 51420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51430 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000000000001fffff44000000 - 51430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 0000000000000012000000001fffff44000000 - 51440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 51440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 51450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000000400000001fffff44000000 - 51460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 51460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51460 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 51470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 51470 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 51470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51470 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000012000000001fffff44000000 - 51480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 51480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51480 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 51480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000090000000001fffff44000000 - 51490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 51490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51490 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001248 -After delta: vaddr = 0x80001248 - 51490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 40000000200004921248ffff1ffff805821008 - 51500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 51500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51500 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000001800000001fffff44000000 - 51500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001248, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51500 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000400000001fffff44000000 - 51510 : [doFinishMem] DTlbResp { resp: <'h0000000080001248,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001248, check_high: 'h00000000080001250, check_inclusive: True } }, specBits: 'h004 } - 51510 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 51510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 - 51520 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 51520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3534 calling cycle - 51530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 51530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51540 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000400000001fffff44000000 - 51540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 51550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000012000000001fffff44000000 - 51560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 51560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000800000001fffff44000000 - 51570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 51570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51570 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 51580 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800012c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 51580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 51580 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 51580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51580 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 51590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 51590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51590 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 51590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800012c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000012400000001fffff44000000 - 51600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 51600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51600 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 51600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 0000000000000092000000001fffff44000000 - 51610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 51610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51610 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001800000001fffff44000000 - 51610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51610 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 51610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001250 -After delta: vaddr = 0x80001250 - 51610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - 51630 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle - 51640 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 51690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3543 calling cycle - 51700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 51720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 51730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 51730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 51730 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 51730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 - 51740 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001800000001fffff44000000 - 51740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 51740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 51740 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 51740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 51750 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 51750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 51760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1817 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5176 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h001 } - 51770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1818 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 5177 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h019 } - 51780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51780 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 51790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 51790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51790 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 51790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51790 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1819 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5179 -instret:1820 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5179 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 51800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51800 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 51800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51800 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1821 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 5180 -instret:1822 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 5180 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 51810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 51810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51810 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001800000001fffff44000000 - 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51810 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:1823 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 5181 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51820 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000000400000001fffff44000000 - 51830 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51830 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000000000001fffff44000000 - 51830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 1000000000000000040000001fffff44000000 - 51840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 51840 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h009 } - 51850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51850 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 - 51850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 51860 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 7c <= 0000000000000012000000001fffff44000000 - 51870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 51870 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000000000001fffff44000000 - 51870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1824 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5187 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 51880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 51880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 51880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1825 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5188 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h014 } - 51890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 51890 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1826 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5189 -instret:1827 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5189 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 51900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51900 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 51900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 51900 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 51900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1828 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5190 -instret:1829 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5190 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000012000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 51910 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 51910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 51910 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 51910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1830 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5191 -instret:1831 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5191 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000090000000001fffff44000000 - 51920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 51920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51920 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000001800000001fffff44000000 - 51920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001248 -After delta: vaddr = 0x80001248 - 51920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1832 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5192 -instret:1833 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5192 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 40000000200004921248ffff1ffff805821008 - 51930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 51930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001248, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 51930 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 51930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1834 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5193 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000400000001fffff44000000 - 51940 : [doFinishMem] DTlbResp { resp: <'h0000000080001248,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001248 o: 'h0000000000000240 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001248, check_high: 'h00000000080001250, check_inclusive: True } }, specBits: 'h000 } - 51940 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 51940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1835 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 5194 -instret:1836 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 5194 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 1000000000000000040000001fffff44000000 - 51950 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 51950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1837 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 5195 -instret:1838 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 5195 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2ee, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 51960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001248, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 51960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 51960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1839 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 5196 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51970 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000400000001fffff44000000 - 51970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 51970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 51970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 51970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 51970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 51970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 51970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1840 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5197 -instret:1841 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5197 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 51980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 51980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 51980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 51980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1842 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5198 -instret:1843 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5198 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000012000000001fffff44000000 - 51990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 51990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 51990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 51990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 51990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 51990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000000800000001fffff44000000 - 52000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 52000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52000 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 52000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 52010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 52010 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 52010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52010 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 52010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 52020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52020 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 52020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000012400000001fffff44000000 - 52030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 52030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52030 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 52030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000092000000001fffff44000000 - 52040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 52040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52040 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001800000001fffff44000000 - 52040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52040 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 52040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001250 -After delta: vaddr = 0x80001250 - 52040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 40000000200004941250ffff1ffff805821008 - 52050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52050 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000400000001fffff44000000 - 52050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001250, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52050 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 52050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52060 : [doFinishMem] DTlbResp { resp: <'h0000000080001250,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001250 o: 'h0000000000000248 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001250, check_high: 'h00000000080001258, check_inclusive: True } }, specBits: 'h004 } - 52060 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 52060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h2ee, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 52070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52070 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000800000001fffff44000000 - 52070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1844 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5207 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 52080 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000800000001fffff44000000 - 52080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1845 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5208 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 52090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1846 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5209 -instret:1847 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5209 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 52100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1848 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5210 -instret:1849 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5210 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 05 <= 0000000000000012000000001fffff44000000 - 52110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 52110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1850 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5211 -instret:1851 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5211 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 52120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 52120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 52120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52120 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1852 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5212 -instret:1853 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5212 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 52130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52130 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200004021008ffff1ffff805821008 - 52130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1854 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5213 -instret:1855 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5213 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 52140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 52140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52140 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1856 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5214 -instret:1857 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5214 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000012800000001fffff44000000 - 52150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 52150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52150 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001800000001fffff44000000 - 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52150 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1858 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5215 -instret:1859 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5215 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000094000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001250, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 52160 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 52160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001258 -After delta: vaddr = 0x80001258 - 52160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1860 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5216 -instret:1861 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5216 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200004961258ffff1ffff805821008 -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 52170 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000c00000001fffff44000000 - 52170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001258 o: 'h0000000000000250 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001258 o: 'h0000000000000250 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001258, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1862 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5217 -instret:1863 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5217 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h2ee, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 1000000000000000040000001fffff44000000 - 52180 : [doFinishMem] DTlbResp { resp: <'h0000000080001258,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001258 o: 'h0000000000000250 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001258, check_high: 'h00000000080001260, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 52180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 52190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 52200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52200 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000c00000001fffff44000000 - 52200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 46 <= 0000000000000012000000001fffff44000000 - 52210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 52210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52210 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 52220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52220 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000800000001fffff44000000 - 52220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52220 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 52230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52230 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 52230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52230 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 52230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 52240 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200004021008ffff1ffff805821008 - 52240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52240 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 52240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1864 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000012c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 52250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 52250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52250 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000001800000001fffff44000000 - 52250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1865 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000096000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 52260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52260 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 52260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001260 -After delta: vaddr = 0x80001260 - 52260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1866 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5226 -instret:1867 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5226 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200004981260ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52270 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 52270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001260 o: 'h0000000000000258 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001260 o: 'h0000000000000258 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001260, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1868 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5227 -instret:1869 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5227 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52280 : [doFinishMem] DTlbResp { resp: <'h0000000080001260,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001260 o: 'h0000000000000258 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001260, check_high: 'h00000000080001268, check_inclusive: True } }, specBits: 'h010 } - 52280 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000001000000001fffff44000000 - 52280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1870 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5228 -instret:1871 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5228 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 1000000000000000040000001fffff44000000 - 52290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 52290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1872 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5229 -instret:1873 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5229 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52300 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000001000000001fffff44000000 - 52300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h017 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1874 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5230 -instret:1875 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5230 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 52310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1876 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5231 -instret:1877 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5231 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6d <= 0000000000000012000000001fffff44000000 - 52320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 52320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1878 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5232 -instret:1879 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5232 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000001400000001fffff44000000 - 52330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001258, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 52330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52330 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 52330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1880 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5233 -instret:1881 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5233 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 52340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 52340 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 52340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52340 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 52340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1882 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5234 -instret:1883 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5234 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 52350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 52350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52350 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6c <= 40000000200004021008ffff1ffff805821008 - 52350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 52350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000013000000001fffff44000000 - 52360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 52360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52360 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 52360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000098000000001fffff44000000 - 52370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 52370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52370 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000001800000001fffff44000000 - 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52370 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001268 -After delta: vaddr = 0x80001268 - 52370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 63 <= 400000002000049a1268ffff1ffff805821008 - 52380 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003000000001fffff44000000 - 52380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001268 o: 'h0000000000000260 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001268 o: 'h0000000000000260 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001268, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 1000000000000000040000001fffff44000000 - 52390 : [doFinishMem] DTlbResp { resp: <'h0000000080001268,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001268 o: 'h0000000000000260 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001268, check_high: 'h00000000080001270, check_inclusive: True } }, specBits: 'h014 } - 52390 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52390 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001400000001fffff44000000 - 52390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 52400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52400 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52410 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000c00000001fffff44000000 - 52410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 52420 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001400000001fffff44000000 - 52420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 76 <= 0000000000000012000000001fffff44000000 - 52430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 52430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:1884 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5243 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52440 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1885 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5244 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52450 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 52450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1886 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5245 -instret:1887 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5245 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 52460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1888 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5246 -instret:1889 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5246 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000013400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1890 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5247 -instret:1891 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5247 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 000000000000009a000000001fffff44000000 - 52480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 52480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001270 -After delta: vaddr = 0x80001270 - 52480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1892 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5248 -instret:1893 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5248 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 400000002000049c1270ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 52490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001270 o: 'h0000000000000268 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001270 o: 'h0000000000000268 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001270, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52490 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1894 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5249 -instret:1895 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5249 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52500 : [doFinishMem] DTlbResp { resp: <'h0000000080001270,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001270 o: 'h0000000000000268 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001270, check_high: 'h00000000080001278, check_inclusive: True } }, specBits: 'h00c } - 52500 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200004021008ffff1ffff805821008 - 52500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52500 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1896 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5250 -instret:1897 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5250 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 52510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 52510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52510 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000001800000001fffff44000000 - 52510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1898 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5251 -instret:1899 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5251 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001260, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 52520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52520 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 52520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1900 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5252 -instret:1901 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5252 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000000400000001fffff44000000 - 52530 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 52530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 52530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1902 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5253 -instret:1903 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5253 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 52540 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000001800000001fffff44000000 - 52540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 52550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52560 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001800000001fffff44000000 - 52560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 52570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 52570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52570 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 52570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4d <= 0000000000000012000000001fffff44000000 - 52580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 52580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52580 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 52580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 52590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 52600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 -instret:1904 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5260 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1905 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5261 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000013800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1906 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5262 -instret:1907 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5262 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 000000000000009c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001278 -After delta: vaddr = 0x80001278 - 52630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1908 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5263 -instret:1909 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5263 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 400000002000049e1278ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001278 o: 'h0000000000000270 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001278 o: 'h0000000000000270 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001278, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1910 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5264 -instret:1911 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5264 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52650 : [doFinishMem] DTlbResp { resp: <'h0000000080001278,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001278 o: 'h0000000000000270 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001278, check_high: 'h00000000080001280, check_inclusive: True } }, specBits: 'h028 } - 52650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1912 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5265 -instret:1913 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5265 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 52660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1914 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5266 -instret:1915 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5266 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 52670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52670 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 52670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1916 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5267 -instret:1917 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5267 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 52680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 52680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52680 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 67 <= 40000000200004021008ffff1ffff805821008 - 52680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52680 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1918 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5268 -instret:1919 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5268 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001268, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 52690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52690 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001800000001fffff44000000 - 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52690 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1920 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5269 -instret:1921 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5269 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 52700 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1922 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5270 -instret:1923 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5270 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 52710 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001c00000001fffff44000000 - 52710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 52720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52730 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001c00000001fffff44000000 - 52730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 52740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 52740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52740 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5e <= 0000000000000012000000001fffff44000000 - 52750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 52750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52750 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 52750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52760 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 52770 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 -instret:1924 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5277 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1925 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5278 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000013c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1926 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5279 -instret:1927 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5279 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000009e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001280 -After delta: vaddr = 0x80001280 - 52800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1928 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5280 -instret:1929 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5280 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 40000000200004a01280ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001280 o: 'h0000000000000278 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001280 o: 'h0000000000000278 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001280, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1930 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5281 -instret:1931 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5281 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52820 : [doFinishMem] DTlbResp { resp: <'h0000000080001280,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001280 o: 'h0000000000000278 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001280, check_high: 'h00000000080001288, check_inclusive: True } }, specBits: 'h030 } - 52820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1932 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5282 -instret:1933 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5282 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 52830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1934 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5283 -instret:1935 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5283 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 52840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 52840 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1936 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5284 -instret:1937 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5284 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 52850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 52850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52850 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 52850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 52850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 52850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1938 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5285 -instret:1939 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5285 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001270, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 52860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000001800000001fffff44000000 - 52860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 52860 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 52860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1940 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5286 -instret:1941 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5286 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000000400000001fffff44000000 - 52870 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 52870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 52870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1942 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5287 -instret:1943 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5287 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 52880 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002000000001fffff44000000 - 52880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 52880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 52890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 52890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 52890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 52890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52900 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000002000000001fffff44000000 - 52900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 52900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 52910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 52910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 52910 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 52910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 52910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 73 <= 0000000000000012000000001fffff44000000 - 52920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 52920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 52920 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000001800000001fffff44000000 - 52920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 52920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 52930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 52930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 52930 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 52930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 52940 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 -instret:1944 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5294 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1945 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5295 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000014000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1946 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5296 -instret:1947 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5296 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 00000000000000a0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001288 -After delta: vaddr = 0x80001288 - 52970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1948 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5297 -instret:1949 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5297 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200004a21288ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 52980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001288 o: 'h0000000000000280 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001288 o: 'h0000000000000280 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001288, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 52980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 52980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1950 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5298 -instret:1951 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5298 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 52990 : [doFinishMem] DTlbResp { resp: <'h0000000080001288,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001288 o: 'h0000000000000280 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001288, check_high: 'h00000000080001290, check_inclusive: True } }, specBits: 'h014 } - 52990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 52990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 52990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1952 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5299 -instret:1953 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5299 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 53000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1954 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5300 -instret:1955 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5300 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 53010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53010 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 53010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1956 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5301 -instret:1957 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5301 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 53020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53020 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 53020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53020 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1958 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5302 -instret:1959 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5302 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001278, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53030 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001800000001fffff44000000 - 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53030 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1960 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5303 -instret:1961 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5303 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 - 53040 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1962 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5304 -instret:1963 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5304 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53050 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000002400000001fffff44000000 - 53050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53070 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002400000001fffff44000000 - 53070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 53080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53080 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 0000000000000012000000001fffff44000000 - 53090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 53090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53090 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000001c00000001fffff44000000 - 53090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53100 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53110 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 -instret:1964 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5311 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1965 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5312 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000014400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1966 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5313 -instret:1967 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5313 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 00000000000000a2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001290 -After delta: vaddr = 0x80001290 - 53140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1968 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5314 -instret:1969 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5314 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200004a41290ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001290 o: 'h0000000000000288 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001290 o: 'h0000000000000288 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001290, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 53150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1970 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5315 -instret:1971 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5315 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53160 : [doFinishMem] DTlbResp { resp: <'h0000000080001290,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001290 o: 'h0000000000000288 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001290, check_high: 'h00000000080001298, check_inclusive: True } }, specBits: 'h00c } - 53160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 53160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 53160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1972 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5316 -instret:1973 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5316 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 53170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1974 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5317 -instret:1975 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5317 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 53180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53180 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 53180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1976 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5318 -instret:1977 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5318 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 53190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53190 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200004021008ffff1ffff805821008 - 53190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53190 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 53190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1978 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5319 -instret:1979 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5319 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001280, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53200 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001800000001fffff44000000 - 53200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53200 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 53200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:1980 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5320 -instret:1981 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5320 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000000400000001fffff44000000 - 53210 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 53210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:1982 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5321 -instret:1983 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5321 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53220 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002800000001fffff44000000 - 53220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53240 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53240 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002800000001fffff44000000 - 53240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 53240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 53240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 53250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53250 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 53250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53260 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001300, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 08 <= 0000000000000012000000001fffff44000000 - 53260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 53260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53260 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002000000001fffff44000000 - 53260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53270 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 53270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53280 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 -instret:1984 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5328 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:1985 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5329 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000014800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1986 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5330 -instret:1987 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5330 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 00000000000000a4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001298 -After delta: vaddr = 0x80001298 - 53310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1988 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5331 -instret:1989 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5331 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200004a61298ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001298 o: 'h0000000000000290 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001298 o: 'h0000000000000290 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001298, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 53320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1990 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5332 -instret:1991 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5332 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53330 : [doFinishMem] DTlbResp { resp: <'h0000000080001298,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001298 o: 'h0000000000000290 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001298, check_high: 'h000000000800012a0, check_inclusive: True } }, specBits: 'h028 } - 53330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 53330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 53330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:1992 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5333 -instret:1993 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5333 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 53340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:1994 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5334 -instret:1995 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5334 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 53350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53350 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:1996 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5335 -instret:1997 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5335 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 53360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53360 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 53360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53360 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:1998 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5336 -instret:1999 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5336 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001288, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53370 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000001800000001fffff44000000 - 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53370 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2000 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5337 -instret:2001 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5337 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 - 53380 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2002 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5338 -instret:2003 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5338 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53390 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002c00000001fffff44000000 - 53390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 53400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53410 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53410 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002c00000001fffff44000000 - 53410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 53420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 53420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53420 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 51 <= 0000000000000012000000001fffff44000000 - 53430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 53430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53430 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002400000001fffff44000000 - 53430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53440 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 53450 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 -instret:2004 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5345 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2005 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5346 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000014c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2006 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5347 -instret:2007 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5347 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 00000000000000a6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012a0 -After delta: vaddr = 0x800012a0 - 53480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2008 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5348 -instret:2009 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5348 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 40000000200004a812a0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800012a0 o: 'h0000000000000298 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012a0 o: 'h0000000000000298 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 53490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2010 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5349 -instret:2011 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5349 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53500 : [doFinishMem] DTlbResp { resp: <'h00000000800012a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012a0 o: 'h0000000000000298 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012a0, check_high: 'h000000000800012a8, check_inclusive: True } }, specBits: 'h030 } - 53500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 53500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 53500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2012 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5350 -instret:2013 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5350 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 53510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2014 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5351 -instret:2015 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5351 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 53520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53520 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 53520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2016 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5352 -instret:2017 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5352 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 53530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53530 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 53530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53530 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 53530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2018 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5353 -instret:2019 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5353 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001290, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53540 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000001800000001fffff44000000 - 53540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53540 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 53540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2020 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5354 -instret:2021 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5354 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000000400000001fffff44000000 - 53550 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 53550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2022 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5355 -instret:2023 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5355 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53560 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 53560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 53570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53580 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53580 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 - 53580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 53590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 53590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53590 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 53590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000012000000001fffff44000000 - 53600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 53600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53600 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002800000001fffff44000000 - 53600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53610 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 53620 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 -instret:2024 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5362 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2025 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5363 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000015000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2026 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5364 -instret:2027 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5364 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 00000000000000a8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012a8 -After delta: vaddr = 0x800012a8 - 53650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2028 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5365 -instret:2029 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5365 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 40000000200004aa12a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 53660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2030 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5366 -instret:2031 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5366 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53670 : [doFinishMem] DTlbResp { resp: <'h00000000800012a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012a8, check_high: 'h000000000800012b0, check_inclusive: True } }, specBits: 'h014 } - 53670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 53670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 53670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2032 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5367 -instret:2033 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5367 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 53680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2034 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5368 -instret:2035 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5368 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 53690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53690 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2036 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5369 -instret:2037 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5369 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 53700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53700 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200004021008ffff1ffff805821008 - 53700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53700 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2038 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5370 -instret:2039 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5370 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001298, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53710 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000001800000001fffff44000000 - 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53710 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2040 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5371 -instret:2041 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5371 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 53720 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 - 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2042 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5372 -instret:2043 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5372 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53730 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003400000001fffff44000000 - 53730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001300, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 53740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53750 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53750 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003400000001fffff44000000 - 53750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 53760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53760 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 53760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 61 <= 0000000000000012000000001fffff44000000 - 53770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 53770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53770 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002c00000001fffff44000000 - 53770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53780 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 53780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 53790 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 -instret:2044 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5379 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2045 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5380 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000015400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2046 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5381 -instret:2047 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5381 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 00000000000000aa000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012b0 -After delta: vaddr = 0x800012b0 - 53820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2048 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5382 -instret:2049 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5382 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 40000000200004ac12b0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 53830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2050 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5383 -instret:2051 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5383 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53840 : [doFinishMem] DTlbResp { resp: <'h00000000800012b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012b0, check_high: 'h000000000800012b8, check_inclusive: True } }, specBits: 'h00c } - 53840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 53840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 53840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2052 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5384 -instret:2053 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5384 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 53850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2054 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5385 -instret:2055 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5385 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 53860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 53860 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 53860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2056 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5386 -instret:2057 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5386 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 53870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 53870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53870 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 64 <= 40000000200004021008ffff1ffff805821008 - 53870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 53870 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 53870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2058 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5387 -instret:2059 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5387 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 53880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53880 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001800000001fffff44000000 - 53880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 53880 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 53880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2060 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5388 -instret:2061 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5388 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000000400000001fffff44000000 - 53890 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 53890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 53890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2062 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5389 -instret:2063 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5389 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 53900 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003800000001fffff44000000 - 53900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 53900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 53910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 53910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 53910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 53920 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53920 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003800000001fffff44000000 - 53920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 53920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3552 calling cycle - 53930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 53930 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 53930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6f <= 0000000000000012000000001fffff44000000 - 53940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 53940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 53940 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 53940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 53940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 53950 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 53960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 53960 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 -instret:2064 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5396 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h2; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:2065 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5397 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:2066 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5399 calling cycle calling cycle calling cycle calling cycle +instret:561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3561 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 54060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 54070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 54080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 54090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 54090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:2067 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 5409 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 54100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 54100 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 54100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:2068 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 5410 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 54110 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000001800000001fffff44000000 - 54110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 54120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000000000001fffff44000000 - 54130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 54130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 54130 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 54130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2069 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5413 -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000001c00000001fffff44000000 - 54140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 54140 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 - 54140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 54150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 54150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:2070 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 5415 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 54160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2071 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 5416 -instret:2072 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 5416 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 54170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54180 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 54180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 54190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54190 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 54190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 54190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 54200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 54200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54200 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 54200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 54210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 54210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54210 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200004021008ffff1ffff805821008 - 54210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 54210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 54210 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 54210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 54220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 54220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54220 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001c00000001fffff44000000 - 54220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54220 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 54220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54230 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001c00000001fffff44000000 - 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54230 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54240 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 54240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2073 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5424 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54250 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 - 54250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2074 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 5425 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 1000000000000000040000001fffff44000000 - 54260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 54260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2075 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5426 -instret:2076 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5426 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54270 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 54270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2077 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 5427 -instret:2078 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 5427 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 54280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:2079 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 5428 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0b <= 0000000000000015000000001fffff44000000 - 54290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 54290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000400000001fffff44000000 - 54300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 54300 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54300 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 54310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 54310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54310 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 54310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54310 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 54320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54320 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000000000001fffff44000000 - 54320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54320 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 0000000000000015000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 54330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54330 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200004021008ffff1ffff805821008 - 54330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54330 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 00000000000000a8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 54340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54340 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000001c00000001fffff44000000 - 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54340 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012a8 -After delta: vaddr = 0x800012a8 - 54340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2080 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5434 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 40000000200004aa12a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 54350 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 54350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2081 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5435 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54360 : [doFinishMem] DTlbResp { resp: <'h00000000800012a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012a8 o: 'h00000000000002a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012a8, check_high: 'h000000000800012b0, check_inclusive: True } }, specBits: 'h000 } - 54360 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000400000001fffff44000000 - 54360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2082 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5436 -instret:2083 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5436 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 54370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2084 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5437 -instret:2085 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5437 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54380 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000000400000001fffff44000000 - 54380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2086 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5438 -instret:2087 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5438 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 54390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2088 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5439 -instret:2089 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5439 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 40 <= 0000000000000015000000001fffff44000000 - 54400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 54400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2090 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5440 -instret:2091 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5440 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000000800000001fffff44000000 - 54410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 54410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54410 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 54410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2092 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5441 -instret:2093 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5441 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 54420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 54420 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 54420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54420 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 54420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2094 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5442 -instret:2095 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5442 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 54430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54430 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200004021008ffff1ffff805821008 - 54430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2096 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5443 -instret:2097 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5443 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000015400000001fffff44000000 - 54440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 54440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54440 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 54440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2098 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5444 -instret:2099 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5444 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 00000000000000aa000000001fffff44000000 - 54450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 54450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54450 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 54450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54450 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 54450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012b0 -After delta: vaddr = 0x800012b0 - 54450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 40000000200004ac12b0ffff1ffff805821008 -[RFile] wr_ 1: r 7a <= 0000000000000000400000001fffff44000000 - 54460 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 54460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 54460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 1000000000000000040000001fffff44000000 - 54470 : [doFinishMem] DTlbResp { resp: <'h00000000800012b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012b0 o: 'h00000000000002a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012b0, check_high: 'h000000000800012b8, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 54470 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000800000001fffff44000000 - 54470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 54480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 54480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54490 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 - 54490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 54500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54500 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 54500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 62 <= 0000000000000015000000001fffff44000000 - 54510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 54510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54510 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000400000001fffff44000000 - 54510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 54520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54520 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 54520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 54530 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 54530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54530 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 54530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2100 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5453 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 54540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 54540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54540 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 54540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2101 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5454 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000015800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 54550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54550 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2102 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5455 -instret:2103 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5455 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 00000000000000ac000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 54560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54560 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54560 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012b8 -After delta: vaddr = 0x800012b8 - 54560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2104 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5456 -instret:2105 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5456 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 40000000200004ae12b8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54570 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 54570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800012b8 o: 'h00000000000002b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012b8 o: 'h00000000000002b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2106 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5457 -instret:2107 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5457 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000000400000001fffff44000000 - 54580 : [doFinishMem] DTlbResp { resp: <'h00000000800012b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012b8 o: 'h00000000000002b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012b8, check_high: 'h000000000800012c0, check_inclusive: True } }, specBits: 'h004 } - 54580 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000c00000001fffff44000000 - 54580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2108 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5458 -instret:2109 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5458 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 54590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2110 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5459 -instret:2111 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5459 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54600 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000c00000001fffff44000000 - 54600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2112 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5460 -instret:2113 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5460 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 54610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2114 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5461 -instret:2115 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5461 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 59 <= 0000000000000015000000001fffff44000000 - 54620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 54620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2116 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5462 -instret:2117 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5462 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000001000000001fffff44000000 - 54630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 54630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54630 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2118 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5463 -instret:2119 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5463 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 54640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 54640 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 54640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54640 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 54650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 54650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54650 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200004021008ffff1ffff805821008 - 54650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000015c00000001fffff44000000 - 54660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 54660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54660 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 00000000000000ae000000001fffff44000000 - 54670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 54670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54670 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001c00000001fffff44000000 - 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54670 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012c0 -After delta: vaddr = 0x800012c0 - 54670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 4a <= 40000000200004b012c0ffff1ffff805821008 - 54680 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 54680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800012c0 o: 'h00000000000002b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012c0 o: 'h00000000000002b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 1000000000000000040000001fffff44000000 - 54690 : [doFinishMem] DTlbResp { resp: <'h00000000800012c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012c0 o: 'h00000000000002b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012c0, check_high: 'h000000000800012c8, check_inclusive: True } }, specBits: 'h00c } - 54690 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54690 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000001000000001fffff44000000 - 54690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 54700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54700 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54710 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000800000001fffff44000000 - 54710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 54720 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000001000000001fffff44000000 - 54720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 71 <= 0000000000000015000000001fffff44000000 - 54730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 54730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2120 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5473 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 54740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54740 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 54740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2121 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5474 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54750 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 54750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2122 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5475 -instret:2123 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5475 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 54760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2124 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5476 -instret:2125 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5476 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000016000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2126 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5477 -instret:2127 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5477 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 00000000000000b0000000001fffff44000000 - 54780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 54780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012c8 -After delta: vaddr = 0x800012c8 - 54780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2128 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5478 -instret:2129 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5478 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 40000000200004b212c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 54790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800012c8 o: 'h00000000000002c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012c8 o: 'h00000000000002c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54790 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 54790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2130 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5479 -instret:2131 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5479 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54800 : [doFinishMem] DTlbResp { resp: <'h00000000800012c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012c8 o: 'h00000000000002c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012c8, check_high: 'h000000000800012d0, check_inclusive: True } }, specBits: 'h018 } - 54800 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 51 <= 40000000200004021008ffff1ffff805821008 - 54800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54800 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 54800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2132 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5480 -instret:2133 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5480 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 54810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 54810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54810 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001c00000001fffff44000000 - 54810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2134 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5481 -instret:2135 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5481 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 54820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54820 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 54820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2136 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5482 -instret:2137 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5482 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 - 54830 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 54830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 54830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800012b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2138 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5483 -instret:2139 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5483 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 54840 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001400000001fffff44000000 - 54840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 54850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54860 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54860 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001400000001fffff44000000 - 54860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 54870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 54870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 54870 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 54870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6a <= 0000000000000015000000001fffff44000000 - 54880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 54880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54880 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 - 54880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 54890 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 54900 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 -instret:2140 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5490 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2141 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5491 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000016400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2142 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5492 -instret:2143 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5492 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 00000000000000b2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012d0 -After delta: vaddr = 0x800012d0 - 54930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2144 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5493 -instret:2145 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5493 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 40000000200004b412d0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800012d0 o: 'h00000000000002c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012d0 o: 'h00000000000002c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 54940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2146 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5494 -instret:2147 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5494 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54950 : [doFinishMem] DTlbResp { resp: <'h00000000800012d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012d0 o: 'h00000000000002c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012d0, check_high: 'h000000000800012d8, check_inclusive: True } }, specBits: 'h030 } - 54950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 54950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 54950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2148 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5495 -instret:2149 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5495 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 54960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 54960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 54960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2150 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5496 -instret:2151 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5496 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 54970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 54970 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 54970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2152 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5497 -instret:2153 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5497 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 54980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 54980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 54980 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200004021008ffff1ffff805821008 - 54980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 54980 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2154 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5498 -instret:2155 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5498 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 54990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 54990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 54990 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001c00000001fffff44000000 - 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 54990 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 54990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 54990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2156 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5499 -instret:2157 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5499 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000000400000001fffff44000000 - 55000 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2158 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5500 -instret:2159 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5500 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55010 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000001800000001fffff44000000 - 55010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55030 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001800000001fffff44000000 - 55030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 55030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 55030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3570 calling cycle - 55040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55040 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55050 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001340, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 0a <= 0000000000000015000000001fffff44000000 - 55050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 55050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55050 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001000000001fffff44000000 - 55050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55060 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55070 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 -instret:2160 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5507 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2161 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5508 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000016800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2162 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5509 -instret:2163 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5509 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 00000000000000b4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012d8 -After delta: vaddr = 0x800012d8 - 55100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2164 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5510 -instret:2165 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5510 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200004b612d8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800012d8 o: 'h00000000000002d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012d8 o: 'h00000000000002d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2166 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5511 -instret:2167 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5511 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55120 : [doFinishMem] DTlbResp { resp: <'h00000000800012d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012d8 o: 'h00000000000002d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012d8, check_high: 'h000000000800012e0, check_inclusive: True } }, specBits: 'h024 } - 55120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2168 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5512 -instret:2169 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5512 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 55130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2170 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5513 -instret:2171 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5513 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 55140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55140 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 55140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2172 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5514 -instret:2173 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5514 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 55150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 55150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55150 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 40000000200004021008ffff1ffff805821008 - 55150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55150 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 55150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2174 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5515 -instret:2175 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5515 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 55160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55160 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001c00000001fffff44000000 - 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55160 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2176 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5516 -instret:2177 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5516 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000400000001fffff44000000 - 55170 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2178 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5517 -instret:2179 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5517 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55180 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001c00000001fffff44000000 - 55180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55200 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001c00000001fffff44000000 - 55200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 55210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55210 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5f <= 0000000000000015000000001fffff44000000 - 55220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 55220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55220 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001400000001fffff44000000 - 55220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55230 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55240 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 -instret:2180 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5524 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2181 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5525 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000016c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2182 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5526 -instret:2183 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5526 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 00000000000000b6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012e0 -After delta: vaddr = 0x800012e0 - 55270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2184 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5527 -instret:2185 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5527 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200004b812e0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800012e0 o: 'h00000000000002d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012e0 o: 'h00000000000002d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2186 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5528 -instret:2187 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5528 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55290 : [doFinishMem] DTlbResp { resp: <'h00000000800012e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012e0 o: 'h00000000000002d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012e0, check_high: 'h000000000800012e8, check_inclusive: True } }, specBits: 'h00c } - 55290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2188 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5529 -instret:2189 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5529 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 55300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2190 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5530 -instret:2191 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5530 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 55310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55310 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 55310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2192 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5531 -instret:2193 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5531 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 55320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 55320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55320 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 55320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55320 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 55320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2194 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5532 -instret:2195 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5532 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 55330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55330 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000001c00000001fffff44000000 - 55330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55330 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 55330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2196 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5533 -instret:2197 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5533 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000000400000001fffff44000000 - 55340 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 55340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2198 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5534 -instret:2199 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5534 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55350 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 55350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 55360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55370 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55370 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 55370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 55380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 55380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55380 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 55380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 44 <= 0000000000000015000000001fffff44000000 - 55390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 55390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55390 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000001800000001fffff44000000 - 55390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55400 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 55400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 55410 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 -instret:2200 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5541 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2201 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5542 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000017000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2202 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5543 -instret:2203 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5543 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 00000000000000b8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012e8 -After delta: vaddr = 0x800012e8 - 55440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2204 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5544 -instret:2205 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5544 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 40000000200004ba12e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800012e8 o: 'h00000000000002e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012e8 o: 'h00000000000002e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2206 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5545 -instret:2207 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5545 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55460 : [doFinishMem] DTlbResp { resp: <'h00000000800012e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012e8 o: 'h00000000000002e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012e8, check_high: 'h000000000800012f0, check_inclusive: True } }, specBits: 'h018 } - 55460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2208 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5546 -instret:2209 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5546 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 55470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2210 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5547 -instret:2211 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5547 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 55480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55480 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2212 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5548 -instret:2213 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5548 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 55490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 55490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55490 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 55490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55490 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 55490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2214 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5549 -instret:2215 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5549 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 55500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55500 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55500 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2216 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5550 -instret:2217 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5550 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000000400000001fffff44000000 - 55510 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2218 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5551 -instret:2219 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5551 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55520 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000002400000001fffff44000000 - 55520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55530 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001340, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 55530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 55530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55540 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55540 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002400000001fffff44000000 - 55540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 55550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 55550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55550 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 72 <= 0000000000000015000000001fffff44000000 - 55560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 55560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55560 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001c00000001fffff44000000 - 55560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55570 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 55580 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 -instret:2220 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5558 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2221 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5559 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000017400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2222 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5560 -instret:2223 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5560 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 00000000000000ba000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012f0 -After delta: vaddr = 0x800012f0 - 55610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2224 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5561 -instret:2225 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5561 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 40000000200004bc12f0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800012f0 o: 'h00000000000002e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012f0 o: 'h00000000000002e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2226 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5562 -instret:2227 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5562 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55630 : [doFinishMem] DTlbResp { resp: <'h00000000800012f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012f0 o: 'h00000000000002e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012f0, check_high: 'h000000000800012f8, check_inclusive: True } }, specBits: 'h030 } - 55630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2228 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5563 -instret:2229 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5563 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 55640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2230 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5564 -instret:2231 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5564 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 55650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55650 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 55650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2232 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5565 -instret:2233 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5565 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 55660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 55660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55660 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6e <= 40000000200004021008ffff1ffff805821008 - 55660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55660 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2234 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5566 -instret:2235 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5566 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 55670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55670 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 55670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55670 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 55670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2236 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5567 -instret:2237 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5567 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000000400000001fffff44000000 - 55680 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800012e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2238 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5568 -instret:2239 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5568 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55690 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002800000001fffff44000000 - 55690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55710 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002800000001fffff44000000 - 55710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 55720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55720 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 55720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 70 <= 0000000000000015000000001fffff44000000 - 55730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 55730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55730 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 - 55730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55740 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 55740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 55750 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003000000001fffff44000000 -instret:2240 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5575 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2241 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5576 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000017800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2242 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5577 -instret:2243 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5577 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 00000000000000bc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800012f8 -After delta: vaddr = 0x800012f8 - 55780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2244 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5578 -instret:2245 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5578 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 40000000200004be12f8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800012f8 o: 'h00000000000002f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800012f8 o: 'h00000000000002f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800012f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2246 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5579 -instret:2247 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5579 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55800 : [doFinishMem] DTlbResp { resp: <'h00000000800012f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800012f8 o: 'h00000000000002f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800012f8, check_high: 'h00000000080001300, check_inclusive: True } }, specBits: 'h024 } - 55800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2248 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5580 -instret:2249 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5580 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 55810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2250 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5581 -instret:2251 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5581 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 55820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55820 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2252 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5582 -instret:2253 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5582 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 55830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 55830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55830 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 55830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 55830 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2254 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5583 -instret:2255 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5583 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 55840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55840 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001c00000001fffff44000000 - 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 55840 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2256 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5584 -instret:2257 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5584 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000000400000001fffff44000000 - 55850 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800012e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2258 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5585 -instret:2259 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5585 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 55860 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002c00000001fffff44000000 - 55860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55880 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55880 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002c00000001fffff44000000 - 55880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 55890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 55890 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4b <= 0000000000000015000000001fffff44000000 - 55900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 55900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55900 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002400000001fffff44000000 - 55900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 55910 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 55920 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 -instret:2260 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5592 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2261 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5593 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000017c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2262 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5594 -instret:2263 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5594 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 00000000000000be000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001300 -After delta: vaddr = 0x80001300 - 55950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2264 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5595 -instret:2265 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5595 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200004c01300ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001300 o: 'h00000000000002f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001300 o: 'h00000000000002f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001300, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 55960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2266 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5596 -instret:2267 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5596 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55970 : [doFinishMem] DTlbResp { resp: <'h0000000080001300,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001300 o: 'h00000000000002f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001300, check_high: 'h00000000080001308, check_inclusive: True } }, specBits: 'h00c } - 55970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 55970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 55970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2268 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5597 -instret:2269 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5597 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 55980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 55980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 55980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 55980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2270 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5598 -instret:2271 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5598 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 55990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 55990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 55990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 55990 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 55990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 55990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2272 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5599 -instret:2273 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5599 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 56000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 56000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56000 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 56000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56000 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2274 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5600 -instret:2275 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5600 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 56010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56010 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001c00000001fffff44000000 - 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56010 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800012f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2276 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5601 -instret:2277 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5601 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000 - 56020 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800012f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800012f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2278 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5602 -instret:2279 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5602 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 56030 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 56030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 56040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56050 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 - 56050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 56060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 56060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56060 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000015000000001fffff44000000 - 56070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 56070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56070 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002800000001fffff44000000 - 56070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56080 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 56080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 56090 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 -instret:2280 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5609 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2281 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5610 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000018000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2282 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5611 -instret:2283 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5611 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 00000000000000c0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001308 -After delta: vaddr = 0x80001308 - 56120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2284 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5612 -instret:2285 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5612 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 40000000200004c21308ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001308, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2286 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5613 -instret:2287 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5613 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56140 : [doFinishMem] DTlbResp { resp: <'h0000000080001308,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001308, check_high: 'h00000000080001310, check_inclusive: True } }, specBits: 'h018 } - 56140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2288 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5614 -instret:2289 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5614 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 56150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2290 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5615 -instret:2291 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5615 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 56160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56160 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2292 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5616 -instret:2293 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5616 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 56170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 56170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56170 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 78 <= 40000000200004021008ffff1ffff805821008 - 56170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56170 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2294 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5617 -instret:2295 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5617 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800012f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 56180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56180 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001c00000001fffff44000000 - 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56180 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800012f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2296 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5618 -instret:2297 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5618 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000000400000001fffff44000000 - 56190 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003000000001fffff44000000 - 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800012f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800012f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2298 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5619 -instret:2299 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5619 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 56200 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003400000001fffff44000000 - 56200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 56210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56220 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003400000001fffff44000000 - 56220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 56230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 56230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56230 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 60 <= 0000000000000015000000001fffff44000000 - 56240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 56240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56240 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002c00000001fffff44000000 - 56240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56250 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 56260 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003000000001fffff44000000 -instret:2300 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5626 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2301 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5627 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000018400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2302 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5628 -instret:2303 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5628 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 00000000000000c2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001310 -After delta: vaddr = 0x80001310 - 56290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2304 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5629 -instret:2305 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5629 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200004c41310ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001310, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2306 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5630 -instret:2307 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5630 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56310 : [doFinishMem] DTlbResp { resp: <'h0000000080001310,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001310, check_high: 'h00000000080001318, check_inclusive: True } }, specBits: 'h030 } - 56310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2308 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5631 -instret:2309 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5631 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 56320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2310 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5632 -instret:2311 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5632 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 56330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56330 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2312 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5633 -instret:2313 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5633 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 56340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 56340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56340 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5a <= 40000000200004021008ffff1ffff805821008 - 56340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56340 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2314 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5634 -instret:2315 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5634 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001300, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 56350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56350 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001c00000001fffff44000000 - 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56350 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2316 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5635 -instret:2317 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5635 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000000400000001fffff44000000 - 56360 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2318 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5636 -instret:2319 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5636 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 56370 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003800000001fffff44000000 - 56370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 56380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56390 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56390 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003800000001fffff44000000 - 56390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 56390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 56400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 56400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56400 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001380, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 77 <= 0000000000000015000000001fffff44000000 - 56410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 56410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56410 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 56410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56420 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3579 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 56430 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 -instret:2320 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5643 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:2321 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5644 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:2322 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5646 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3588 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 56530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 56540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 56550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 56560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 56560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:2323 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 5656 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 56570 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:2324 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 5657 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 56580 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000001c00000001fffff44000000 - 56580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 56590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000000000000001fffff44000000 - 56600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 56600 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2325 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5660 -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000002000000001fffff44000000 - 56610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 56610 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 56610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 56620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 56620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:2326 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 5662 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 56630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2327 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 5663 -instret:2328 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 5663 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 56640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56650 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 56660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56660 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 56660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 56670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 56670 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56670 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 56680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 56680 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56680 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004021008ffff1ffff805821008 - 56680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 56680 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 56690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 56690 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56690 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002000000001fffff44000000 - 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56690 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56700 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002000000001fffff44000000 - 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56700 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56710 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 56710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2329 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5671 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56720 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 56720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2330 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 5672 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 1000000000000000040000001fffff44000000 - 56730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 56730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2331 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5673 -instret:2332 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5673 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56740 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000000000001fffff44000000 - 56740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2333 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 5674 -instret:2334 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 5674 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 56750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:2335 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 5675 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000018000000001fffff44000000 - 56760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 56760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 - 56770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 56770 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56770 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 56780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 56780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56780 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 56780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56780 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 56790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56790 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000000000000001fffff44000000 - 56790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56790 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000018000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 56800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56800 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200004021008ffff1ffff805821008 - 56800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56800 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 00000000000000c0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 56810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56810 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002000000001fffff44000000 - 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56810 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001308 -After delta: vaddr = 0x80001308 - 56810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2336 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5681 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 40000000200004c21308ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 56820 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 56820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001308, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2337 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5682 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56830 : [doFinishMem] DTlbResp { resp: <'h0000000080001308,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001308 o: 'h0000000000000300 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001308, check_high: 'h00000000080001310, check_inclusive: True } }, specBits: 'h000 } - 56830 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 - 56830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2338 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5683 -instret:2339 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5683 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 56840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2340 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5684 -instret:2341 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5684 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56850 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000400000001fffff44000000 - 56850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2342 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5685 -instret:2343 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5685 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 56860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2344 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5686 -instret:2345 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5686 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 57 <= 0000000000000018000000001fffff44000000 - 56870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 56870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2346 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5687 -instret:2347 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5687 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000000800000001fffff44000000 - 56880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 56880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56880 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2348 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5688 -instret:2349 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5688 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 56890 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001380, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 56890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 56890 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 56890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 56890 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2350 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5689 -instret:2351 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5689 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001308, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 56900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56900 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004021008ffff1ffff805821008 - 56900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080001380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2352 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5690 -instret:2353 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5690 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000018400000001fffff44000000 - 56910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 56910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 56910 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2354 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5691 -instret:2355 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5691 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 00000000000000c2000000001fffff44000000 - 56920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 56920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56920 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 56920 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001310 -After delta: vaddr = 0x80001310 - 56920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200004c41310ffff1ffff805821008 -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 - 56930 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 56930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001310, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 1000000000000000040000001fffff44000000 - 56940 : [doFinishMem] DTlbResp { resp: <'h0000000080001310,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001310 o: 'h0000000000000308 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001310, check_high: 'h00000000080001318, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 56940 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000800000001fffff44000000 - 56940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 56950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56960 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000800000001fffff44000000 - 56960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 56960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 56970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 56970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 56970 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 56970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 64 <= 0000000000000018000000001fffff44000000 - 56980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 56980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56980 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000400000001fffff44000000 - 56980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 56980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 56980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 56990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 56990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 56990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 56990 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 56990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 56990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 56990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 57000 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 - 57000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57000 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2356 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5700 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 57010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 57010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57010 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 57010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2357 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5701 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000018800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 57020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57020 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2358 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5702 -instret:2359 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5702 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 00000000000000c4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 57030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57030 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57030 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001318 -After delta: vaddr = 0x80001318 - 57030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2360 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5703 -instret:2361 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5703 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 40000000200004c61318ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57040 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 57040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001318 o: 'h0000000000000310 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001318 o: 'h0000000000000310 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001318, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2362 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5704 -instret:2363 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5704 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000000400000001fffff44000000 - 57050 : [doFinishMem] DTlbResp { resp: <'h0000000080001318,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001318 o: 'h0000000000000310 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001318, check_high: 'h00000000080001320, check_inclusive: True } }, specBits: 'h004 } - 57050 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000000c00000001fffff44000000 - 57050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2364 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5705 -instret:2365 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5705 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 57060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2366 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5706 -instret:2367 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5706 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57070 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000c00000001fffff44000000 - 57070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2368 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5707 -instret:2369 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5707 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 57080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2370 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5708 -instret:2371 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5708 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 55 <= 0000000000000018000000001fffff44000000 - 57090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001310, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2372 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5709 -instret:2373 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5709 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000001000000001fffff44000000 - 57100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 57100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57100 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2374 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5710 -instret:2375 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5710 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 57110 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 57110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57110 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 57120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 57120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57120 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200004021008ffff1ffff805821008 - 57120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000018c00000001fffff44000000 - 57130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57130 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 00000000000000c6000000001fffff44000000 - 57140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 57140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57140 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57140 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001320 -After delta: vaddr = 0x80001320 - 57140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 7b <= 40000000200004c81320ffff1ffff805821008 - 57150 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 57150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001320 o: 'h0000000000000318 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001320 o: 'h0000000000000318 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001320, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 - 57160 : [doFinishMem] DTlbResp { resp: <'h0000000080001320,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001320 o: 'h0000000000000318 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001320, check_high: 'h00000000080001328, check_inclusive: True } }, specBits: 'h00c } - 57160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57160 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001000000001fffff44000000 - 57160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 57170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57170 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57180 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000800000001fffff44000000 - 57180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 57190 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000001000000001fffff44000000 - 57190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 42 <= 0000000000000018000000001fffff44000000 - 57200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 57200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2376 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5720 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57210 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2377 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5721 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57220 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 57220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2378 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5722 -instret:2379 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5722 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 57230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2380 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5723 -instret:2381 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5723 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000019000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2382 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5724 -instret:2383 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5724 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 00000000000000c8000000001fffff44000000 - 57250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 57250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001328 -After delta: vaddr = 0x80001328 - 57250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2384 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5725 -instret:2385 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5725 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 40000000200004ca1328ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 57260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001328 o: 'h0000000000000320 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001328 o: 'h0000000000000320 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001328, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57260 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2386 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5726 -instret:2387 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5726 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57270 : [doFinishMem] DTlbResp { resp: <'h0000000080001328,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001328 o: 'h0000000000000320 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001328, check_high: 'h00000000080001330, check_inclusive: True } }, specBits: 'h018 } - 57270 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4b <= 40000000200004021008ffff1ffff805821008 - 57270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57270 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2388 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5727 -instret:2389 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5727 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 57280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57280 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002000000001fffff44000000 - 57280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2390 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5728 -instret:2391 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5728 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001318, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57290 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2392 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5729 -instret:2393 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5729 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 - 57300 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2394 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5730 -instret:2395 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5730 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57310 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000001400000001fffff44000000 - 57310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 57320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57330 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001400000001fffff44000000 - 57330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 57340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 57340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57340 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5d <= 0000000000000018000000001fffff44000000 - 57350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 57350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57350 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 - 57350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57360 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 57370 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 -instret:2396 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5737 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2397 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5738 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000019400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2398 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5739 -instret:2399 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5739 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 00000000000000ca000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001330 -After delta: vaddr = 0x80001330 - 57400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2400 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5740 -instret:2401 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5740 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 40000000200004cc1330ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001330 o: 'h0000000000000328 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001330 o: 'h0000000000000328 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001330, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2402 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5741 -instret:2403 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5741 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57420 : [doFinishMem] DTlbResp { resp: <'h0000000080001330,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001330 o: 'h0000000000000328 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001330, check_high: 'h00000000080001338, check_inclusive: True } }, specBits: 'h030 } - 57420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2404 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5742 -instret:2405 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5742 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 57430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2406 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5743 -instret:2407 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5743 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 57440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57440 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 57440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2408 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5744 -instret:2409 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5744 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 57450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57450 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200004021008ffff1ffff805821008 - 57450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57450 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2410 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5745 -instret:2411 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5745 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001320, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57460 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002000000001fffff44000000 - 57460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57460 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 57460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2412 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5746 -instret:2413 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5746 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000000400000001fffff44000000 - 57470 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 57470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2414 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5747 -instret:2415 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5747 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57480 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001800000001fffff44000000 - 57480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 57490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 57490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57500 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001800000001fffff44000000 - 57500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 57510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 57510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57510 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5b <= 0000000000000018000000001fffff44000000 - 57520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 57520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57520 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001000000001fffff44000000 - 57520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57530 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 57540 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 -instret:2416 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5754 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2417 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5755 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000019800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2418 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5756 -instret:2419 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5756 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 00000000000000cc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001338 -After delta: vaddr = 0x80001338 - 57570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2420 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5757 -instret:2421 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5757 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 40000000200004ce1338ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001338 o: 'h0000000000000330 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001338 o: 'h0000000000000330 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001338, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2422 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5758 -instret:2423 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5758 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57590 : [doFinishMem] DTlbResp { resp: <'h0000000080001338,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001338 o: 'h0000000000000330 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001338, check_high: 'h00000000080001340, check_inclusive: True } }, specBits: 'h024 } - 57590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2424 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5759 -instret:2425 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5759 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 57600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2426 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5760 -instret:2427 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5760 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 57610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57610 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 57610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2428 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5761 -instret:2429 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5761 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 57620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57620 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 59 <= 40000000200004021008ffff1ffff805821008 - 57620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57620 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 57620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2430 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5762 -instret:2431 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5762 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001328, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57630 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002000000001fffff44000000 - 57630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57630 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 57630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2432 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5763 -instret:2433 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5763 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 57640 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 57640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2434 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5764 -instret:2435 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5764 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57650 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001c00000001fffff44000000 - 57650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 57660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 57660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57670 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57670 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001c00000001fffff44000000 - 57670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3597 calling cycle - 57680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 57680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57680 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 57680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 02 <= 0000000000000018000000001fffff44000000 - 57690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 57690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57690 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 57690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57700 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 57700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 57710 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 -instret:2436 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5771 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2437 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5772 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000019c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2438 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5773 -instret:2439 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5773 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 00000000000000ce000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001340 -After delta: vaddr = 0x80001340 - 57740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2440 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5774 -instret:2441 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5774 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 40000000200004d01340ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001340 o: 'h0000000000000338 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001340 o: 'h0000000000000338 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001340, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2442 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5775 -instret:2443 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5775 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57760 : [doFinishMem] DTlbResp { resp: <'h0000000080001340,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001340 o: 'h0000000000000338 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001340, check_high: 'h00000000080001348, check_inclusive: True } }, specBits: 'h00c } - 57760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2444 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5776 -instret:2445 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5776 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 57770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2446 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5777 -instret:2447 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5777 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 57780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57780 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 57780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2448 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5778 -instret:2449 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5778 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 57790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57790 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 57790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57790 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 57790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2450 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5779 -instret:2451 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5779 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001330, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57800 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002000000001fffff44000000 - 57800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57800 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 57800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2452 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5780 -instret:2453 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5780 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000000400000001fffff44000000 - 57810 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 57810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2454 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5781 -instret:2455 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5781 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57820 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 57820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 57830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 57830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57840 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57840 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 57840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 57850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 57850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 57850 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 57850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 50 <= 0000000000000018000000001fffff44000000 - 57860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 57860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57860 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000001800000001fffff44000000 - 57860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 57870 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 57870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 57880 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003000000001fffff44000000 -instret:2456 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5788 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2457 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5789 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 000000000000001a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2458 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5790 -instret:2459 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5790 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 00000000000000d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001348 -After delta: vaddr = 0x80001348 - 57910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2460 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5791 -instret:2461 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5791 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200004d21348ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001348 o: 'h0000000000000340 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001348 o: 'h0000000000000340 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001348, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 57920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2462 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5792 -instret:2463 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5792 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57930 : [doFinishMem] DTlbResp { resp: <'h0000000080001348,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001348 o: 'h0000000000000340 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001348, check_high: 'h00000000080001350, check_inclusive: True } }, specBits: 'h018 } - 57930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 57930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 57930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2464 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5793 -instret:2465 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5793 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 57940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 57940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 57940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2466 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5794 -instret:2467 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5794 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 57950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 57950 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 57950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2468 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5795 -instret:2469 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5795 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 57960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 57960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 57960 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 57960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 57960 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2470 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5796 -instret:2471 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5796 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 57970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001338, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 57970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 57970 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 57970 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2472 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5797 -instret:2473 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5797 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000000400000001fffff44000000 - 57980 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 57980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2474 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5798 -instret:2475 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5798 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 57990 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002400000001fffff44000000 - 57990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 57990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 57990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58010 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58010 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 58010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58020 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7f <= 0000000000000018000000001fffff44000000 - 58030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 58030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58030 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001c00000001fffff44000000 - 58030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58040 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58050 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 -instret:2476 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5805 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2477 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5806 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 000000000000001a400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2478 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5807 -instret:2479 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5807 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 00000000000000d2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001350 -After delta: vaddr = 0x80001350 - 58080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2480 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5808 -instret:2481 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5808 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 40000000200004d41350ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001350 o: 'h0000000000000348 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001350 o: 'h0000000000000348 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001350, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 58090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2482 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5809 -instret:2483 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5809 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58100 : [doFinishMem] DTlbResp { resp: <'h0000000080001350,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001350 o: 'h0000000000000348 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001350, check_high: 'h00000000080001358, check_inclusive: True } }, specBits: 'h030 } - 58100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 58100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 58100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2484 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5810 -instret:2485 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5810 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 58110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2486 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5811 -instret:2487 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5811 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 58120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58120 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2488 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5812 -instret:2489 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5812 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 58130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 58130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58130 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200004021008ffff1ffff805821008 - 58130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58130 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2490 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5813 -instret:2491 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5813 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001340, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 58140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58140 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58140 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2492 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5814 -instret:2493 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5814 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 - 58150 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2494 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5815 -instret:2495 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5815 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 58160 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002800000001fffff44000000 - 58160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800013c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58180 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58180 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002800000001fffff44000000 - 58180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800013c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 58180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 58180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58190 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 58190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58200 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800013c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800013c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 66 <= 0000000000000018000000001fffff44000000 - 58200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 58200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58200 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002000000001fffff44000000 - 58200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58210 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 58210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58220 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 -instret:2496 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5822 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2497 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5823 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 000000000000001a800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2498 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5824 -instret:2499 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5824 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 00000000000000d4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001358 -After delta: vaddr = 0x80001358 - 58250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2500 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5825 -instret:2501 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5825 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 40000000200004d61358ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001358 o: 'h0000000000000350 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001358 o: 'h0000000000000350 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001358, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 58260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2502 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5826 -instret:2503 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5826 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58270 : [doFinishMem] DTlbResp { resp: <'h0000000080001358,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001358 o: 'h0000000000000350 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001358, check_high: 'h00000000080001360, check_inclusive: True } }, specBits: 'h024 } - 58270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 58270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 58270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2504 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5827 -instret:2505 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5827 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 58280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2506 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5828 -instret:2507 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5828 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 58290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58290 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 58290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2508 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5829 -instret:2509 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5829 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 58300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 58300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58300 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 58300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58300 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2510 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5830 -instret:2511 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5830 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001348, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 58310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58310 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58310 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2512 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5831 -instret:2513 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5831 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 - 58320 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2514 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5832 -instret:2515 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5832 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 58330 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002c00000001fffff44000000 - 58330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 58340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58350 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002c00000001fffff44000000 - 58350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 58360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58360 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 61 <= 0000000000000018000000001fffff44000000 - 58370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 58370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58370 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000002400000001fffff44000000 - 58370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58380 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 58390 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 -instret:2516 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5839 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2517 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5840 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 000000000000001ac00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2518 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5841 -instret:2519 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5841 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 00000000000000d6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001360 -After delta: vaddr = 0x80001360 - 58420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2520 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5842 -instret:2521 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5842 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 40000000200004d81360ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001360 o: 'h0000000000000358 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001360 o: 'h0000000000000358 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001360, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 58430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2522 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5843 -instret:2523 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5843 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58440 : [doFinishMem] DTlbResp { resp: <'h0000000080001360,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001360 o: 'h0000000000000358 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001360, check_high: 'h00000000080001368, check_inclusive: True } }, specBits: 'h00c } - 58440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 58440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 58440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2524 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5844 -instret:2525 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5844 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 58450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2526 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5845 -instret:2527 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5845 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 58460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58460 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2528 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5846 -instret:2529 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5846 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 58470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 58470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58470 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 58470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58470 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 58470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2530 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5847 -instret:2531 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5847 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001350, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 58480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58480 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002000000001fffff44000000 - 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58480 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2532 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5848 -instret:2533 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5848 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 58490 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 58490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 58490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2534 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5849 -instret:2535 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5849 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 58500 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 58500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 58510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58520 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 58520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 58530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58530 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 58530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000018000000001fffff44000000 - 58540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 58540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58540 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 58540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58550 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 58550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 58560 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 -instret:2536 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5856 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2537 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5857 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 000000000000001b000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2538 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5858 -instret:2539 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5858 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 00000000000000d8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001368 -After delta: vaddr = 0x80001368 - 58590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2540 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5859 -instret:2541 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5859 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 40000000200004da1368ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001368, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 58600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2542 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5860 -instret:2543 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5860 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58610 : [doFinishMem] DTlbResp { resp: <'h0000000080001368,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001368, check_high: 'h00000000080001370, check_inclusive: True } }, specBits: 'h018 } - 58610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 58610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 58610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2544 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5861 -instret:2545 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5861 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 58620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2546 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5862 -instret:2547 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5862 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 58630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58630 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2548 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5863 -instret:2549 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5863 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 58640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 58640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58640 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200004021008ffff1ffff805821008 - 58640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58640 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2550 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5864 -instret:2551 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5864 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001358, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 58650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58650 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002000000001fffff44000000 - 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58650 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2552 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5865 -instret:2553 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5865 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000000400000001fffff44000000 - 58660 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 - 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2554 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5866 -instret:2555 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5866 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 58670 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003400000001fffff44000000 - 58670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58680 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800013c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 58680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58690 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58690 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003400000001fffff44000000 - 58690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 58690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800013c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 58690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58700 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 58700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 43 <= 0000000000000018000000001fffff44000000 - 58710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 58710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58710 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002c00000001fffff44000000 - 58710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58720 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 58720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 58730 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 -instret:2556 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5873 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2557 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5874 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 000000000000001b400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2558 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5875 -instret:2559 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5875 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 00000000000000da000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001370 -After delta: vaddr = 0x80001370 - 58760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2560 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5876 -instret:2561 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5876 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 40000000200004dc1370ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001370, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 58770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2562 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5877 -instret:2563 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5877 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58780 : [doFinishMem] DTlbResp { resp: <'h0000000080001370,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001370, check_high: 'h00000000080001378, check_inclusive: True } }, specBits: 'h030 } - 58780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 58780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 58780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2564 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5878 -instret:2565 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5878 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 58790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2566 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5879 -instret:2567 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5879 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 58800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 58800 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2568 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5880 -instret:2569 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5880 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 58810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 58810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58810 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 69 <= 40000000200004021008ffff1ffff805821008 - 58810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 58810 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 58810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2570 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5881 -instret:2571 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5881 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001360, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 58820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58820 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002000000001fffff44000000 - 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 58820 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2572 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5882 -instret:2573 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5882 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000000400000001fffff44000000 - 58830 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 - 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2574 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5883 -instret:2575 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5883 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 58840 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003800000001fffff44000000 - 58840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 58840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 58860 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58860 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003800000001fffff44000000 - 58860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 58860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 58870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 58870 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 58870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 47 <= 0000000000000018000000001fffff44000000 - 58880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 58880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 58880 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 58880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 58880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 58890 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 58900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 58900 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 -instret:2576 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5890 +instret:566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3606 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:2577 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5891 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:2578 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5893 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3615 calling cycle - 59000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 59010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 59020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 59030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 59030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:2579 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 5903 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 59040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 59040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 59040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:2580 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 5904 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 59050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002000000001fffff44000000 - 59050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 59060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000000000000001fffff44000000 - 59070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 59070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 59070 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 59070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2581 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5907 -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000002400000001fffff44000000 - 59080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 59080 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 59080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 59090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 59090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:2582 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 5909 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 59100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2583 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 5910 -instret:2584 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 5910 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 59110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59120 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 59130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59130 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 59130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 59140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 59140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59140 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 59150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 59150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59150 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 59150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 59150 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 59160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 59160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59160 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002400000001fffff44000000 - 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59160 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59170 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59170 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59170 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59180 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 59180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2585 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 5918 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59190 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 - 59190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2586 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 5919 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 1000000000000000040000001fffff44000000 - 59200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 59200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2587 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5920 -instret:2588 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5920 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59210 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 - 59210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2589 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 5921 -instret:2590 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 5921 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 59220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:2591 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 5922 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 40 <= 000000000000001b000000001fffff44000000 - 59230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 59230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000400000001fffff44000000 - 59240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 59240 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59240 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 59250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 59250 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59250 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 59250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59250 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 59260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59260 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 - 59260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59260 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 000000000000001b000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 59270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59270 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 02 <= 40000000200004021008ffff1ffff805821008 - 59270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59270 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 00000000000000d8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 59280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59280 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002400000001fffff44000000 - 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59280 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001368 -After delta: vaddr = 0x80001368 - 59280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2592 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5928 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 40000000200004da1368ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 59290 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 59290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001368, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2593 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5929 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59300 : [doFinishMem] DTlbResp { resp: <'h0000000080001368,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001368 o: 'h0000000000000360 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001368, check_high: 'h00000000080001370, check_inclusive: True } }, specBits: 'h000 } - 59300 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 59300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2594 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5930 -instret:2595 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5930 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 59310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2596 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5931 -instret:2597 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5931 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59320 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000400000001fffff44000000 - 59320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2598 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5932 -instret:2599 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5932 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 59330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2600 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5933 -instret:2601 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5933 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 78 <= 000000000000001b000000001fffff44000000 - 59340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 59340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2602 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5934 -instret:2603 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5934 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000000800000001fffff44000000 - 59350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 59350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59350 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2604 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5935 -instret:2605 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5935 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 59360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 59360 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 59360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59360 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 59360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2606 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5936 -instret:2607 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5936 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001368, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 59370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59370 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200004021008ffff1ffff805821008 - 59370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2608 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5937 -instret:2609 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5937 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 000000000000001b400000001fffff44000000 - 59380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 59380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59380 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 59380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2610 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5938 -instret:2611 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 00000000000000da000000001fffff44000000 - 59390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 59390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59390 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002400000001fffff44000000 - 59390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59390 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 59390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001370 -After delta: vaddr = 0x80001370 - 59390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200004dc1370ffff1ffff805821008 -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 - 59400 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 59400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001370, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 59400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 1000000000000000040000001fffff44000000 - 59410 : [doFinishMem] DTlbResp { resp: <'h0000000080001370,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001370 o: 'h0000000000000368 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001370, check_high: 'h00000000080001378, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 59410 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000000800000001fffff44000000 - 59410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 59420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59430 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59430 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000800000001fffff44000000 - 59430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 59440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59440 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5a <= 000000000000001b000000001fffff44000000 - 59450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 59450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59450 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 - 59450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 59460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59460 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 59470 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003000000001fffff44000000 - 59470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59470 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2612 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5947 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 59480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 59480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59480 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 59480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2613 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5948 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 000000000000001b800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 59490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59490 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2614 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5949 -instret:2615 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5949 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 00000000000000dc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 59500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59500 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002400000001fffff44000000 - 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59500 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001378 -After delta: vaddr = 0x80001378 - 59500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2616 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5950 -instret:2617 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5950 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 40000000200004de1378ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59510 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 - 59510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001378 o: 'h0000000000000370 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001378 o: 'h0000000000000370 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001378, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2618 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5951 -instret:2619 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5951 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 0000000000000000400000001fffff44000000 - 59520 : [doFinishMem] DTlbResp { resp: <'h0000000080001378,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001378 o: 'h0000000000000370 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001378, check_high: 'h00000000080001380, check_inclusive: True } }, specBits: 'h004 } - 59520 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000c00000001fffff44000000 - 59520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2620 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5952 -instret:2621 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5952 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 59530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2622 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5953 -instret:2623 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5953 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59540 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000c00000001fffff44000000 - 59540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2624 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5954 -instret:2625 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5954 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 59550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2626 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5955 -instret:2627 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5955 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 49 <= 000000000000001b000000001fffff44000000 - 59560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001370, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 59560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2628 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5956 -instret:2629 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5956 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000001000000001fffff44000000 - 59570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 59570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59570 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2630 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5957 -instret:2631 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5957 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 59580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 59580 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 59580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59580 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 59580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 59590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 59590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59590 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 66 <= 40000000200004021008ffff1ffff805821008 - 59590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 59590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 000000000000001bc00000001fffff44000000 - 59600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 59600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59600 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 59600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 00000000000000de000000001fffff44000000 - 59610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 59610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59610 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002400000001fffff44000000 - 59610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59610 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 59610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001380 -After delta: vaddr = 0x80001380 - 59610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 75 <= 40000000200004e01380ffff1ffff805821008 - 59620 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 59620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001380 o: 'h0000000000000378 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001380 o: 'h0000000000000378 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001380, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 59620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 1000000000000000040000001fffff44000000 - 59630 : [doFinishMem] DTlbResp { resp: <'h0000000080001380,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001380 o: 'h0000000000000378 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001380, check_high: 'h00000000080001388, check_inclusive: True } }, specBits: 'h00c } - 59630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59630 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001000000001fffff44000000 - 59630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 59640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59640 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59650 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 - 59650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 59660 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000001000000001fffff44000000 - 59660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 7a <= 000000000000001b000000001fffff44000000 - 59670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 59670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2632 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5967 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 59680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59680 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 59680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2633 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5968 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59690 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 59690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2634 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5969 -instret:2635 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5969 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 59700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2636 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5970 -instret:2637 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5970 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 000000000000001c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2638 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5971 -instret:2639 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5971 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 00000000000000e0000000001fffff44000000 - 59720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 59720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001388 -After delta: vaddr = 0x80001388 - 59720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2640 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5972 -instret:2641 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5972 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 40000000200004e21388ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 59730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001388 o: 'h0000000000000380 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001388 o: 'h0000000000000380 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001388, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59730 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2642 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5973 -instret:2643 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5973 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59740 : [doFinishMem] DTlbResp { resp: <'h0000000080001388,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001388 o: 'h0000000000000380 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001388, check_high: 'h00000000080001390, check_inclusive: True } }, specBits: 'h018 } - 59740 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 40000000200004021008ffff1ffff805821008 - 59740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59740 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 59740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2644 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5974 -instret:2645 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5974 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 59750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 59750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59750 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002400000001fffff44000000 - 59750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2646 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5975 -instret:2647 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5975 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001378, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 59760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59760 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2648 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5976 -instret:2649 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5976 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000000400000001fffff44000000 - 59770 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 - 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2650 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5977 -instret:2651 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5977 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 59780 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001400000001fffff44000000 - 59780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 59790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59800 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59800 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001400000001fffff44000000 - 59800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 59810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 59810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59810 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6e <= 000000000000001b000000001fffff44000000 - 59820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 59820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59820 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000c00000001fffff44000000 - 59820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 59830 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 59840 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 -instret:2652 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5984 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2653 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 5985 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 000000000000001c400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2654 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 5986 -instret:2655 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 5986 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 00000000000000e2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001390 -After delta: vaddr = 0x80001390 - 59870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2656 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 5987 -instret:2657 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 5987 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 40000000200004e41390ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001390 o: 'h0000000000000388 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001390 o: 'h0000000000000388 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001390, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 59880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2658 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 5988 -instret:2659 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 5988 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59890 : [doFinishMem] DTlbResp { resp: <'h0000000080001390,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001390 o: 'h0000000000000388 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001390, check_high: 'h00000000080001398, check_inclusive: True } }, specBits: 'h030 } - 59890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 59890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 59890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2660 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 5989 -instret:2661 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 5989 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 59900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 59900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2662 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 5990 -instret:2663 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 5990 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 59910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 59910 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2664 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 5991 -instret:2665 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 5991 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 59920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 59920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59920 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6f <= 40000000200004021008ffff1ffff805821008 - 59920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 59920 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 59920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2666 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 5992 -instret:2667 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 5992 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001380, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 59930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59930 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002400000001fffff44000000 - 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 59930 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2668 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 5993 -instret:2669 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 5993 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000000400000001fffff44000000 - 59940 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 59940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 59940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2670 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 5994 -instret:2671 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 5994 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 59950 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001800000001fffff44000000 - 59950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 59960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 59960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 59960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 59960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 59960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59970 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59970 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001800000001fffff44000000 - 59970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 59970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 59970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 59970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 59980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 59980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 59980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 59980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 59980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 59980 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 59980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 59980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 59990 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001400, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 5c <= 000000000000001b000000001fffff44000000 - 59990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 59990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 59990 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001000000001fffff44000000 - 59990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 59990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60000 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 60000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 60010 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 -instret:2672 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6001 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2673 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6002 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 000000000000001c800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2674 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6003 -instret:2675 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6003 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 00000000000000e4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001398 -After delta: vaddr = 0x80001398 - 60040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2676 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6004 -instret:2677 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6004 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200004e61398ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001398 o: 'h0000000000000390 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001398 o: 'h0000000000000390 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001398, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2678 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6005 -instret:2679 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6005 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60060 : [doFinishMem] DTlbResp { resp: <'h0000000080001398,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001398 o: 'h0000000000000390 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001398, check_high: 'h000000000800013a0, check_inclusive: True } }, specBits: 'h024 } - 60060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2680 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6006 -instret:2681 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6006 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 60070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2682 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6007 -instret:2683 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6007 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 60080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60080 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2684 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6008 -instret:2685 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6008 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 60090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60090 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200004021008ffff1ffff805821008 - 60090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60090 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2686 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6009 -instret:2687 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6009 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001388, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60100 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60100 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2688 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6010 -instret:2689 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6010 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000000400000001fffff44000000 - 60110 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2690 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6011 -instret:2691 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6011 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60120 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001c00000001fffff44000000 - 60120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60140 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 60140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 60150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60150 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 000000000000001b000000001fffff44000000 - 60160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 60160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60160 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001400000001fffff44000000 - 60160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60170 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 60170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60180 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 -instret:2692 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6018 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2693 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6019 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 000000000000001cc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2694 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6020 -instret:2695 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6020 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 00000000000000e6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013a0 -After delta: vaddr = 0x800013a0 - 60210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2696 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6021 -instret:2697 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6021 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200004e813a0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800013a0 o: 'h0000000000000398 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013a0 o: 'h0000000000000398 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2698 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6022 -instret:2699 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6022 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60230 : [doFinishMem] DTlbResp { resp: <'h00000000800013a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013a0 o: 'h0000000000000398 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013a0, check_high: 'h000000000800013a8, check_inclusive: True } }, specBits: 'h00c } - 60230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2700 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6023 -instret:2701 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6023 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 60240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2702 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6024 -instret:2703 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6024 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 60250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60250 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 60250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2704 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6025 -instret:2705 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6025 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 60260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60260 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 60260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60260 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 60260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2706 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6026 -instret:2707 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6026 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001390, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60270 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002400000001fffff44000000 - 60270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60270 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 60270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2708 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6027 -instret:2709 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6027 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000000400000001fffff44000000 - 60280 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 60280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2710 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6028 -instret:2711 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6028 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60290 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 60290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 60300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60310 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002000000001fffff44000000 - 60310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3624 calling cycle - 60320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 60320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60320 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 60320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 000000000000001b000000001fffff44000000 - 60330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 60330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60330 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000001800000001fffff44000000 - 60330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60340 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 60350 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 -instret:2712 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6035 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2713 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6036 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 000000000000001d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2714 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6037 -instret:2715 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6037 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 00000000000000e8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013a8 -After delta: vaddr = 0x800013a8 - 60380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2716 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6038 -instret:2717 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6038 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200004ea13a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800013a8 o: 'h00000000000003a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013a8 o: 'h00000000000003a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2718 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6039 -instret:2719 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6039 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60400 : [doFinishMem] DTlbResp { resp: <'h00000000800013a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013a8 o: 'h00000000000003a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013a8, check_high: 'h000000000800013b0, check_inclusive: True } }, specBits: 'h018 } - 60400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2720 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6040 -instret:2721 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6040 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 60410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2722 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6041 -instret:2723 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6041 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 60420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60420 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2724 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6042 -instret:2725 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6042 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 60430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60430 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 60430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60430 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2726 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6043 -instret:2727 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6043 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001398, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60440 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002400000001fffff44000000 - 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60440 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2728 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6044 -instret:2729 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6044 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000400000001fffff44000000 - 60450 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2730 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6045 -instret:2731 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6045 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60460 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000002400000001fffff44000000 - 60460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60470 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001400, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 60470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 60470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60480 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60480 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002400000001fffff44000000 - 60480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 60490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 60490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60490 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6d <= 000000000000001b000000001fffff44000000 - 60500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 60500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60500 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001c00000001fffff44000000 - 60500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60510 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 60520 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 -instret:2732 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6052 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2733 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6053 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 000000000000001d400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2734 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6054 -instret:2735 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6054 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 00000000000000ea000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013b0 -After delta: vaddr = 0x800013b0 - 60550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2736 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6055 -instret:2737 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6055 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 40000000200004ec13b0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800013b0 o: 'h00000000000003a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013b0 o: 'h00000000000003a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2738 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6056 -instret:2739 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6056 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60570 : [doFinishMem] DTlbResp { resp: <'h00000000800013b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013b0 o: 'h00000000000003a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013b0, check_high: 'h000000000800013b8, check_inclusive: True } }, specBits: 'h030 } - 60570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2740 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6057 -instret:2741 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6057 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 60580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2742 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6058 -instret:2743 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6058 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 60590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60590 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 60590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2744 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6059 -instret:2745 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6059 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 60600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60600 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 01 <= 40000000200004021008ffff1ffff805821008 - 60600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60600 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2746 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6060 -instret:2747 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6060 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60610 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002400000001fffff44000000 - 60610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60610 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 60610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2748 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6061 -instret:2749 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6061 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000400000001fffff44000000 - 60620 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2750 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6062 -instret:2751 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6062 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60630 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 - 60630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 60640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60650 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60650 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 60650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 60660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 60660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60660 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4e <= 000000000000001b000000001fffff44000000 - 60670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 60670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60670 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002000000001fffff44000000 - 60670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60680 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 60690 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003000000001fffff44000000 -instret:2752 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6069 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2753 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6070 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 000000000000001d800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2754 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6071 -instret:2755 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6071 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 00000000000000ec000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013b8 -After delta: vaddr = 0x800013b8 - 60720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2756 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6072 -instret:2757 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6072 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200004ee13b8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800013b8 o: 'h00000000000003b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013b8 o: 'h00000000000003b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2758 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6073 -instret:2759 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6073 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60740 : [doFinishMem] DTlbResp { resp: <'h00000000800013b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013b8 o: 'h00000000000003b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013b8, check_high: 'h000000000800013c0, check_inclusive: True } }, specBits: 'h024 } - 60740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2760 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6074 -instret:2761 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6074 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 60750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2762 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6075 -instret:2763 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6075 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 60760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60760 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2764 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6076 -instret:2765 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6076 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 60770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60770 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 60770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60770 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2766 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6077 -instret:2767 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6077 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60780 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002400000001fffff44000000 - 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60780 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2768 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6078 -instret:2769 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6078 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 60790 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2770 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6079 -instret:2771 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6079 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60800 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002c00000001fffff44000000 - 60800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60820 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60820 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002c00000001fffff44000000 - 60820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 60830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 60830 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 60 <= 000000000000001b000000001fffff44000000 - 60840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 60840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60840 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002400000001fffff44000000 - 60840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 60850 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 60860 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 -instret:2772 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6086 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2773 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6087 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 000000000000001dc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2774 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6088 -instret:2775 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6088 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 00000000000000ee000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013c0 -After delta: vaddr = 0x800013c0 - 60890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2776 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6089 -instret:2777 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6089 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 40000000200004f013c0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800013c0 o: 'h00000000000003b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013c0 o: 'h00000000000003b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 60900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2778 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6090 -instret:2779 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6090 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60910 : [doFinishMem] DTlbResp { resp: <'h00000000800013c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013c0 o: 'h00000000000003b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013c0, check_high: 'h000000000800013c8, check_inclusive: True } }, specBits: 'h00c } - 60910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 60910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 60910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2780 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6091 -instret:2781 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6091 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 60920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 60920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2782 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6092 -instret:2783 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6092 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 60930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 60930 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2784 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6093 -instret:2785 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6093 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 60940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 60940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60940 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 60940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 60940 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 60940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2786 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6094 -instret:2787 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6094 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 60950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60950 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002400000001fffff44000000 - 60950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 60950 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 60950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800013b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2788 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6095 -instret:2789 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6095 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000000400000001fffff44000000 - 60960 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800013b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800013b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2790 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6096 -instret:2791 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6096 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 60970 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 60970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 60970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 60980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 60980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 60980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 60990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 60990 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 60990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 60990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 60990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 61000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 61000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61000 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 61000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000001b000000001fffff44000000 - 61010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 61010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61010 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002800000001fffff44000000 - 61010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61020 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 61030 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 -instret:2792 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6103 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2793 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6104 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 000000000000001e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2794 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6105 -instret:2795 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6105 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 00000000000000f0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013c8 -After delta: vaddr = 0x800013c8 - 61060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2796 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6106 -instret:2797 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6106 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 40000000200004f213c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2798 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6107 -instret:2799 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6107 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61080 : [doFinishMem] DTlbResp { resp: <'h00000000800013c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013c8, check_high: 'h000000000800013d0, check_inclusive: True } }, specBits: 'h018 } - 61080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2800 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6108 -instret:2801 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6108 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 61090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2802 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6109 -instret:2803 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6109 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 61100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61100 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2804 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6110 -instret:2805 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6110 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 61110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 61110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61110 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200004021008ffff1ffff805821008 - 61110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61110 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2806 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6111 -instret:2807 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6111 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 61120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61120 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002400000001fffff44000000 - 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61120 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2808 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6112 -instret:2809 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6112 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000000400000001fffff44000000 - 61130 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 - 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2810 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6113 -instret:2811 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6113 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 61140 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003400000001fffff44000000 - 61140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 61150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61160 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003400000001fffff44000000 - 61160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 61170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 61170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61170 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6b <= 000000000000001b000000001fffff44000000 - 61180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 61180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61180 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002c00000001fffff44000000 - 61180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61190 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 61200 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003000000001fffff44000000 -instret:2812 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6120 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2813 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6121 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 000000000000001e400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2814 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6122 -instret:2815 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6122 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 00000000000000f2000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013d0 -After delta: vaddr = 0x800013d0 - 61230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2816 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6123 -instret:2817 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6123 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200004f413d0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2818 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6124 -instret:2819 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6124 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61250 : [doFinishMem] DTlbResp { resp: <'h00000000800013d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013d0, check_high: 'h000000000800013d8, check_inclusive: True } }, specBits: 'h030 } - 61250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2820 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6125 -instret:2821 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6125 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 61260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2822 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6126 -instret:2823 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6126 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 61270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61270 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2824 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6127 -instret:2825 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6127 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 61280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 61280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61280 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0c <= 40000000200004021008ffff1ffff805821008 - 61280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61280 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 61280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2826 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6128 -instret:2827 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6128 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 61290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61290 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 61290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61290 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 61290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2828 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6129 -instret:2829 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6129 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000000400000001fffff44000000 - 61300 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 61300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 61300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2830 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6130 -instret:2831 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6130 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 61310 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003800000001fffff44000000 - 61310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 61320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61330 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003800000001fffff44000000 - 61330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 61330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 61340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 61340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61340 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61350 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001440, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 4a <= 000000000000001b000000001fffff44000000 - 61350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 61350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61350 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 61350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61360 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 61370 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 -instret:2832 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6137 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:2833 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6138 +instret:569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3633 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:2834 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6140 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 61470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +instret:570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3642 calling cycle - 61480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 61490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 61500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 61500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:2835 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 6150 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 61510 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:2836 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 6151 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 61520 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002400000001fffff44000000 - 61520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 61530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 0000000000000000000000001fffff44000000 - 61540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 61540 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2837 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6154 -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000002800000001fffff44000000 - 61550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 61550 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 61550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 61560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 61560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:2838 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 6156 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 61570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2839 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 6157 -instret:2840 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 6157 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 61580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61590 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 61590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 61600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61600 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 61600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 61610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 61610 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61610 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 61610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 61620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 61620 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61620 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 61620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 61620 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 61630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 61630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61630 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002800000001fffff44000000 - 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61630 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61640 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002800000001fffff44000000 - 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61640 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61650 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 61650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2841 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6165 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61660 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 - 61660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2842 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 6166 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 1000000000000000040000001fffff44000000 - 61670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 61670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2843 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6167 -instret:2844 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6167 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61680 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 - 61680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2845 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 6168 -instret:2846 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 6168 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 61690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:2847 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 6169 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 57 <= 000000000000001e000000001fffff44000000 - 61700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 61700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000000400000001fffff44000000 - 61710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 61710 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61710 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 61720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 61720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61720 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 61720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61720 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 61730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61730 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000000000001fffff44000000 - 61730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61730 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 000000000000001e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 61740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61740 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6c <= 40000000200004021008ffff1ffff805821008 - 61740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61740 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 00000000000000f0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 61750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61750 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61750 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013c8 -After delta: vaddr = 0x800013c8 - 61750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2848 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6175 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 40000000200004f213c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 61760 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 61760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2849 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6176 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61770 : [doFinishMem] DTlbResp { resp: <'h00000000800013c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013c8 o: 'h00000000000003c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013c8, check_high: 'h000000000800013d0, check_inclusive: True } }, specBits: 'h000 } - 61770 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 - 61770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2850 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6177 -instret:2851 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6177 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 61780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2852 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6178 -instret:2853 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6178 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61790 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000400000001fffff44000000 - 61790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2854 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6179 -instret:2855 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6179 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 61800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2856 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6180 -instret:2857 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6180 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 7d <= 000000000000001e000000001fffff44000000 - 61810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 61810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2858 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6181 -instret:2859 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6181 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000000800000001fffff44000000 - 61820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 61820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61820 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 61820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2860 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6182 -instret:2861 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6182 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 61830 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001440, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 61830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 61830 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 61830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61830 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 61830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2862 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6183 -instret:2863 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6183 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 61840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61840 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 61840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61840 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 61840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 61840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2864 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6184 -instret:2865 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6184 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 000000000000001e400000001fffff44000000 - 61850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 61850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61850 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 61850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2866 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6185 -instret:2867 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6185 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 00000000000000f2000000001fffff44000000 - 61860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 61860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61860 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002800000001fffff44000000 - 61860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61860 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 61860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013d0 -After delta: vaddr = 0x800013d0 - 61860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 40000000200004f413d0ffff1ffff805821008 -[RFile] wr_ 1: r 68 <= 0000000000000000400000001fffff44000000 - 61870 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 61870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 61870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 1000000000000000040000001fffff44000000 - 61880 : [doFinishMem] DTlbResp { resp: <'h00000000800013d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013d0 o: 'h00000000000003c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013d0, check_high: 'h000000000800013d8, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 61880 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000800000001fffff44000000 - 61880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 61890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 61890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 61890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61900 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000800000001fffff44000000 - 61900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 61910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 61910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 61910 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 61910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 61910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 69 <= 000000000000001e000000001fffff44000000 - 61920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 61920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61920 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000400000001fffff44000000 - 61920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 61920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 61930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 61930 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 61930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 61930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 61940 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 - 61940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 61940 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 61940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2868 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6194 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 61950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 61950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61950 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 61950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 61950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2869 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6195 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 000000000000001e800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 61960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 61960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 61960 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 61960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 61960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2870 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6196 -instret:2871 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6196 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 00000000000000f4000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 61970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 61970 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002800000001fffff44000000 - 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 61970 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 61970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013d8 -After delta: vaddr = 0x800013d8 - 61970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2872 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6197 -instret:2873 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6197 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200004f613d8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 61980 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003000000001fffff44000000 - 61980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800013d8 o: 'h00000000000003d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013d8 o: 'h00000000000003d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2874 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6198 -instret:2875 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6198 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000000400000001fffff44000000 - 61990 : [doFinishMem] DTlbResp { resp: <'h00000000800013d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013d8 o: 'h00000000000003d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013d8, check_high: 'h000000000800013e0, check_inclusive: True } }, specBits: 'h004 } - 61990 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000c00000001fffff44000000 - 61990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 61990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2876 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6199 -instret:2877 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6199 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 62000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2878 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6200 -instret:2879 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6200 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62010 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000c00000001fffff44000000 - 62010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2880 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6201 -instret:2881 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6201 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 62020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2882 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6202 -instret:2883 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6202 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 56 <= 000000000000001e000000001fffff44000000 - 62030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2884 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6203 -instret:2885 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6203 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 0000000000000001000000001fffff44000000 - 62040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 62040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62040 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2886 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6204 -instret:2887 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6204 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 62050 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 62050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62050 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 62060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 62060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62060 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200004021008ffff1ffff805821008 - 62060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 000000000000001ec00000001fffff44000000 - 62070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62070 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 00000000000000f6000000001fffff44000000 - 62080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 62080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62080 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002800000001fffff44000000 - 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62080 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013e0 -After delta: vaddr = 0x800013e0 - 62080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 6f <= 40000000200004f813e0ffff1ffff805821008 - 62090 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 62090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800013e0 o: 'h00000000000003d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013e0 o: 'h00000000000003d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 1000000000000000040000001fffff44000000 - 62100 : [doFinishMem] DTlbResp { resp: <'h00000000800013e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013e0 o: 'h00000000000003d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013e0, check_high: 'h000000000800013e8, check_inclusive: True } }, specBits: 'h00c } - 62100 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62100 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001000000001fffff44000000 - 62100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 62110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62110 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 62110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62120 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 - 62120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 62130 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001000000001fffff44000000 - 62130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 79 <= 000000000000001e000000001fffff44000000 - 62140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 62140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:2888 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6214 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 62150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62150 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 62150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2889 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6215 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62160 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 62160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2890 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6216 -instret:2891 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6216 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 62170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2892 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6217 -instret:2893 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6217 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 000000000000001f000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2894 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6218 -instret:2895 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6218 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 00000000000000f8000000001fffff44000000 - 62190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 62190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013e8 -After delta: vaddr = 0x800013e8 - 62190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2896 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6219 -instret:2897 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6219 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 40000000200004fa13e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 62200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800013e8 o: 'h00000000000003e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013e8 o: 'h00000000000003e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62200 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 62200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2898 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6220 -instret:2899 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6220 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62210 : [doFinishMem] DTlbResp { resp: <'h00000000800013e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013e8 o: 'h00000000000003e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013e8, check_high: 'h000000000800013f0, check_inclusive: True } }, specBits: 'h018 } - 62210 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 60 <= 40000000200004021008ffff1ffff805821008 - 62210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62210 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 62210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2900 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6221 -instret:2901 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6221 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 62220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62220 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002800000001fffff44000000 - 62220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2902 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6222 -instret:2903 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6222 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62230 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 62230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2904 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6223 -instret:2905 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6223 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 - 62240 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 - 62240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800013d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2906 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6224 -instret:2907 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6224 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62250 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000001400000001fffff44000000 - 62250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62270 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001400000001fffff44000000 - 62270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 62280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62280 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4f <= 000000000000001e000000001fffff44000000 - 62290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 62290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62290 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 - 62290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62300 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62310 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 -instret:2908 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6231 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2909 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6232 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 000000000000001f400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2910 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6233 -instret:2911 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6233 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 00000000000000fa000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013f0 -After delta: vaddr = 0x800013f0 - 62340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2912 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6234 -instret:2913 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6234 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 40000000200004fc13f0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800013f0 o: 'h00000000000003e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013f0 o: 'h00000000000003e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2914 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6235 -instret:2915 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6235 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62360 : [doFinishMem] DTlbResp { resp: <'h00000000800013f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013f0 o: 'h00000000000003e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013f0, check_high: 'h000000000800013f8, check_inclusive: True } }, specBits: 'h030 } - 62360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2916 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6236 -instret:2917 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6236 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 62370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2918 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6237 -instret:2919 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6237 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 62380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62380 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2920 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6238 -instret:2921 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6238 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 62390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62390 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 77 <= 40000000200004021008ffff1ffff805821008 - 62390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62390 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2922 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6239 -instret:2923 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6239 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62400 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002800000001fffff44000000 - 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62400 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2924 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6240 -instret:2925 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6240 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 0000000000000000400000001fffff44000000 - 62410 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800013e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2926 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6241 -instret:2927 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6241 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62420 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000001800000001fffff44000000 - 62420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 62430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62440 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62440 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001800000001fffff44000000 - 62440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 62450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 62450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62450 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 62450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 41 <= 000000000000001e000000001fffff44000000 - 62460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 62460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62460 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001000000001fffff44000000 - 62460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62470 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 62470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 62480 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 -instret:2928 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6248 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2929 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6249 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 000000000000001f800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2930 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6250 -instret:2931 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6250 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 00000000000000fc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800013f8 -After delta: vaddr = 0x800013f8 - 62510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2932 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6251 -instret:2933 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6251 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 40000000200004fe13f8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800013f8 o: 'h00000000000003f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800013f8 o: 'h00000000000003f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800013f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2934 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6252 -instret:2935 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6252 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62530 : [doFinishMem] DTlbResp { resp: <'h00000000800013f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800013f8 o: 'h00000000000003f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800013f8, check_high: 'h00000000080001400, check_inclusive: True } }, specBits: 'h024 } - 62530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2936 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6253 -instret:2937 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6253 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 62540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2938 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6254 -instret:2939 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6254 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 62550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62550 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 62550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2940 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6255 -instret:2941 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6255 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 62560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62560 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 49 <= 40000000200004021008ffff1ffff805821008 - 62560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62560 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2942 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6256 -instret:2943 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6256 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62570 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002800000001fffff44000000 - 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62570 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2944 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6257 -instret:2945 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6257 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000000400000001fffff44000000 - 62580 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 62580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800013e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2946 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6258 -instret:2947 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6258 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62590 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 62590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 62600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62610 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62610 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001c00000001fffff44000000 - 62610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 62620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 62620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62620 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 51 <= 000000000000001e000000001fffff44000000 - 62630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 62630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62630 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 62630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62640 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 62650 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 -instret:2948 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6265 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2949 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6266 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 000000000000001fc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2950 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6267 -instret:2951 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6267 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 00000000000000fe000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001400 -After delta: vaddr = 0x80001400 - 62680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2952 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6268 -instret:2953 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6268 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 40000000200005001400ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001400 o: 'h00000000000003f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001400 o: 'h00000000000003f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001400, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2954 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6269 -instret:2955 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6269 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62700 : [doFinishMem] DTlbResp { resp: <'h0000000080001400,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001400 o: 'h00000000000003f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001400, check_high: 'h00000000080001408, check_inclusive: True } }, specBits: 'h00c } - 62700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2956 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6270 -instret:2957 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6270 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 62710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2958 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6271 -instret:2959 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6271 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 62720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62720 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 62720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2960 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6272 -instret:2961 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6272 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 62730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62730 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 62730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62730 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 62730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2962 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6273 -instret:2963 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6273 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62740 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 62740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62740 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 62740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2964 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6274 -instret:2965 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6274 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000000400000001fffff44000000 - 62750 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 62750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800013f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2966 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6275 -instret:2967 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6275 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62760 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002000000001fffff44000000 - 62760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 62770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62780 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 62780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 62790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 62790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62790 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 62790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 72 <= 000000000000001e000000001fffff44000000 - 62800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 62800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62800 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001800000001fffff44000000 - 62800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62810 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 62810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 62820 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 -instret:2968 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6282 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2969 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6283 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000020000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2970 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6284 -instret:2971 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6284 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000100000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001408 -After delta: vaddr = 0x80001408 - 62850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2972 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6285 -instret:2973 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6285 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 40000000200005021408ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001408 o: 'h0000000000000400 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001408 o: 'h0000000000000400 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001408, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 62860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2974 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6286 -instret:2975 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6286 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62870 : [doFinishMem] DTlbResp { resp: <'h0000000080001408,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001408 o: 'h0000000000000400 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001408, check_high: 'h00000000080001410, check_inclusive: True } }, specBits: 'h018 } - 62870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 62870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 62870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2976 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6287 -instret:2977 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6287 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 62880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2978 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6288 -instret:2979 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6288 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 62890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 62890 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:2980 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6289 -instret:2981 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6289 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 62900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 62900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62900 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 62900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 62900 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:2982 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6290 -instret:2983 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6290 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800013f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 62910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62910 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002800000001fffff44000000 - 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 62910 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800013f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:2984 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6291 -instret:2985 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6291 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 62920 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 - 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800013f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800013f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:2986 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6292 -instret:2987 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6292 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 62930 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002400000001fffff44000000 - 62930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 62930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 62950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62950 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002400000001fffff44000000 - 62950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 62950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3651 calling cycle - 62960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 62960 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 62960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 000000000000001e000000001fffff44000000 - 62970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 62970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 62970 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001c00000001fffff44000000 - 62970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 62970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 44 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 62980 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 62990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 62990 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 -instret:2988 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6299 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:2989 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6300 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000020400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2990 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6301 -instret:2991 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6301 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000102000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001410 -After delta: vaddr = 0x80001410 - 63020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2992 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6302 -instret:2993 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6302 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200005041410ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001410 o: 'h0000000000000408 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001410 o: 'h0000000000000408 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001410, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 63030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2994 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6303 -instret:2995 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6303 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63040 : [doFinishMem] DTlbResp { resp: <'h0000000080001410,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001410 o: 'h0000000000000408 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001410, check_high: 'h00000000080001418, check_inclusive: True } }, specBits: 'h030 } - 63040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 63040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:2996 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6304 -instret:2997 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6304 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 63050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:2998 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6305 -instret:2999 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6305 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 63060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63060 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 63060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3000 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6306 -instret:3001 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6306 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 63070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 63070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63070 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 05 <= 40000000200004021008ffff1ffff805821008 - 63070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63070 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 63070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3002 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6307 -instret:3003 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6307 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001400, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 63080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63080 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002800000001fffff44000000 - 63080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63080 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 63080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3004 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6308 -instret:3005 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6308 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000000400000001fffff44000000 - 63090 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 63090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 63090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3006 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6309 -instret:3007 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6309 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 63100 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002800000001fffff44000000 - 63100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 63110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63120 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63120 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002800000001fffff44000000 - 63120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 63120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 63120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 63130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63130 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 63130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63140 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001480, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 08 <= 000000000000001e000000001fffff44000000 - 63140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 63140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63140 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002000000001fffff44000000 - 63140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63150 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 63150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63160 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 -instret:3008 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6316 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3009 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6317 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000020800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3010 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6318 -instret:3011 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6318 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000104000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001418 -After delta: vaddr = 0x80001418 - 63190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3012 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6319 -instret:3013 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6319 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 40000000200005061418ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001418 o: 'h0000000000000410 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001418 o: 'h0000000000000410 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001418, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 63200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3014 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6320 -instret:3015 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6320 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63210 : [doFinishMem] DTlbResp { resp: <'h0000000080001418,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001418 o: 'h0000000000000410 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001418, check_high: 'h00000000080001420, check_inclusive: True } }, specBits: 'h024 } - 63210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 63210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3016 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6321 -instret:3017 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6321 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 63220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3018 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6322 -instret:3019 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6322 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 63230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63230 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3020 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6323 -instret:3021 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6323 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 63240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 63240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63240 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200004021008ffff1ffff805821008 - 63240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63240 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3022 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6324 -instret:3023 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6324 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001408, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 63250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63250 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002800000001fffff44000000 - 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63250 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3024 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6325 -instret:3025 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6325 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000000400000001fffff44000000 - 63260 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3026 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6326 -instret:3027 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6326 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 63270 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002c00000001fffff44000000 - 63270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 63280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63290 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63290 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002c00000001fffff44000000 - 63290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 63300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 63300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63300 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 43 <= 000000000000001e000000001fffff44000000 - 63310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 63310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63310 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002400000001fffff44000000 - 63310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63320 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 63330 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 -instret:3028 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6333 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3029 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6334 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000020c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3030 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6335 -instret:3031 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6335 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000106000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001420 -After delta: vaddr = 0x80001420 - 63360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3032 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6336 -instret:3033 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6336 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 40000000200005081420ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001420 o: 'h0000000000000418 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001420 o: 'h0000000000000418 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001420, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 63370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3034 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6337 -instret:3035 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6337 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63380 : [doFinishMem] DTlbResp { resp: <'h0000000080001420,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001420 o: 'h0000000000000418 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001420, check_high: 'h00000000080001428, check_inclusive: True } }, specBits: 'h00c } - 63380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 63380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3036 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6338 -instret:3037 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6338 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 63390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3038 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6339 -instret:3039 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6339 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 63400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63400 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 63400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3040 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6340 -instret:3041 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6340 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 63410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 63410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63410 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200004021008ffff1ffff805821008 - 63410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63410 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 63410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3042 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6341 -instret:3043 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6341 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001410, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 63420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63420 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002800000001fffff44000000 - 63420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63420 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 63420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3044 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6342 -instret:3045 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6342 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000000400000001fffff44000000 - 63430 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 63430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 63430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3046 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6343 -instret:3047 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6343 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 63440 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 63440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 63450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 63450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63460 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 63460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 63470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 63470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63470 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 63470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000001e000000001fffff44000000 - 63480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 63480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63480 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000002800000001fffff44000000 - 63480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63490 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 63500 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 -instret:3048 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6350 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3049 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6351 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000021000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3050 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6352 -instret:3051 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6352 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000000000108000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001428 -After delta: vaddr = 0x80001428 - 63530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3052 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6353 -instret:3053 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6353 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 400000002000050a1428ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001428, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 63540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3054 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6354 -instret:3055 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6354 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63550 : [doFinishMem] DTlbResp { resp: <'h0000000080001428,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001428, check_high: 'h00000000080001430, check_inclusive: True } }, specBits: 'h018 } - 63550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 63550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3056 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6355 -instret:3057 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6355 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 63560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3058 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6356 -instret:3059 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6356 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 63570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63570 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3060 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6357 -instret:3061 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6357 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 63580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 63580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63580 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200004021008ffff1ffff805821008 - 63580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63580 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3062 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6358 -instret:3063 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6358 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001418, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 63590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63590 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002800000001fffff44000000 - 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63590 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3064 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6359 -instret:3065 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6359 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 63600 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3066 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6360 -instret:3067 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6360 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 63610 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003400000001fffff44000000 - 63610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63620 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001480, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 63620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 63620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63630 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003400000001fffff44000000 - 63630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 63640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 63640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63640 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 74 <= 000000000000001e000000001fffff44000000 - 63650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 63650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63650 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002c00000001fffff44000000 - 63650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63660 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 63660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 63670 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 -instret:3068 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6367 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3069 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6368 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000021400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3070 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6369 -instret:3071 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6369 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 000000000000010a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001430 -After delta: vaddr = 0x80001430 - 63700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3072 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6370 -instret:3073 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6370 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 400000002000050c1430ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001430, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 63710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3074 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6371 -instret:3075 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6371 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63720 : [doFinishMem] DTlbResp { resp: <'h0000000080001430,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001430, check_high: 'h00000000080001438, check_inclusive: True } }, specBits: 'h030 } - 63720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 63720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3076 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6372 -instret:3077 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6372 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 63730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3078 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6373 -instret:3079 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6373 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 63740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 63740 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 63740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3080 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6374 -instret:3081 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6374 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 63750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 63750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63750 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 76 <= 40000000200004021008ffff1ffff805821008 - 63750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 63750 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 63750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3082 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6375 -instret:3083 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6375 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001420, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 63760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63760 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002800000001fffff44000000 - 63760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 63760 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 63760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3084 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6376 -instret:3085 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6376 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 - 63770 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 63770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 63770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3086 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6377 -instret:3087 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6377 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 63780 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003800000001fffff44000000 - 63780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 63790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 63790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 63790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63800 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63800 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003800000001fffff44000000 - 63800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 63800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 63810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 63810 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7b <= 000000000000001e000000001fffff44000000 - 63820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 63820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63820 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 63820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 63820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 63830 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 63840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 63840 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 -instret:3088 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6384 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:3089 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6385 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +instret:572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3660 calling cycle -instret:3090 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6387 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 63940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 63950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3669 calling cycle - 63960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 63970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 63970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 63970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 63970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 63970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:3091 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 6397 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 63980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 63980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 63980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 63980 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 63980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 63980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:3092 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 6398 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 63990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 63990 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002800000001fffff44000000 - 63990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 63990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 64000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000000000001fffff44000000 - 64010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 64010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 64010 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 64010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3093 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6401 -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000002c00000001fffff44000000 - 64020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 64020 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 - 64020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 64030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 64030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:3094 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 6403 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 64040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3095 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 6404 -instret:3096 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 6404 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 64050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64060 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 64060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 64070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64070 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 64070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 64070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 64080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 64080 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64080 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 64080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 64090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 64090 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64090 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 64090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 64090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 64090 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 64090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 64100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 64100 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64100 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002c00000001fffff44000000 - 64100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64100 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 64100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64110 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64110 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002c00000001fffff44000000 - 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 64120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3097 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6412 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64130 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000 - 64130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3098 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 6413 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 1000000000000000040000001fffff44000000 - 64140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 64140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3099 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6414 -instret:3100 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6414 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64150 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000000000001fffff44000000 - 64150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3101 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 6415 -instret:3102 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 6415 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 64160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:3103 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 6416 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 78 <= 0000000000000021000000001fffff44000000 - 64170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 64170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000400000001fffff44000000 - 64180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 64180 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64180 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 64190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 64190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64190 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 64190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64190 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 64200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64200 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 64200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64200 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000021000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 64210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64210 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 51 <= 40000000200004021008ffff1ffff805821008 - 64210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64210 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000108000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 64220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64220 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002c00000001fffff44000000 - 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64220 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001428 -After delta: vaddr = 0x80001428 - 64220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3104 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6422 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 400000002000050a1428ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 64230 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 64230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001428, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3105 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6423 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64240 : [doFinishMem] DTlbResp { resp: <'h0000000080001428,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001428 o: 'h0000000000000420 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001428, check_high: 'h00000000080001430, check_inclusive: True } }, specBits: 'h000 } - 64240 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000400000001fffff44000000 - 64240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3106 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6424 -instret:3107 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6424 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 64250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3108 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6425 -instret:3109 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6425 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64260 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000400000001fffff44000000 - 64260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3110 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6426 -instret:3111 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6426 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 64270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3112 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6427 -instret:3113 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6427 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 73 <= 0000000000000021000000001fffff44000000 - 64280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 64280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3114 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6428 -instret:3115 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6428 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 0000000000000000800000001fffff44000000 - 64290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 64290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64290 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 64290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3116 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6429 -instret:3117 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6429 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 64300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 64300 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 64300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64300 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 64300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3118 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6430 -instret:3119 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6430 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001428, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 64310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64310 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 64310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3120 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6431 -instret:3121 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6431 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000021400000001fffff44000000 - 64320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 64320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64320 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 64320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3122 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6432 -instret:3123 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6432 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 000000000000010a000000001fffff44000000 - 64330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 64330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64330 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002c00000001fffff44000000 - 64330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64330 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 64330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001430 -After delta: vaddr = 0x80001430 - 64330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 400000002000050c1430ffff1ffff805821008 -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 - 64340 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 64340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001430, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 64340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 1000000000000000040000001fffff44000000 - 64350 : [doFinishMem] DTlbResp { resp: <'h0000000080001430,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001430 o: 'h0000000000000428 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001430, check_high: 'h00000000080001438, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 64350 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 - 64350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 64360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 64360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64370 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64370 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000800000001fffff44000000 - 64370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 64380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64380 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 64380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0c <= 0000000000000021000000001fffff44000000 - 64390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 64390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64390 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000400000001fffff44000000 - 64390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 64400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64400 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 64400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 64410 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 64410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64410 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 64410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3124 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6441 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 64420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 64420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64420 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 64420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3125 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6442 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000021800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 64430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64430 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3126 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6443 -instret:3127 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6443 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 000000000000010c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 64440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64440 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002c00000001fffff44000000 - 64440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64440 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 64440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001438 -After delta: vaddr = 0x80001438 - 64440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3128 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6444 -instret:3129 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6444 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 400000002000050e1438ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64450 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000003000000001fffff44000000 - 64450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001438 o: 'h0000000000000430 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001438 o: 'h0000000000000430 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001438, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3130 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6445 -instret:3131 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6445 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 0000000000000000400000001fffff44000000 - 64460 : [doFinishMem] DTlbResp { resp: <'h0000000080001438,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001438 o: 'h0000000000000430 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001438, check_high: 'h00000000080001440, check_inclusive: True } }, specBits: 'h004 } - 64460 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000c00000001fffff44000000 - 64460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3132 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6446 -instret:3133 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6446 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 64470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3134 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6447 -instret:3135 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6447 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64480 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000c00000001fffff44000000 - 64480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3136 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6448 -instret:3137 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6448 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 64490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3138 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6449 -instret:3139 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6449 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 0000000000000021000000001fffff44000000 - 64500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001430, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 64500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3140 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6450 -instret:3141 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6450 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000001000000001fffff44000000 - 64510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 64510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64510 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3142 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6451 -instret:3143 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6451 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 64520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 64520 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 64520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64520 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 64530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 64530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64530 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200004021008ffff1ffff805821008 - 64530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000021c00000001fffff44000000 - 64540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 64540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64540 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 000000000000010e000000001fffff44000000 - 64550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 64550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64550 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002c00000001fffff44000000 - 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64550 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001440 -After delta: vaddr = 0x80001440 - 64550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 77 <= 40000000200005101440ffff1ffff805821008 - 64560 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 64560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001440 o: 'h0000000000000438 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001440 o: 'h0000000000000438 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001440, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 - 64570 : [doFinishMem] DTlbResp { resp: <'h0000000080001440,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001440 o: 'h0000000000000438 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001440, check_high: 'h00000000080001448, check_inclusive: True } }, specBits: 'h00c } - 64570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64570 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000001000000001fffff44000000 - 64570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 64580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64580 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 64580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64590 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000800000001fffff44000000 - 64590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 64600 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001000000001fffff44000000 - 64600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 7e <= 0000000000000021000000001fffff44000000 - 64610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 64610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3144 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6461 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 64620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64620 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 64620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3145 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6462 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64630 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 64630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3146 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6463 -instret:3147 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6463 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 64640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3148 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6464 -instret:3149 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6464 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000022000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3150 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6465 -instret:3151 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6465 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000110000000001fffff44000000 - 64660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 64660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001448 -After delta: vaddr = 0x80001448 - 64660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3152 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6466 -instret:3153 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6466 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 40000000200005121448ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 64670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001448 o: 'h0000000000000440 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001448 o: 'h0000000000000440 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001448, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64670 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 64670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3154 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6467 -instret:3155 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6467 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64680 : [doFinishMem] DTlbResp { resp: <'h0000000080001448,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001448 o: 'h0000000000000440 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001448, check_high: 'h00000000080001450, check_inclusive: True } }, specBits: 'h018 } - 64680 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 43 <= 40000000200004021008ffff1ffff805821008 - 64680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64680 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 64680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3156 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6468 -instret:3157 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6468 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 64690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 64690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64690 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002c00000001fffff44000000 - 64690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3158 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6469 -instret:3159 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6469 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001438, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 64700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64700 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 64700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3160 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6470 -instret:3161 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6470 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 64710 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 - 64710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 64710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3162 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6471 -instret:3163 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6471 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 64720 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001400000001fffff44000000 - 64720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 64730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64740 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64740 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001400000001fffff44000000 - 64740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 64750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 64750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64750 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 01 <= 0000000000000021000000001fffff44000000 - 64760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 64760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64760 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000c00000001fffff44000000 - 64760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64770 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 64780 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 -instret:3164 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6478 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3165 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6479 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000022400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3166 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6480 -instret:3167 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6480 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000112000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001450 -After delta: vaddr = 0x80001450 - 64810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3168 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6481 -instret:3169 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6481 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 40000000200005141450ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001450 o: 'h0000000000000448 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001450 o: 'h0000000000000448 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001450, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3170 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6482 -instret:3171 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6482 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64830 : [doFinishMem] DTlbResp { resp: <'h0000000080001450,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001450 o: 'h0000000000000448 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001450, check_high: 'h00000000080001458, check_inclusive: True } }, specBits: 'h030 } - 64830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 64830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 64830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3172 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6483 -instret:3173 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6483 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 64840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3174 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6484 -instret:3175 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6484 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 64850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 64850 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3176 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6485 -instret:3177 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6485 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 64860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 64860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64860 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 47 <= 40000000200004021008ffff1ffff805821008 - 64860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 64860 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3178 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6486 -instret:3179 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6486 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001440, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 64870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64870 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002c00000001fffff44000000 - 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 64870 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3180 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6487 -instret:3181 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6487 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000000400000001fffff44000000 - 64880 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3182 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6488 -instret:3183 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6488 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 64890 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001800000001fffff44000000 - 64890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 64900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 64900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 64900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 64900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 64900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800014c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64910 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001800000001fffff44000000 - 64910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800014c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 64910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 64910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 64910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 64920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 64920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 64920 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 64920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 64920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 64930 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800014c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800014c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 52 <= 0000000000000021000000001fffff44000000 - 64930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 64930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 64930 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001000000001fffff44000000 - 64930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 64930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 64940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 64940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 64940 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 64940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 64950 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 -instret:3184 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6495 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3185 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6496 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000022800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3186 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6497 -instret:3187 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6497 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000114000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001458 -After delta: vaddr = 0x80001458 - 64980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3188 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6498 -instret:3189 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6498 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200005161458ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 64990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001458 o: 'h0000000000000450 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001458 o: 'h0000000000000450 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001458, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 64990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 64990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3190 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6499 -instret:3191 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6499 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65000 : [doFinishMem] DTlbResp { resp: <'h0000000080001458,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001458 o: 'h0000000000000450 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001458, check_high: 'h00000000080001460, check_inclusive: True } }, specBits: 'h024 } - 65000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3192 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6500 -instret:3193 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6500 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 65010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3194 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6501 -instret:3195 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6501 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 65020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65020 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 65020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3196 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6502 -instret:3197 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6502 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 65030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65030 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 56 <= 40000000200004021008ffff1ffff805821008 - 65030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65030 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 65030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3198 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6503 -instret:3199 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6503 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001448, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65040 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002c00000001fffff44000000 - 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65040 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3200 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6504 -instret:3201 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6504 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000000400000001fffff44000000 - 65050 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3202 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6505 -instret:3203 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6505 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65060 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001c00000001fffff44000000 - 65060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65080 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65080 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001c00000001fffff44000000 - 65080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 65090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65090 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4b <= 0000000000000021000000001fffff44000000 - 65100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 65100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65100 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001400000001fffff44000000 - 65100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65110 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65120 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 -instret:3204 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6512 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3205 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6513 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000022c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3206 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6514 -instret:3207 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6514 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000116000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001460 -After delta: vaddr = 0x80001460 - 65150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3208 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6515 -instret:3209 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6515 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 40000000200005181460ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001460 o: 'h0000000000000458 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001460 o: 'h0000000000000458 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001460, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 65160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3210 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6516 -instret:3211 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6516 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65170 : [doFinishMem] DTlbResp { resp: <'h0000000080001460,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001460 o: 'h0000000000000458 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001460, check_high: 'h00000000080001468, check_inclusive: True } }, specBits: 'h00c } - 65170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3212 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6517 -instret:3213 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6517 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 65180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3214 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6518 -instret:3215 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6518 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 65190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65190 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 65190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3216 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6519 -instret:3217 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6519 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 65200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65200 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 65200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65200 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 65200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3218 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6520 -instret:3219 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6520 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001450, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65210 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002c00000001fffff44000000 - 65210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65210 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 65210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3220 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6521 -instret:3221 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6521 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000000400000001fffff44000000 - 65220 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 65220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3222 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6522 -instret:3223 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6522 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65230 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 65230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65250 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65250 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002000000001fffff44000000 - 65250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 65260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65260 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 65260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7f <= 0000000000000021000000001fffff44000000 - 65270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 65270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65270 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001800000001fffff44000000 - 65270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65280 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 65280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65290 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 -instret:3224 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6529 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3225 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6530 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000023000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3226 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6531 -instret:3227 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6531 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000118000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001468 -After delta: vaddr = 0x80001468 - 65320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3228 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6532 -instret:3229 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6532 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 400000002000051a1468ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001468 o: 'h0000000000000460 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001468 o: 'h0000000000000460 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001468, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 65330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3230 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6533 -instret:3231 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6533 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65340 : [doFinishMem] DTlbResp { resp: <'h0000000080001468,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001468 o: 'h0000000000000460 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001468, check_high: 'h00000000080001470, check_inclusive: True } }, specBits: 'h018 } - 65340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3232 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6534 -instret:3233 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6534 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 65350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3234 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6535 -instret:3235 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6535 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 65360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65360 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3236 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6536 -instret:3237 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6536 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 65370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65370 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200004021008ffff1ffff805821008 - 65370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65370 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3238 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6537 -instret:3239 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6537 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001458, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65380 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002c00000001fffff44000000 - 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65380 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3240 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6538 -instret:3241 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6538 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000000400000001fffff44000000 - 65390 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 - 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3242 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6539 -instret:3243 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6539 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65400 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002400000001fffff44000000 - 65400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800014c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 65410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 65410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65420 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65420 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002400000001fffff44000000 - 65420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800014c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 65430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 65430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65430 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 42 <= 0000000000000021000000001fffff44000000 - 65440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 65440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65440 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001c00000001fffff44000000 - 65440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65450 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 65460 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 -instret:3244 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6546 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3245 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6547 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000023400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3246 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6548 -instret:3247 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6548 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 000000000000011a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001470 -After delta: vaddr = 0x80001470 - 65490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3248 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6549 -instret:3249 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6549 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 400000002000051c1470ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001470 o: 'h0000000000000468 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001470 o: 'h0000000000000468 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001470, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 65500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3250 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6550 -instret:3251 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6550 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65510 : [doFinishMem] DTlbResp { resp: <'h0000000080001470,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001470 o: 'h0000000000000468 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001470, check_high: 'h00000000080001478, check_inclusive: True } }, specBits: 'h030 } - 65510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3252 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6551 -instret:3253 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6551 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 65520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3254 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6552 -instret:3255 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6552 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 65530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65530 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 65530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3256 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6553 -instret:3257 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6553 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 65540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65540 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 62 <= 40000000200004021008ffff1ffff805821008 - 65540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65540 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 65540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3258 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6554 -instret:3259 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6554 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001460, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65550 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002c00000001fffff44000000 - 65550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65550 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 65550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3260 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6555 -instret:3261 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6555 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000000400000001fffff44000000 - 65560 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 65560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3262 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6556 -instret:3263 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6556 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65570 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002800000001fffff44000000 - 65570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 65580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65590 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65590 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000002800000001fffff44000000 - 65590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3678 calling cycle - 65600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 65600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65600 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 65600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 70 <= 0000000000000021000000001fffff44000000 - 65610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 65610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65610 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002000000001fffff44000000 - 65610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65620 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 65620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 65630 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003000000001fffff44000000 -instret:3264 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6563 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3265 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6564 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000023800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3266 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6565 -instret:3267 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6565 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 000000000000011c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001478 -After delta: vaddr = 0x80001478 - 65660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3268 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6566 -instret:3269 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6566 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 400000002000051e1478ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001478 o: 'h0000000000000470 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001478 o: 'h0000000000000470 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001478, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 65670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3270 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6567 -instret:3271 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6567 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65680 : [doFinishMem] DTlbResp { resp: <'h0000000080001478,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001478 o: 'h0000000000000470 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001478, check_high: 'h00000000080001480, check_inclusive: True } }, specBits: 'h024 } - 65680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3272 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6568 -instret:3273 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6568 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 65690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3274 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6569 -instret:3275 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6569 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 65700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65700 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3276 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6570 -instret:3277 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6570 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 65710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65710 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004021008ffff1ffff805821008 - 65710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65710 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3278 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6571 -instret:3279 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6571 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001468, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65720 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002c00000001fffff44000000 - 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65720 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3280 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6572 -instret:3281 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6572 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000 - 65730 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3282 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6573 -instret:3283 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6573 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65740 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002c00000001fffff44000000 - 65740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65760 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65760 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002c00000001fffff44000000 - 65760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 65770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65770 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6b <= 0000000000000021000000001fffff44000000 - 65780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 65780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65780 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000002400000001fffff44000000 - 65780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65790 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 65800 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003000000001fffff44000000 -instret:3284 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6580 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3285 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6581 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000023c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3286 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6582 -instret:3287 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6582 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 000000000000011e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001480 -After delta: vaddr = 0x80001480 - 65830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3288 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6583 -instret:3289 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6583 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005201480ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001480 o: 'h0000000000000478 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001480 o: 'h0000000000000478 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001480, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 65840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3290 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6584 -instret:3291 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6584 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65850 : [doFinishMem] DTlbResp { resp: <'h0000000080001480,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001480 o: 'h0000000000000478 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001480, check_high: 'h00000000080001488, check_inclusive: True } }, specBits: 'h00c } - 65850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 65850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 65850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3292 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6585 -instret:3293 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6585 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 65860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3294 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6586 -instret:3295 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6586 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 65870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 65870 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 65870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3296 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6587 -instret:3297 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6587 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 65880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 65880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65880 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200004021008ffff1ffff805821008 - 65880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 65880 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 65880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3298 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6588 -instret:3299 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6588 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001470, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 65890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65890 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002c00000001fffff44000000 - 65890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 65890 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 65890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3300 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6589 -instret:3301 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6589 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000000400000001fffff44000000 - 65900 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 - 65900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 65900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3302 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6590 -instret:3303 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6590 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 65910 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 65910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 65910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 65920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 65920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 65920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 65930 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65930 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 - 65930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 65930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 65940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 65940 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 65940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 65940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000021000000001fffff44000000 - 65950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 65950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 65950 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002800000001fffff44000000 - 65950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 65950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 65960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 65960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 65960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 65960 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 65960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 65970 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 -instret:3304 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6597 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3305 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6598 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000024000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 65990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3306 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6599 -instret:3307 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6599 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000120000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001488 -After delta: vaddr = 0x80001488 - 66000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3308 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6600 -instret:3309 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6600 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 40000000200005221488ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001488, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3310 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6601 -instret:3311 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6601 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66020 : [doFinishMem] DTlbResp { resp: <'h0000000080001488,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001488, check_high: 'h00000000080001490, check_inclusive: True } }, specBits: 'h018 } - 66020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3312 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6602 -instret:3313 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6602 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 66030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3314 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6603 -instret:3315 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6603 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 66040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66040 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3316 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6604 -instret:3317 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6604 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 66050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 66050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66050 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200004021008ffff1ffff805821008 - 66050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66050 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3318 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6605 -instret:3319 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6605 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001478, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 66060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002c00000001fffff44000000 - 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66060 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3320 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6606 -instret:3321 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6606 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000000400000001fffff44000000 - 66070 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 - 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3322 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6607 -instret:3323 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6607 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 66080 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003400000001fffff44000000 - 66080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 66090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66100 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66100 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003400000001fffff44000000 - 66100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 66110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 66110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66110 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 0000000000000021000000001fffff44000000 - 66120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 66120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66120 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002c00000001fffff44000000 - 66120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66130 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 66140 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 -instret:3324 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6614 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3325 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6615 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000024400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3326 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6616 -instret:3327 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6616 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000122000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001490 -After delta: vaddr = 0x80001490 - 66170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3328 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6617 -instret:3329 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6617 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200005241490ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3330 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6618 -instret:3331 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6618 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66190 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h030 } - 66190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3332 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6619 -instret:3333 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6619 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 66200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3334 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6620 -instret:3335 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6620 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 66210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66210 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 66210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3336 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6621 -instret:3337 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6621 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 66220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 66220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66220 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6a <= 40000000200004021008ffff1ffff805821008 - 66220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66220 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 66220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3338 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6622 -instret:3339 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6622 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001480, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 66230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66230 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002c00000001fffff44000000 - 66230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66230 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 66230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3340 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6623 -instret:3341 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6623 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000000400000001fffff44000000 - 66240 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 66240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 66240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3342 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6624 -instret:3343 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6624 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 66250 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003800000001fffff44000000 - 66250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 66260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 66260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66270 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003800000001fffff44000000 - 66270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 66270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 66270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 66280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 66280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66280 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001500, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 75 <= 0000000000000021000000001fffff44000000 - 66290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 66290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66290 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 66290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66300 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 66300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 66310 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 -instret:3344 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6631 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:3345 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6632 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:3346 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6634 +instret:575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3687 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 66410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 66420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 66430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3696 calling cycle - 66440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 66440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:3347 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 6644 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 66450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 66450 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 66450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:3348 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 6645 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 66460 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002c00000001fffff44000000 - 66460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 66470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 - 66480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 66480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 66480 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 66480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3349 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6648 -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000003000000001fffff44000000 - 66490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 66490 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 66490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 66500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 66500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:3350 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 6650 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 66510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3351 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 6651 -instret:3352 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 6651 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 66520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66530 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 66530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 66540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66540 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 66540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 66540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 66550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 66550 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66550 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 66550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 66560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 66560 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66560 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 66560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 66560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 66560 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 66560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 66570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 66570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66570 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 66570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66570 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 66570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66580 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66580 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 66580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66580 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 66580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66590 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 66590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3353 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6659 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66600 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 - 66600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3354 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 6660 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 1000000000000000040000001fffff44000000 - 66610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 66610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3355 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6661 -instret:3356 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6661 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66620 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 - 66620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3357 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 6662 -instret:3358 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 6662 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 66630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:3359 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 6663 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7d <= 0000000000000024000000001fffff44000000 - 66640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 66640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 - 66650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 66650 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66650 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 66660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 66660 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66660 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 66660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66660 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 66670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66670 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000000000001fffff44000000 - 66670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66670 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000024000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 66680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66680 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4b <= 40000000200004021008ffff1ffff805821008 - 66680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66680 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000120000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 66690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66690 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66690 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001488 -After delta: vaddr = 0x80001488 - 66690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3360 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6669 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 40000000200005221488ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 66700 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 - 66700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001488, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3361 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6670 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66710 : [doFinishMem] DTlbResp { resp: <'h0000000080001488,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001488 o: 'h0000000000000480 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001488, check_high: 'h00000000080001490, check_inclusive: True } }, specBits: 'h000 } - 66710 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000400000001fffff44000000 - 66710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3362 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6671 -instret:3363 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6671 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 66720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3364 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6672 -instret:3365 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6672 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66730 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000400000001fffff44000000 - 66730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3366 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6673 -instret:3367 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6673 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 66740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3368 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6674 -instret:3369 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6674 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 44 <= 0000000000000024000000001fffff44000000 - 66750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 66750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3370 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6675 -instret:3371 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6675 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000800000001fffff44000000 - 66760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 66760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66760 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3372 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6676 -instret:3373 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6676 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 66770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001500, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 66770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 66770 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 66770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66770 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 66770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3374 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6677 -instret:3375 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6677 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001488, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 66780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66780 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 66780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 66780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 66780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3376 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6678 -instret:3377 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6678 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000024400000001fffff44000000 - 66790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 66790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66790 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 66790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3378 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6679 -instret:3379 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6679 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 0000000000000122000000001fffff44000000 - 66800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 66800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66800 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 66800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66800 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 66800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001490 -After delta: vaddr = 0x80001490 - 66800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200005241490ffff1ffff805821008 -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 66810 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 66810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 66810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 1000000000000000040000001fffff44000000 - 66820 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001490 o: 'h0000000000000488 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 66820 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000800000001fffff44000000 - 66820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 66830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 66830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 66830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66840 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66840 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 - 66840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 66850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 66850 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 66850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 76 <= 0000000000000024000000001fffff44000000 - 66860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 66860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66860 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 66860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 66870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66870 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 66870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 66880 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 66880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66880 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 66880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3380 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6688 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 66890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 66890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66890 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 66890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3381 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6689 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 0000000000000024800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 66900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 66900 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3382 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6690 -instret:3383 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6690 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000124000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 66910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66910 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 - 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 66910 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001498 -After delta: vaddr = 0x80001498 - 66910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3384 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6691 -instret:3385 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6691 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 40000000200005261498ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66920 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 66920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001498 o: 'h0000000000000490 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001498 o: 'h0000000000000490 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001498, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3386 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6692 -instret:3387 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6692 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000000400000001fffff44000000 - 66930 : [doFinishMem] DTlbResp { resp: <'h0000000080001498,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001498 o: 'h0000000000000490 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001498, check_high: 'h000000000800014a0, check_inclusive: True } }, specBits: 'h004 } - 66930 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000c00000001fffff44000000 - 66930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3388 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6693 -instret:3389 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6693 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 66940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 66940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 66940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3390 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6694 -instret:3391 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6694 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66950 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000c00000001fffff44000000 - 66950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3392 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6695 -instret:3393 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6695 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 66960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 66960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 66960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3394 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6696 -instret:3395 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6696 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0b <= 0000000000000024000000001fffff44000000 - 66970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001490, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 66970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 66970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 66970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3396 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6697 -instret:3397 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6697 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000001000000001fffff44000000 - 66980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 66980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 66980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 66980 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 66980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3398 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6698 -instret:3399 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6698 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 66990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 66990 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 66990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 66990 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 66990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 66990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 66990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 67000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 67000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67000 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200004021008ffff1ffff805821008 - 67000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000024c00000001fffff44000000 - 67010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67010 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000126000000001fffff44000000 - 67020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 67020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67020 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67020 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014a0 -After delta: vaddr = 0x800014a0 - 67020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 47 <= 400000002000052814a0ffff1ffff805821008 - 67030 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 67030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800014a0 o: 'h0000000000000498 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014a0 o: 'h0000000000000498 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 1000000000000000040000001fffff44000000 - 67040 : [doFinishMem] DTlbResp { resp: <'h00000000800014a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014a0 o: 'h0000000000000498 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014a0, check_high: 'h000000000800014a8, check_inclusive: True } }, specBits: 'h00c } - 67040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67040 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001000000001fffff44000000 - 67040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 67050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67050 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67060 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000800000001fffff44000000 - 67060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 67070 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000001000000001fffff44000000 - 67070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 68 <= 0000000000000024000000001fffff44000000 - 67080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 67080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3400 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6708 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67090 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3401 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6709 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67100 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 67100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3402 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6710 -instret:3403 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6710 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 67110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3404 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6711 -instret:3405 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6711 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000025000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3406 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6712 -instret:3407 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6712 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000128000000001fffff44000000 - 67130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 67130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014a8 -After delta: vaddr = 0x800014a8 - 67130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3408 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6713 -instret:3409 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6713 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 400000002000052a14a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 67140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800014a8 o: 'h00000000000004a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014a8 o: 'h00000000000004a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67140 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 67140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3410 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6714 -instret:3411 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6714 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67150 : [doFinishMem] DTlbResp { resp: <'h00000000800014a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014a8 o: 'h00000000000004a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014a8, check_high: 'h000000000800014b0, check_inclusive: True } }, specBits: 'h018 } - 67150 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6b <= 40000000200004021008ffff1ffff805821008 - 67150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67150 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 67150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3412 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6715 -instret:3413 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6715 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 67160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 67160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67160 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 67160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3414 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6716 -instret:3415 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6716 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001498, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 67170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67170 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 67170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3416 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6717 -instret:3417 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6717 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000000400000001fffff44000000 - 67180 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 - 67180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3418 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6718 -instret:3419 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6718 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 76 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67190 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001400000001fffff44000000 - 67190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67210 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001400000001fffff44000000 - 67210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 67220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67220 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 05 <= 0000000000000024000000001fffff44000000 - 67230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 67230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67230 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000c00000001fffff44000000 - 67230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67240 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67250 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 -instret:3420 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6725 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3421 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6726 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000025400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3422 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6727 -instret:3423 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6727 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 000000000000012a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014b0 -After delta: vaddr = 0x800014b0 - 67280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3424 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6728 -instret:3425 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6728 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 400000002000052c14b0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800014b0 o: 'h00000000000004a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014b0 o: 'h00000000000004a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3426 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6729 -instret:3427 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6729 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67300 : [doFinishMem] DTlbResp { resp: <'h00000000800014b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014b0 o: 'h00000000000004a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014b0, check_high: 'h000000000800014b8, check_inclusive: True } }, specBits: 'h030 } - 67300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3428 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6730 -instret:3429 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6730 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 67310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3430 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6731 -instret:3431 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6731 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 67320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67320 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3432 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6732 -instret:3433 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6732 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 67330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 67330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67330 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200004021008ffff1ffff805821008 - 67330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67330 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3434 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6733 -instret:3435 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6733 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 67340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67340 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 67340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67340 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 67340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3436 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6734 -instret:3437 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6734 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000000400000001fffff44000000 - 67350 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 67350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800014a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3438 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6735 -instret:3439 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6735 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67360 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000001800000001fffff44000000 - 67360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 67370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67380 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67380 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001800000001fffff44000000 - 67380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 67390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 67390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67390 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 67390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4d <= 0000000000000024000000001fffff44000000 - 67400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 67400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67400 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001000000001fffff44000000 - 67400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67410 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 67410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 67420 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 -instret:3440 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6742 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3441 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6743 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000025800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3442 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6744 -instret:3443 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6744 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 000000000000012c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014b8 -After delta: vaddr = 0x800014b8 - 67450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3444 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6745 -instret:3445 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6745 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000052e14b8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800014b8 o: 'h00000000000004b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014b8 o: 'h00000000000004b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3446 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6746 -instret:3447 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6746 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67470 : [doFinishMem] DTlbResp { resp: <'h00000000800014b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014b8 o: 'h00000000000004b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014b8, check_high: 'h000000000800014c0, check_inclusive: True } }, specBits: 'h024 } - 67470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3448 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6747 -instret:3449 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6747 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 67480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3450 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6748 -instret:3451 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6748 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 67490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67490 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 67490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3452 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6749 -instret:3453 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6749 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 67500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 67500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67500 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200004021008ffff1ffff805821008 - 67500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67500 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 67500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3454 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6750 -instret:3455 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6750 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 67510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67510 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 67510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67510 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 67510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800014a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3456 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6751 -instret:3457 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6751 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000000400000001fffff44000000 - 67520 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800014a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800014a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3458 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6752 -instret:3459 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6752 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67530 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001c00000001fffff44000000 - 67530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 67540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67550 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67550 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001c00000001fffff44000000 - 67550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 67560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 67560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67560 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 61 <= 0000000000000024000000001fffff44000000 - 67570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 67570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67570 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 67570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67580 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 67590 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 -instret:3460 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6759 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3461 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6760 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000025c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3462 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6761 -instret:3463 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6761 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 000000000000012e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014c0 -After delta: vaddr = 0x800014c0 - 67620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3464 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6762 -instret:3465 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6762 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 400000002000053014c0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800014c0 o: 'h00000000000004b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014c0 o: 'h00000000000004b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3466 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6763 -instret:3467 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6763 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67640 : [doFinishMem] DTlbResp { resp: <'h00000000800014c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014c0 o: 'h00000000000004b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014c0, check_high: 'h000000000800014c8, check_inclusive: True } }, specBits: 'h00c } - 67640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3468 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6764 -instret:3469 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6764 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 67650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3470 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6765 -instret:3471 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6765 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 67660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67660 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3472 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6766 -instret:3473 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6766 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 67670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 67670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67670 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 67670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67670 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3474 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6767 -instret:3475 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6767 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 67680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67680 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003000000001fffff44000000 - 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67680 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800014b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3476 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6768 -instret:3477 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6768 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 - 67690 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800014b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800014b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3478 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6769 -instret:3479 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6769 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67700 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 67700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 67710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67720 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 67720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 67730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 67730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67730 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6d <= 0000000000000024000000001fffff44000000 - 67740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 67740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67740 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001800000001fffff44000000 - 67740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67750 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 67750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 67760 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 -instret:3480 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6776 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3481 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6777 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000026000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3482 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6778 -instret:3483 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6778 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000130000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014c8 -After delta: vaddr = 0x800014c8 - 67790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3484 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6779 -instret:3485 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6779 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 400000002000053214c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800014c8 o: 'h00000000000004c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014c8 o: 'h00000000000004c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3486 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6780 -instret:3487 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6780 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67810 : [doFinishMem] DTlbResp { resp: <'h00000000800014c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014c8 o: 'h00000000000004c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014c8, check_high: 'h000000000800014d0, check_inclusive: True } }, specBits: 'h018 } - 67810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3488 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6781 -instret:3489 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6781 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 67820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3490 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6782 -instret:3491 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6782 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 67830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 67830 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3492 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6783 -instret:3493 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6783 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 67840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 67840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67840 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200004021008ffff1ffff805821008 - 67840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 67840 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3494 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6784 -instret:3495 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6784 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 67850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67850 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 67850 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800014b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3496 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6785 -instret:3497 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6785 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 67860 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003000000001fffff44000000 - 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800014b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800014b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3498 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6786 -instret:3499 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6786 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 67870 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002400000001fffff44000000 - 67870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67890 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67890 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002400000001fffff44000000 - 67890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 67900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 67900 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 67900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7a <= 0000000000000024000000001fffff44000000 - 67910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 67910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67910 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001c00000001fffff44000000 - 67910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 67910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 67920 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 67930 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 -instret:3500 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6793 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3501 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6794 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000026400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3502 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6795 -instret:3503 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6795 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000132000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014d0 -After delta: vaddr = 0x800014d0 - 67960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3504 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6796 -instret:3505 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6796 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 400000002000053414d0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800014d0 o: 'h00000000000004c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014d0 o: 'h00000000000004c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 67970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3506 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6797 -instret:3507 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6797 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 67980 : [doFinishMem] DTlbResp { resp: <'h00000000800014d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014d0 o: 'h00000000000004c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014d0, check_high: 'h000000000800014d8, check_inclusive: True } }, specBits: 'h030 } - 67980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 67980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 67980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3508 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6798 -instret:3509 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6798 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 67990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 67990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 67990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 67990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 67990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 67990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3510 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6799 -instret:3511 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6799 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 68000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68000 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3512 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6800 -instret:3513 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6800 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 68010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 68010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68010 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 64 <= 40000000200004021008ffff1ffff805821008 - 68010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68010 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3514 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6801 -instret:3515 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6801 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 68020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68020 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 - 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68020 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3516 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6802 -instret:3517 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6802 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000000400000001fffff44000000 - 68030 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3518 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6803 -instret:3519 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6803 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 68040 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002800000001fffff44000000 - 68040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68050 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68060 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002800000001fffff44000000 - 68060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 68060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 68070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68070 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68080 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001540, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 66 <= 0000000000000024000000001fffff44000000 - 68080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 68080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68080 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002000000001fffff44000000 - 68080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68090 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68100 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 -instret:3520 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6810 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3521 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6811 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000026800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3522 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6812 -instret:3523 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6812 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000134000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014d8 -After delta: vaddr = 0x800014d8 - 68130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3524 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6813 -instret:3525 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6813 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 400000002000053614d8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800014d8 o: 'h00000000000004d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014d8 o: 'h00000000000004d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 68140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3526 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6814 -instret:3527 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6814 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68150 : [doFinishMem] DTlbResp { resp: <'h00000000800014d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014d8 o: 'h00000000000004d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014d8, check_high: 'h000000000800014e0, check_inclusive: True } }, specBits: 'h024 } - 68150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 68150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3528 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6815 -instret:3529 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6815 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 68160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3530 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6816 -instret:3531 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6816 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 68170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68170 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3532 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6817 -instret:3533 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6817 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 68180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 68180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68180 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 68180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68180 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 68180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3534 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6818 -instret:3535 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6818 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 68190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68190 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68190 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3536 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6819 -instret:3537 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6819 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 68200 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3538 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6820 -instret:3539 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6820 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 68210 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002c00000001fffff44000000 - 68210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 68220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68230 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002c00000001fffff44000000 - 68230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3705 calling cycle - 68240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 68240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68240 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 74 <= 0000000000000024000000001fffff44000000 - 68250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 68250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68250 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000002400000001fffff44000000 - 68250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68260 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 68270 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 -instret:3540 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6827 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3541 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6828 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000026c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3542 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6829 -instret:3543 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6829 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000136000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014e0 -After delta: vaddr = 0x800014e0 - 68300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3544 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6830 -instret:3545 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6830 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 400000002000053814e0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800014e0 o: 'h00000000000004d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014e0 o: 'h00000000000004d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 68310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3546 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6831 -instret:3547 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6831 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68320 : [doFinishMem] DTlbResp { resp: <'h00000000800014e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014e0 o: 'h00000000000004d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014e0, check_high: 'h000000000800014e8, check_inclusive: True } }, specBits: 'h00c } - 68320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 68320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3548 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6832 -instret:3549 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6832 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 68330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3550 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6833 -instret:3551 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6833 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 68340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68340 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3552 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6834 -instret:3553 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6834 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 68350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 68350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68350 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 02 <= 40000000200004021008ffff1ffff805821008 - 68350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68350 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3554 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6835 -instret:3555 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6835 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 68360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68360 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68360 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3556 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6836 -instret:3557 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6836 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 0000000000000000400000001fffff44000000 - 68370 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3558 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6837 -instret:3559 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6837 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 68380 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 68380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 68390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68400 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68400 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 68400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 68410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 68410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68410 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000024000000001fffff44000000 - 68420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 68420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68420 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002800000001fffff44000000 - 68420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68430 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 68440 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 -instret:3560 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6844 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3561 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6845 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000027000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3562 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6846 -instret:3563 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6846 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000138000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014e8 -After delta: vaddr = 0x800014e8 - 68470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3564 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6847 -instret:3565 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6847 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 400000002000053a14e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 68480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3566 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6848 -instret:3567 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6848 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68490 : [doFinishMem] DTlbResp { resp: <'h00000000800014e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014e8, check_high: 'h000000000800014f0, check_inclusive: True } }, specBits: 'h018 } - 68490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 68490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3568 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6849 -instret:3569 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6849 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 68500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3570 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6850 -instret:3571 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6850 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 68510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68510 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3572 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6851 -instret:3573 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6851 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 68520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 68520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68520 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200004021008ffff1ffff805821008 - 68520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68520 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3574 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6852 -instret:3575 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6852 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 68530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68530 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68530 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3576 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6853 -instret:3577 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6853 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 - 68540 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003000000001fffff44000000 - 68540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 68540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3578 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6854 -instret:3579 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6854 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 68550 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003400000001fffff44000000 - 68550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68560 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001540, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 68560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 68560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68570 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68570 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003400000001fffff44000000 - 68570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080001540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 68580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 68580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68580 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 67 <= 0000000000000024000000001fffff44000000 - 68590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 68590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68590 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000002c00000001fffff44000000 - 68590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68600 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 68610 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003000000001fffff44000000 -instret:3580 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6861 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3581 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6862 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000027400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3582 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6863 -instret:3583 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6863 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 000000000000013a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014f0 -After delta: vaddr = 0x800014f0 - 68640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3584 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6864 -instret:3585 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6864 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 400000002000053c14f0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 68650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3586 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6865 -instret:3587 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6865 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68660 : [doFinishMem] DTlbResp { resp: <'h00000000800014f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014f0, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h030 } - 68660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 68660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3588 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6866 -instret:3589 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6866 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 68670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3590 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6867 -instret:3591 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6867 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 68680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 68680 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3592 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6868 -instret:3593 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6868 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 68690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 68690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68690 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200004021008ffff1ffff805821008 - 68690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 68690 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3594 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6869 -instret:3595 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6869 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 68700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68700 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 68700 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3596 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6870 -instret:3597 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6870 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000000400000001fffff44000000 - 68710 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3598 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6871 -instret:3599 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6871 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 68720 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003800000001fffff44000000 - 68720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68740 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68740 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003800000001fffff44000000 - 68740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 68740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 68750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 68750 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6f <= 0000000000000024000000001fffff44000000 - 68760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 68760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68760 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 68760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 68770 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 68780 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 -instret:3600 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6878 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:3601 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6879 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:3602 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6881 calling cycle +instret:578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3714 calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 68880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 68890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 68900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 68910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 68910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:3603 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 6891 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 68920 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:3604 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 6892 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 68930 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 68930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3723 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 68940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 68940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000000000000001fffff44000000 - 68950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 68950 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 68950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 68950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3605 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6895 -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000003400000001fffff44000000 - 68960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 68960 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000004000000001fffff44000000 - 68960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 68960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 68970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 68970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:3606 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 6897 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 68980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 68980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3607 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 6898 -instret:3608 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 6898 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 68990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 68990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 68990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 68990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 68990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69000 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 69010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69010 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 69010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 69020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69020 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 69030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 69030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69030 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200004021008ffff1ffff805821008 - 69030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 69030 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 69040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69040 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003400000001fffff44000000 - 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69040 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69050 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003400000001fffff44000000 - 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69050 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69060 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 69060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3609 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 6906 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69070 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 - 69070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3610 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 6907 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 1000000000000000040000001fffff44000000 - 69080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 69080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3611 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6908 -instret:3612 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6908 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69090 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000000000001fffff44000000 - 69090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3613 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 6909 -instret:3614 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 6909 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 69100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:3615 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 6910 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 73 <= 0000000000000027000000001fffff44000000 - 69110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 69110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000400000001fffff44000000 - 69120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 69120 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69120 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 69130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 69130 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69130 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 69130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69130 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 69140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69140 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 - 69140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69140 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000027000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 69150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69150 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 40000000200004021008ffff1ffff805821008 - 69150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69150 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000138000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 69160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69160 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003400000001fffff44000000 - 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69160 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014e8 -After delta: vaddr = 0x800014e8 - 69160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3616 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6916 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 400000002000053a14e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 69170 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 69170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3617 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6917 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69180 : [doFinishMem] DTlbResp { resp: <'h00000000800014e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014e8 o: 'h00000000000004e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014e8, check_high: 'h000000000800014f0, check_inclusive: True } }, specBits: 'h000 } - 69180 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000400000001fffff44000000 - 69180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3618 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6918 -instret:3619 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6918 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 69190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3620 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6919 -instret:3621 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6919 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69200 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000400000001fffff44000000 - 69200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3622 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6920 -instret:3623 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6920 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 69210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3624 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6921 -instret:3625 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6921 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 50 <= 0000000000000027000000001fffff44000000 - 69220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 69220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3626 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6922 -instret:3627 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6922 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000000800000001fffff44000000 - 69230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 69230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69230 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 69230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3628 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6923 -instret:3629 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6923 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 69240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 69240 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 69240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69240 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 69240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3630 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6924 -instret:3631 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6924 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 69250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69250 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 69250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3632 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6925 -instret:3633 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6925 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000027400000001fffff44000000 - 69260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 69260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69260 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3634 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6926 -instret:3635 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6926 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 000000000000013a000000001fffff44000000 - 69270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 69270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69270 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003400000001fffff44000000 - 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69270 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014f0 -After delta: vaddr = 0x800014f0 - 69270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800014e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000053c14f0ffff1ffff805821008 -[RFile] wr_ 1: r 02 <= 0000000000000000400000001fffff44000000 - 69280 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 69280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800014e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800014e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 1000000000000000040000001fffff44000000 - 69290 : [doFinishMem] DTlbResp { resp: <'h00000000800014f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f0 o: 'h00000000000004e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014f0, check_high: 'h000000000800014f8, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 69290 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000800000001fffff44000000 - 69290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 69300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69310 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000800000001fffff44000000 - 69310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 69320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69320 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6a <= 0000000000000027000000001fffff44000000 - 69330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 69330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69330 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000400000001fffff44000000 - 69330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 69340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69340 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 69350 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 69350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69350 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3636 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6935 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 69360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 69360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69360 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200004021008ffff1ffff805821008 - 69360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3637 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6936 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000000000027800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 69370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69370 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3638 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6937 -instret:3639 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6937 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 000000000000013c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 69380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69380 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003400000001fffff44000000 - 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69380 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800014f8 -After delta: vaddr = 0x800014f8 - 69380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3640 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6938 -instret:3641 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 400000002000053e14f8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69390 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000003000000001fffff44000000 - 69390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800014f8 o: 'h00000000000004f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800014f8 o: 'h00000000000004f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800014f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3642 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6939 -instret:3643 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6939 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000000400000001fffff44000000 - 69400 : [doFinishMem] DTlbResp { resp: <'h00000000800014f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800014f8 o: 'h00000000000004f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800014f8, check_high: 'h00000000080001500, check_inclusive: True } }, specBits: 'h004 } - 69400 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000c00000001fffff44000000 - 69400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3644 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6940 -instret:3645 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6940 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 69410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3646 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6941 -instret:3647 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69420 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000c00000001fffff44000000 - 69420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3648 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6942 -instret:3649 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6942 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 69430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3650 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6943 -instret:3651 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6943 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000027000000001fffff44000000 - 69440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 69440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3652 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6944 -instret:3653 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6944 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000001000000001fffff44000000 - 69450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 69450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69450 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3654 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6945 -instret:3655 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6945 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 69460 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 69460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69460 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800014f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 69470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 69470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69470 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 66 <= 40000000200004021008ffff1ffff805821008 - 69470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800014f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800014f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000027c00000001fffff44000000 - 69480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 69480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69480 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 000000000000013e000000001fffff44000000 - 69490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 69490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69490 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003400000001fffff44000000 - 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69490 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001500 -After delta: vaddr = 0x80001500 - 69490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 4a <= 40000000200005401500ffff1ffff805821008 - 69500 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 69500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001500 o: 'h00000000000004f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001500 o: 'h00000000000004f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001500, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 1000000000000000040000001fffff44000000 - 69510 : [doFinishMem] DTlbResp { resp: <'h0000000080001500,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001500 o: 'h00000000000004f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001500, check_high: 'h00000000080001508, check_inclusive: True } }, specBits: 'h00c } - 69510 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69510 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001000000001fffff44000000 - 69510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 69520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69520 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69530 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000800000001fffff44000000 - 69530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 69540 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001000000001fffff44000000 - 69540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 5e <= 0000000000000027000000001fffff44000000 - 69550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 69550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3656 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6955 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69560 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3657 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6956 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69570 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 69570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3658 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6957 -instret:3659 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6957 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 69580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3660 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6958 -instret:3661 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6958 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000028000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3662 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6959 -instret:3663 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6959 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000140000000001fffff44000000 - 69600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 69600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001508 -After delta: vaddr = 0x80001508 - 69600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3664 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6960 -instret:3665 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6960 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 40000000200005421508ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 69610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001508 o: 'h0000000000000500 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001508 o: 'h0000000000000500 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001508, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69610 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3666 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6961 -instret:3667 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6961 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69620 : [doFinishMem] DTlbResp { resp: <'h0000000080001508,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001508 o: 'h0000000000000500 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001508, check_high: 'h00000000080001510, check_inclusive: True } }, specBits: 'h018 } - 69620 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 74 <= 40000000200004021008ffff1ffff805821008 - 69620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69620 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3668 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6962 -instret:3669 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6962 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 69630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69630 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003400000001fffff44000000 - 69630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3670 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6963 -instret:3671 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6963 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800014f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 69640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69640 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3672 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6964 -instret:3673 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6964 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000 - 69650 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003000000001fffff44000000 - 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800014f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3674 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6965 -instret:3675 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6965 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 69660 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001400000001fffff44000000 - 69660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 69670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69680 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69680 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001400000001fffff44000000 - 69680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 69690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 69690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69690 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 62 <= 0000000000000027000000001fffff44000000 - 69700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 69700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69700 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 69700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69710 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 69720 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 -instret:3676 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6972 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3677 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6973 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000028400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3678 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6974 -instret:3679 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6974 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000142000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001510 -After delta: vaddr = 0x80001510 - 69750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3680 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6975 -instret:3681 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6975 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 40000000200005441510ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001510 o: 'h0000000000000508 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001510 o: 'h0000000000000508 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001510, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3682 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6976 -instret:3683 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6976 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69770 : [doFinishMem] DTlbResp { resp: <'h0000000080001510,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001510 o: 'h0000000000000508 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001510, check_high: 'h00000000080001518, check_inclusive: True } }, specBits: 'h030 } - 69770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3684 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6977 -instret:3685 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6977 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 69780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3686 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6978 -instret:3687 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6978 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 69790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69790 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3688 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6979 -instret:3689 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6979 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 69800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69800 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200004021008ffff1ffff805821008 - 69800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69800 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3690 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6980 -instret:3691 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6980 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001500, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 69810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69810 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003400000001fffff44000000 - 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69810 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3692 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6981 -instret:3693 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6981 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000000400000001fffff44000000 - 69820 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3694 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6982 -instret:3695 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6982 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 69830 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000001800000001fffff44000000 - 69830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 69840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 69840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69850 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69850 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001800000001fffff44000000 - 69850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 69850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 69860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 69860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 69860 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 69860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69870 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001580, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 0a <= 0000000000000027000000001fffff44000000 - 69870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 69870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69870 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001000000001fffff44000000 - 69870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 69880 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 69880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 69890 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 -instret:3696 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6989 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3697 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 6990 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000028800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3698 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 6991 -instret:3699 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 6991 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000144000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001518 -After delta: vaddr = 0x80001518 - 69920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3700 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 6992 -instret:3701 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 6992 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200005461518ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001518 o: 'h0000000000000510 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001518 o: 'h0000000000000510 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001518, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 69930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3702 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 6993 -instret:3703 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 6993 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69940 : [doFinishMem] DTlbResp { resp: <'h0000000080001518,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001518 o: 'h0000000000000510 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001518, check_high: 'h00000000080001520, check_inclusive: True } }, specBits: 'h024 } - 69940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 69940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 69940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3704 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 6994 -instret:3705 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 6994 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 69950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 69950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 69950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3706 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 6995 -instret:3707 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 6995 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 69960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 69960 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 69960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3708 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 6996 -instret:3709 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 6996 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 69970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 69970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 69970 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0b <= 40000000200004021008ffff1ffff805821008 - 69970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 69970 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3710 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 6997 -instret:3711 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 6997 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 69980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001508, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 69980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 69980 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003400000001fffff44000000 - 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 69980 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 69980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3712 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 6998 -instret:3713 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 6998 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000000400000001fffff44000000 - 69990 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 69990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3714 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 6999 -instret:3715 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 6999 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70000 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001c00000001fffff44000000 - 70000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70020 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 70020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 70030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70030 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 60 <= 0000000000000027000000001fffff44000000 - 70040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 70040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70040 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001400000001fffff44000000 - 70040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70050 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70060 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 -instret:3716 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7006 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3717 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7007 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000028c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3718 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7008 -instret:3719 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7008 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000146000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001520 -After delta: vaddr = 0x80001520 - 70090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3720 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7009 -instret:3721 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7009 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200005481520ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001520 o: 'h0000000000000518 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001520 o: 'h0000000000000518 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001520, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3722 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7010 -instret:3723 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7010 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70110 : [doFinishMem] DTlbResp { resp: <'h0000000080001520,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001520 o: 'h0000000000000518 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001520, check_high: 'h00000000080001528, check_inclusive: True } }, specBits: 'h00c } - 70110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3724 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7011 -instret:3725 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7011 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 70120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3726 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7012 -instret:3727 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7012 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 70130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70130 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3728 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7013 -instret:3729 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7013 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 70140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70140 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200004021008ffff1ffff805821008 - 70140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3730 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7014 -instret:3731 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7014 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001510, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 70150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000003400000001fffff44000000 - 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3732 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7015 -instret:3733 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7015 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000000400000001fffff44000000 - 70160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3734 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7016 -instret:3735 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7016 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70170 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 70170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70190 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002000000001fffff44000000 - 70190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 70200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70200 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 0000000000000027000000001fffff44000000 - 70210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 70210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70210 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000001800000001fffff44000000 - 70210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70220 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70230 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 -instret:3736 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7023 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3737 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7024 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000029000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3738 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7025 -instret:3739 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7025 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000148000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001528 -After delta: vaddr = 0x80001528 - 70260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3740 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7026 -instret:3741 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7026 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 400000002000054a1528ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001528 o: 'h0000000000000520 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001528 o: 'h0000000000000520 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001528, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3742 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7027 -instret:3743 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7027 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70280 : [doFinishMem] DTlbResp { resp: <'h0000000080001528,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001528 o: 'h0000000000000520 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001528, check_high: 'h00000000080001530, check_inclusive: True } }, specBits: 'h018 } - 70280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3744 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7028 -instret:3745 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7028 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 70290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3746 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7029 -instret:3747 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7029 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 70300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70300 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3748 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7030 -instret:3749 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7030 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 70310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70310 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 02 <= 40000000200004021008ffff1ffff805821008 - 70310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70310 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3750 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7031 -instret:3751 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7031 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001518, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 70320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70320 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003400000001fffff44000000 - 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70320 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3752 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7032 -instret:3753 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7032 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000000400000001fffff44000000 - 70330 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 - 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3754 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7033 -instret:3755 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7033 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70340 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002400000001fffff44000000 - 70340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70350 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001580, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 70350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 70350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70360 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70360 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002400000001fffff44000000 - 70360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 70370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 70370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 79 <= 0000000000000027000000001fffff44000000 - 70380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 70380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001c00000001fffff44000000 - 70380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70390 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 70400 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000003000000001fffff44000000 -instret:3756 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7040 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3757 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7041 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000029400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3758 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7042 -instret:3759 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7042 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 000000000000014a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001530 -After delta: vaddr = 0x80001530 - 70430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3760 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7043 -instret:3761 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7043 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 400000002000054c1530ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001530 o: 'h0000000000000528 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001530 o: 'h0000000000000528 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001530, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3762 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7044 -instret:3763 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7044 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70450 : [doFinishMem] DTlbResp { resp: <'h0000000080001530,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001530 o: 'h0000000000000528 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001530, check_high: 'h00000000080001538, check_inclusive: True } }, specBits: 'h030 } - 70450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3764 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7045 -instret:3765 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7045 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 70460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3766 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7046 -instret:3767 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7046 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 70470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70470 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 70470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3768 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7047 -instret:3769 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7047 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 70480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70480 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5a <= 40000000200004021008ffff1ffff805821008 - 70480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70480 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 70480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3770 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7048 -instret:3771 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7048 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001520, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 70490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70490 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003400000001fffff44000000 - 70490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70490 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 70490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3772 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7049 -instret:3773 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7049 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000000400000001fffff44000000 - 70500 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 70500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 70500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3774 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7050 -instret:3775 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7050 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70510 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002800000001fffff44000000 - 70510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 70520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70530 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70530 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002800000001fffff44000000 - 70530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 70540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 70540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70540 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 70540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4e <= 0000000000000027000000001fffff44000000 - 70550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 70550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70550 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002000000001fffff44000000 - 70550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70560 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 70560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 70570 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003000000001fffff44000000 -instret:3776 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7057 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3777 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7058 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000029800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3778 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7059 -instret:3779 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7059 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000000000014c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001538 -After delta: vaddr = 0x80001538 - 70600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3780 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7060 -instret:3781 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7060 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 400000002000054e1538ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001538 o: 'h0000000000000530 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001538 o: 'h0000000000000530 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001538, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3782 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7061 -instret:3783 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7061 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70620 : [doFinishMem] DTlbResp { resp: <'h0000000080001538,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001538 o: 'h0000000000000530 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001538, check_high: 'h00000000080001540, check_inclusive: True } }, specBits: 'h024 } - 70620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3784 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7062 -instret:3785 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7062 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 70630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3786 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7063 -instret:3787 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7063 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 70640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70640 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3788 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7064 -instret:3789 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7064 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 70650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70650 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 70650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70650 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3790 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7065 -instret:3791 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001528, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 70660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70660 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003400000001fffff44000000 - 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70660 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3792 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7066 -instret:3793 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7066 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000000400000001fffff44000000 - 70670 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3794 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7067 -instret:3795 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7067 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70680 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002c00000001fffff44000000 - 70680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70700 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000002c00000001fffff44000000 - 70700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 70710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70710 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 0000000000000027000000001fffff44000000 - 70720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 70720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70720 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002400000001fffff44000000 - 70720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70730 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 70740 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 -instret:3796 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7074 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3797 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7075 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000029c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3798 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7076 -instret:3799 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7076 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 000000000000014e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001540 -After delta: vaddr = 0x80001540 - 70770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3800 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7077 -instret:3801 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7077 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 40000000200005501540ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001540 o: 'h0000000000000538 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001540 o: 'h0000000000000538 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001540, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3802 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7078 -instret:3803 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7078 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70790 : [doFinishMem] DTlbResp { resp: <'h0000000080001540,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001540 o: 'h0000000000000538 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001540, check_high: 'h00000000080001548, check_inclusive: True } }, specBits: 'h00c } - 70790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3804 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7079 -instret:3805 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7079 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 70800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3806 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7080 -instret:3807 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7080 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 70810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70810 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 70810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3808 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7081 -instret:3809 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7081 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 70820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70820 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6c <= 40000000200004021008ffff1ffff805821008 - 70820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70820 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 70820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3810 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7082 -instret:3811 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7082 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001530, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 70830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70830 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003400000001fffff44000000 - 70830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 70830 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 70830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3812 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7083 -instret:3813 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7083 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000400000001fffff44000000 - 70840 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 - 70840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 70840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3814 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7084 -instret:3815 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7084 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 70850 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 70850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 70860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 70860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 70860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70870 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70870 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 70870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3732 calling cycle - 70880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 70880 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000027000000001fffff44000000 - 70890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 70890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70890 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002800000001fffff44000000 - 70890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 70900 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 70910 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 -instret:3816 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7091 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3817 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7092 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 000000000000002a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3818 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7093 -instret:3819 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7093 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000150000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001548 -After delta: vaddr = 0x80001548 - 70940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3820 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7094 -instret:3821 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7094 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 40000000200005521548ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001548, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 70950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3822 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7095 -instret:3823 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7095 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70960 : [doFinishMem] DTlbResp { resp: <'h0000000080001548,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001548, check_high: 'h00000000080001550, check_inclusive: True } }, specBits: 'h018 } - 70960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 70960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 70960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3824 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7096 -instret:3825 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7096 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 70970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 70970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 70970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 70970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3826 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7097 -instret:3827 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7097 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 70980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 70980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 70980 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 70980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3828 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7098 -instret:3829 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7098 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 70990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 70990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 70990 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200004021008ffff1ffff805821008 - 70990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 70990 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 70990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3830 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7099 -instret:3831 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7099 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001538, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 71000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71000 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003400000001fffff44000000 - 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71000 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3832 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7100 -instret:3833 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7100 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000000400000001fffff44000000 - 71010 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3834 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7101 -instret:3835 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7101 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 71020 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003400000001fffff44000000 - 71020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 71030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71040 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003400000001fffff44000000 - 71040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 71050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 71050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71050 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 46 <= 0000000000000027000000001fffff44000000 - 71060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 71060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71060 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002c00000001fffff44000000 - 71060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71070 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 71080 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003000000001fffff44000000 -instret:3836 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7108 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3837 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7109 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 000000000000002a400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3838 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7110 -instret:3839 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7110 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000152000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001550 -After delta: vaddr = 0x80001550 - 71110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3840 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7111 -instret:3841 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7111 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 40000000200005541550ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001550, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3842 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7112 -instret:3843 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7112 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71130 : [doFinishMem] DTlbResp { resp: <'h0000000080001550,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001550, check_high: 'h00000000080001558, check_inclusive: True } }, specBits: 'h030 } - 71130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3844 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7113 -instret:3845 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7113 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 71140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3846 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7114 -instret:3847 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7114 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 71150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71150 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 71150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3848 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7115 -instret:3849 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7115 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 71160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 71160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71160 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6e <= 40000000200004021008ffff1ffff805821008 - 71160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71160 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3850 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7116 -instret:3851 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7116 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001540, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 71170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71170 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003400000001fffff44000000 - 71170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71170 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 71170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3852 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7117 -instret:3853 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7117 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000000400000001fffff44000000 - 71180 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003000000001fffff44000000 - 71180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 71180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3854 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7118 -instret:3855 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7118 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 71190 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003800000001fffff44000000 - 71190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 71200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71200 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71210 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003800000001fffff44000000 - 71210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 71210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 71220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 71220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71220 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71230 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800015c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 77 <= 0000000000000027000000001fffff44000000 - 71230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 71230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71230 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 71230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71240 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 71250 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 -instret:3856 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7125 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:3857 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7126 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:3858 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7128 calling cycle calling cycle +instret:581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3741 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 71350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 71360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 71370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 71380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 71380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:3859 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 7138 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 71390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 71390 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 71390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:3860 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 7139 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 71400 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003400000001fffff44000000 - 71400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 71410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000000000000001fffff44000000 - 71420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 71420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 71420 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 71420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3861 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7142 -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000003800000001fffff44000000 - 71430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 71430 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000004000000001fffff44000000 - 71430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3750 calling cycle - 71440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 71440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:3862 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 7144 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 71450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3863 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 7145 -instret:3864 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 7145 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 71460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71470 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 71470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 71480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71480 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 71480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 71480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 71490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 71490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71490 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 71490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 71500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 71500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71500 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200004021008ffff1ffff805821008 - 71500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 71500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 71500 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 71500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 71510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 71510 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71510 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003800000001fffff44000000 - 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71510 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71520 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003800000001fffff44000000 - 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71520 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71530 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 71530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3865 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7153 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71540 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000 - 71540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3866 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 7154 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 1000000000000000040000001fffff44000000 - 71550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 71550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3867 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7155 -instret:3868 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7155 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71560 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 71560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3869 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 7156 -instret:3870 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 7156 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 71570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:3871 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 7157 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 44 <= 000000000000002a000000001fffff44000000 - 71580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 71580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000000400000001fffff44000000 - 71590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 71590 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71590 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 71600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 71600 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71600 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 71600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71600 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 71610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71610 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 71610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71610 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 000000000000002a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 71620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71620 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 60 <= 40000000200004021008ffff1ffff805821008 - 71620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000150000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 71630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003800000001fffff44000000 - 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71630 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001548 -After delta: vaddr = 0x80001548 - 71630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3872 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7163 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 40000000200005521548ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 71640 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003000000001fffff44000000 - 71640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001548, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3873 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7164 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71650 : [doFinishMem] DTlbResp { resp: <'h0000000080001548,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001548 o: 'h0000000000000540 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001548, check_high: 'h00000000080001550, check_inclusive: True } }, specBits: 'h000 } - 71650 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000400000001fffff44000000 - 71650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3874 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7165 -instret:3875 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7165 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 71660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3876 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7166 -instret:3877 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7166 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71670 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 71670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3878 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7167 -instret:3879 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7167 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 71680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3880 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7168 -instret:3881 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7168 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 54 <= 000000000000002a000000001fffff44000000 - 71690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 71690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3882 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7169 -instret:3883 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7169 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000000800000001fffff44000000 - 71700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 71700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71700 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 71700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3884 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7170 -instret:3885 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7170 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 71710 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800015c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 71710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 71710 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 71710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71710 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 71710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3886 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7171 -instret:3887 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7171 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001548, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 71720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71720 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200004021008ffff1ffff805821008 - 71720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71720 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 71720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800015c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 71720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3888 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7172 -instret:3889 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7172 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 000000000000002a400000001fffff44000000 - 71730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 71730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71730 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 71730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3890 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7173 -instret:3891 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7173 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000000000152000000001fffff44000000 - 71740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 71740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71740 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003800000001fffff44000000 - 71740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71740 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 71740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001550 -After delta: vaddr = 0x80001550 - 71740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200005541550ffff1ffff805821008 -[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000 - 71750 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 71750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001550, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 71750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 1000000000000000040000001fffff44000000 - 71760 : [doFinishMem] DTlbResp { resp: <'h0000000080001550,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001550 o: 'h0000000000000548 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001550, check_high: 'h00000000080001558, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 71760 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000800000001fffff44000000 - 71760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 71770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 71770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71780 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000800000001fffff44000000 - 71780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 71790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71790 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 71790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5d <= 000000000000002a000000001fffff44000000 - 71800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 71800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71800 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000400000001fffff44000000 - 71800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 71810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71810 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 71810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 71820 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 71820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71820 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3892 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7182 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 71830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 71830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71830 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200004021008ffff1ffff805821008 - 71830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3893 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7183 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 000000000000002a800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 71840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71840 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3894 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7184 -instret:3895 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7184 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000000000154000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 71850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71850 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003800000001fffff44000000 - 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71850 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001558 -After delta: vaddr = 0x80001558 - 71850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3896 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7185 -instret:3897 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7185 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005561558ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71860 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000003000000001fffff44000000 - 71860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001558 o: 'h0000000000000550 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001558 o: 'h0000000000000550 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001558, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3898 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7186 -instret:3899 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7186 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000400000001fffff44000000 - 71870 : [doFinishMem] DTlbResp { resp: <'h0000000080001558,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001558 o: 'h0000000000000550 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001558, check_high: 'h00000000080001560, check_inclusive: True } }, specBits: 'h004 } - 71870 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 - 71870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3900 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7187 -instret:3901 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7187 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 71880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 71880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3902 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7188 -instret:3903 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7188 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71890 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000c00000001fffff44000000 - 71890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3904 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7189 -instret:3905 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7189 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 71900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 71900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3906 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7190 -instret:3907 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7190 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 40 <= 000000000000002a000000001fffff44000000 - 71910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001550, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 71910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 71910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3908 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7191 -instret:3909 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7191 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000001000000001fffff44000000 - 71920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 71920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 71920 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 71920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3910 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7192 -instret:3911 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7192 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 71930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 71930 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 71930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 71930 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 71930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 71940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 71940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71940 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200004021008ffff1ffff805821008 - 71940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 000000000000002ac00000001fffff44000000 - 71950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 71950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 71950 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000156000000001fffff44000000 - 71960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 71960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71960 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003800000001fffff44000000 - 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 71960 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001560 -After delta: vaddr = 0x80001560 - 71960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 7b <= 40000000200005581560ffff1ffff805821008 - 71970 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 71970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001560 o: 'h0000000000000558 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001560 o: 'h0000000000000558 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001560, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 1000000000000000040000001fffff44000000 - 71980 : [doFinishMem] DTlbResp { resp: <'h0000000080001560,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001560 o: 'h0000000000000558 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001560, check_high: 'h00000000080001568, check_inclusive: True } }, specBits: 'h00c } - 71980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 71980 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001000000001fffff44000000 - 71980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 71980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 71980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 71990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 71990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 71990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 71990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 71990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 71990 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 71990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 71990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 71990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72000 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000800000001fffff44000000 - 72000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 72010 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000001000000001fffff44000000 - 72010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 5f <= 000000000000002a000000001fffff44000000 - 72020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 72020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:3912 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7202 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 72030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72030 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 72030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3913 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7203 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72040 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 72040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3914 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7204 -instret:3915 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7204 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 72050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3916 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7205 -instret:3917 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7205 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 000000000000002b000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3918 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7206 -instret:3919 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7206 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000158000000001fffff44000000 - 72070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 72070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001568 -After delta: vaddr = 0x80001568 - 72070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3920 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7207 -instret:3921 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7207 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 400000002000055a1568ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 72080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001568 o: 'h0000000000000560 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001568 o: 'h0000000000000560 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001568, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72080 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 72080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3922 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7208 -instret:3923 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7208 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72090 : [doFinishMem] DTlbResp { resp: <'h0000000080001568,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001568 o: 'h0000000000000560 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001568, check_high: 'h00000000080001570, check_inclusive: True } }, specBits: 'h018 } - 72090 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200004021008ffff1ffff805821008 - 72090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72090 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 72090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3924 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7209 -instret:3925 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7209 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 72100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72100 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003800000001fffff44000000 - 72100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3926 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7210 -instret:3927 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7210 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001558, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72110 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 72110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3928 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7211 -instret:3929 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7211 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 72120 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000003000000001fffff44000000 - 72120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3930 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7212 -instret:3931 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7212 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72130 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000001400000001fffff44000000 - 72130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72150 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001400000001fffff44000000 - 72150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 72160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72160 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 64 <= 000000000000002a000000001fffff44000000 - 72170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 72170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72170 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000c00000001fffff44000000 - 72170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72180 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72190 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 -instret:3932 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7219 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3933 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7220 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 000000000000002b400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3934 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7221 -instret:3935 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7221 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 000000000000015a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001570 -After delta: vaddr = 0x80001570 - 72220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3936 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7222 -instret:3937 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7222 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 400000002000055c1570ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001570 o: 'h0000000000000568 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001570 o: 'h0000000000000568 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001570, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3938 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7223 -instret:3939 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7223 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72240 : [doFinishMem] DTlbResp { resp: <'h0000000080001570,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001570 o: 'h0000000000000568 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001570, check_high: 'h00000000080001578, check_inclusive: True } }, specBits: 'h030 } - 72240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3940 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7224 -instret:3941 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 72250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3942 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7225 -instret:3943 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 72260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72260 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3944 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7226 -instret:3945 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7226 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 72270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72270 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200004021008ffff1ffff805821008 - 72270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72270 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3946 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7227 -instret:3947 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7227 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001560, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72280 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003800000001fffff44000000 - 72280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72280 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 72280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3948 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7228 -instret:3949 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7228 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000000400000001fffff44000000 - 72290 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 72290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3950 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7229 -instret:3951 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7229 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72300 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001800000001fffff44000000 - 72300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 72310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72320 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72320 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001800000001fffff44000000 - 72320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 72330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 72330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72330 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 72330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5b <= 000000000000002a000000001fffff44000000 - 72340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 72340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72340 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001000000001fffff44000000 - 72340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72350 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 72350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 72360 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 -instret:3952 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7236 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3953 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7237 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 000000000000002b800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3954 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7238 -instret:3955 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7238 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 000000000000015c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001578 -After delta: vaddr = 0x80001578 - 72390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3956 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7239 -instret:3957 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7239 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 400000002000055e1578ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001578 o: 'h0000000000000570 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001578 o: 'h0000000000000570 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001578, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3958 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7240 -instret:3959 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7240 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72410 : [doFinishMem] DTlbResp { resp: <'h0000000080001578,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001578 o: 'h0000000000000570 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001578, check_high: 'h00000000080001580, check_inclusive: True } }, specBits: 'h024 } - 72410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3960 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7241 -instret:3961 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7241 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 72420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3962 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7242 -instret:3963 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7242 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 72430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72430 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 72430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3964 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7243 -instret:3965 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7243 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 72440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72440 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 40000000200004021008ffff1ffff805821008 - 72440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72440 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3966 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7244 -instret:3967 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7244 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001568, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72450 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003800000001fffff44000000 - 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72450 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3968 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7245 -instret:3969 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7245 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 - 72460 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3970 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7246 -instret:3971 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7246 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72470 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001c00000001fffff44000000 - 72470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 72480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72490 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001c00000001fffff44000000 - 72490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 72500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 72500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72500 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 43 <= 000000000000002a000000001fffff44000000 - 72510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 72510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72510 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 72510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72520 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 72530 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 -instret:3972 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7253 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3973 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7254 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 000000000000002bc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3974 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7255 -instret:3975 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7255 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 000000000000015e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001580 -After delta: vaddr = 0x80001580 - 72560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3976 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7256 -instret:3977 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7256 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 40000000200005601580ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001580 o: 'h0000000000000578 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001580 o: 'h0000000000000578 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001580, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3978 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7257 -instret:3979 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7257 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72580 : [doFinishMem] DTlbResp { resp: <'h0000000080001580,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001580 o: 'h0000000000000578 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001580, check_high: 'h00000000080001588, check_inclusive: True } }, specBits: 'h00c } - 72580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3980 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7258 -instret:3981 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7258 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 72590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:3982 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7259 -instret:3983 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7259 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 72600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72600 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:3984 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7260 -instret:3985 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7260 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 72610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72610 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5e <= 40000000200004021008ffff1ffff805821008 - 72610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72610 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 72610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:3986 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7261 -instret:3987 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7261 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001570, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72620 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000003800000001fffff44000000 - 72620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72620 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 72620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:3988 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7262 -instret:3989 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7262 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000000400000001fffff44000000 - 72630 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 - 72630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:3990 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7263 -instret:3991 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7263 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72640 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002000000001fffff44000000 - 72640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 72650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72660 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72660 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002000000001fffff44000000 - 72660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 72670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 72670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72670 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 72670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 42 <= 000000000000002a000000001fffff44000000 - 72680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 72680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72680 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001800000001fffff44000000 - 72680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72690 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 72690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 72700 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 -instret:3992 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7270 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:3993 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7271 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 000000000000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3994 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7272 -instret:3995 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7272 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000160000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001588 -After delta: vaddr = 0x80001588 - 72730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3996 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7273 -instret:3997 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7273 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 40000000200005621588ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001588 o: 'h0000000000000580 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001588 o: 'h0000000000000580 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001588, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:3998 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7274 -instret:3999 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7274 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72750 : [doFinishMem] DTlbResp { resp: <'h0000000080001588,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001588 o: 'h0000000000000580 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001588, check_high: 'h00000000080001590, check_inclusive: True } }, specBits: 'h018 } - 72750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4000 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7275 -instret:4001 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7275 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 72760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4002 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7276 -instret:4003 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7276 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 72770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72770 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 72770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4004 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7277 -instret:4005 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7277 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 72780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72780 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6c <= 40000000200004021008ffff1ffff805821008 - 72780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72780 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4006 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7278 -instret:4007 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7278 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001578, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72790 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003800000001fffff44000000 - 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72790 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4008 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7279 -instret:4009 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7279 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000000400000001fffff44000000 - 72800 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000003000000001fffff44000000 - 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4010 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7280 -instret:4011 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7280 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72810 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002400000001fffff44000000 - 72810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72830 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72830 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002400000001fffff44000000 - 72830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 72840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 72840 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7e <= 000000000000002a000000001fffff44000000 - 72850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 72850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72850 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001c00000001fffff44000000 - 72850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 72860 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 72870 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 -instret:4012 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7287 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4013 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7288 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 000000000000002c400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4014 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7289 -instret:4015 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7289 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000162000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001590 -After delta: vaddr = 0x80001590 - 72900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4016 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7290 -instret:4017 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7290 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005641590ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001590 o: 'h0000000000000588 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001590 o: 'h0000000000000588 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001590, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 72910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4018 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7291 -instret:4019 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7291 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72920 : [doFinishMem] DTlbResp { resp: <'h0000000080001590,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001590 o: 'h0000000000000588 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001590, check_high: 'h00000000080001598, check_inclusive: True } }, specBits: 'h030 } - 72920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 72920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 72920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4020 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7292 -instret:4021 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7292 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 72930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 72930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 72930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4022 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7293 -instret:4023 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7293 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 72940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 72940 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 72940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4024 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7294 -instret:4025 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7294 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 72950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 72950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 72950 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 69 <= 40000000200004021008ffff1ffff805821008 - 72950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 72950 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 72950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4026 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7295 -instret:4027 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7295 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001580, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 72960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72960 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003800000001fffff44000000 - 72960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 72960 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 72960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4028 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7296 -instret:4029 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7296 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000 - 72970 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 72970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 72970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4030 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7297 -instret:4031 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7297 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 72980 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002800000001fffff44000000 - 72980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 72980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 72990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 72990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 72990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 72990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 72990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 72990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 72990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 72990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 72990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 72990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73000 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73000 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002800000001fffff44000000 - 73000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 73000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 73000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 73010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 73010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73010 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 73010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 08 <= 000000000000002a000000001fffff44000000 - 73020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 73020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73020 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002000000001fffff44000000 - 73020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73030 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 73030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 73040 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000003000000001fffff44000000 -instret:4032 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7304 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4033 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7305 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 000000000000002c800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4034 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7306 -instret:4035 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7306 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000164000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001598 -After delta: vaddr = 0x80001598 - 73070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4036 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7307 -instret:4037 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7307 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 40000000200005661598ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001598 o: 'h0000000000000590 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001598 o: 'h0000000000000590 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001598, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 73080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4038 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7308 -instret:4039 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7308 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73090 : [doFinishMem] DTlbResp { resp: <'h0000000080001598,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001598 o: 'h0000000000000590 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001598, check_high: 'h000000000800015a0, check_inclusive: True } }, specBits: 'h024 } - 73090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 73090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4040 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7309 -instret:4041 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7309 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 73100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4042 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7310 -instret:4043 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7310 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 73110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73110 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4044 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7311 -instret:4045 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7311 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 73120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73120 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200004021008ffff1ffff805821008 - 73120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73120 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4046 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7312 -instret:4047 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001588, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 73130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73130 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000003800000001fffff44000000 - 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73130 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4048 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7313 -instret:4049 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7313 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000000400000001fffff44000000 - 73140 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 - 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4050 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7314 -instret:4051 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7314 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 73150 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002c00000001fffff44000000 - 73150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 73160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73170 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73170 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002c00000001fffff44000000 - 73170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 73180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 73180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73180 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 67 <= 000000000000002a000000001fffff44000000 - 73190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 73190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73190 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000002400000001fffff44000000 - 73190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73200 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 73210 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 -instret:4052 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7321 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4053 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7322 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 000000000000002cc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4054 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7323 -instret:4055 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7323 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000166000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015a0 -After delta: vaddr = 0x800015a0 - 73240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4056 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7324 -instret:4057 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7324 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 400000002000056815a0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800015a0 o: 'h0000000000000598 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015a0 o: 'h0000000000000598 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 73250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4058 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7325 -instret:4059 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7325 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73260 : [doFinishMem] DTlbResp { resp: <'h00000000800015a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015a0 o: 'h0000000000000598 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015a0, check_high: 'h000000000800015a8, check_inclusive: True } }, specBits: 'h00c } - 73260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 73260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4060 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7326 -instret:4061 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7326 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 73270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4062 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7327 -instret:4063 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7327 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 73280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73280 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 73280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4064 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7328 -instret:4065 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7328 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 73290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73290 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 51 <= 40000000200004021008ffff1ffff805821008 - 73290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73290 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 73290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4066 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7329 -instret:4067 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7329 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001590, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 73300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73300 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003800000001fffff44000000 - 73300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73300 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 73300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4068 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7330 -instret:4069 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7330 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000000000000400000001fffff44000000 - 73310 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 - 73310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 73310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4070 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7331 -instret:4071 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7331 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 73320 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 - 73320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 73330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 73330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73340 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73340 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000003000000001fffff44000000 - 73340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 73350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 73350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73350 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 73350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000002a000000001fffff44000000 - 73360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 73360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73360 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 - 73360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73370 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 73380 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003000000001fffff44000000 -instret:4072 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7338 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4073 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7339 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000002d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4074 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7340 -instret:4075 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7340 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000000000168000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015a8 -After delta: vaddr = 0x800015a8 - 73410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4076 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7341 -instret:4077 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7341 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 400000002000056a15a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 73420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4078 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7342 -instret:4079 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7342 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73430 : [doFinishMem] DTlbResp { resp: <'h00000000800015a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015a8, check_high: 'h000000000800015b0, check_inclusive: True } }, specBits: 'h018 } - 73430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 73430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4080 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7343 -instret:4081 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7343 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 73440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4082 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7344 -instret:4083 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7344 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 73450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73450 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4084 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7345 -instret:4085 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7345 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 73460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73460 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200004021008ffff1ffff805821008 - 73460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73460 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4086 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7346 -instret:4087 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7346 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001598, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 73470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73470 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003800000001fffff44000000 - 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73470 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4088 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7347 -instret:4089 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7347 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000000400000001fffff44000000 - 73480 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000003000000001fffff44000000 - 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4090 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7348 -instret:4091 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7348 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 73490 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003400000001fffff44000000 - 73490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 73500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73510 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73510 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003400000001fffff44000000 - 73510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3759 calling cycle - 73520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 73520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73520 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 73520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 59 <= 000000000000002a000000001fffff44000000 - 73530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 73530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73530 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002c00000001fffff44000000 - 73530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73540 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 73540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 73550 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003000000001fffff44000000 -instret:4092 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7355 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4093 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7356 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 000000000000002d400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4094 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7357 -instret:4095 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7357 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 000000000000016a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015b0 -After delta: vaddr = 0x800015b0 - 73580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4096 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7358 -instret:4097 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7358 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 400000002000056c15b0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 73590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4098 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7359 -instret:4099 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7359 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73600 : [doFinishMem] DTlbResp { resp: <'h00000000800015b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015b0, check_high: 'h000000000800015b8, check_inclusive: True } }, specBits: 'h030 } - 73600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 73600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4100 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7360 -instret:4101 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7360 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 73610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4102 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7361 -instret:4103 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7361 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 73620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73620 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 73620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4104 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7362 -instret:4105 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7362 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 73630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73630 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200004021008ffff1ffff805821008 - 73630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73630 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 73630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4106 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7363 -instret:4107 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7363 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 73640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73640 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003800000001fffff44000000 - 73640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73640 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 73640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4108 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7364 -instret:4109 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7364 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000000400000001fffff44000000 - 73650 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000003000000001fffff44000000 - 73650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 73650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4110 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7365 -instret:4111 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7365 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 73660 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003800000001fffff44000000 - 73660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 73670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 73670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73680 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73680 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000003800000001fffff44000000 - 73680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 73690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 73690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 73690 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 47 <= 000000000000002a000000001fffff44000000 - 73700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 73700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73700 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000003000000001fffff44000000 - 73700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73710 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 73720 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003000000001fffff44000000 -instret:4112 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7372 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:4113 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7373 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:4114 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7375 calling cycle calling cycle calling cycle +instret:584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3768 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 73820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 73830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 73840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 73850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 73850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:4115 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 7385 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 73860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 73860 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 73860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4116 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 7386 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 73870 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003800000001fffff44000000 - 73870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 73880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000000000001fffff44000000 - 73890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 73890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 73890 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 73890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4117 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7389 -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000003c00000001fffff44000000 - 73900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 73900 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 - 73900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 73910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 73910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:4118 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 7391 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 73920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4119 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 7392 -instret:4120 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 7392 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 73930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 73930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 73940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 73940 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 73940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 73940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 73950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 73950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73950 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 73950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 73950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 73950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 73950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 73950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 73960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 73960 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 73960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 73960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 73970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 73970 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73970 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200004021008ffff1ffff805821008 - 73970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 73970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 73970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 73970 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 73970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 73980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 73980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 73980 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003c00000001fffff44000000 - 73980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 73980 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 73980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 73990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 73990 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003c00000001fffff44000000 - 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 73990 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 73990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74000 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003000000001fffff44000000 - 74000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4121 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7400 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74010 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000000000001fffff44000000 - 74010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4122 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 7401 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 1000000000000000040000001fffff44000000 - 74020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 74020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4123 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7402 -instret:4124 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7402 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74030 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000000000001fffff44000000 - 74030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4125 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 7403 -instret:4126 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 7403 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 74040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:4127 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 7404 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 50 <= 000000000000002d000000001fffff44000000 - 74050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 74050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000400000001fffff44000000 - 74060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 74060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74060 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 74070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 74070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74070 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000003000000001fffff44000000 - 74070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74070 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 74080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74080 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 74080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74080 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 000000000000002d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 74090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74090 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 43 <= 40000000200004021008ffff1ffff805821008 - 74090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74090 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000168000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 74100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74100 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003c00000001fffff44000000 - 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74100 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015a8 -After delta: vaddr = 0x800015a8 - 74100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4128 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7410 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 400000002000056a15a8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 74110 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003000000001fffff44000000 - 74110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4129 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7411 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74120 : [doFinishMem] DTlbResp { resp: <'h00000000800015a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015a8 o: 'h00000000000005a0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015a8, check_high: 'h000000000800015b0, check_inclusive: True } }, specBits: 'h000 } - 74120 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000400000001fffff44000000 - 74120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4130 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7412 -instret:4131 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7412 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 74130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4132 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7413 -instret:4133 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7413 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74140 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000400000001fffff44000000 - 74140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4134 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7414 -instret:4135 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7414 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 74150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4136 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7415 -instret:4137 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7415 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 72 <= 000000000000002d000000001fffff44000000 - 74160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 74160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4138 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7416 -instret:4139 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7416 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000000800000001fffff44000000 - 74170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 74170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74170 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 74170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4140 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7417 -instret:4141 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7417 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 74180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 74180 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000003000000001fffff44000000 - 74180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74180 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 74180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4142 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7418 -instret:4143 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7418 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 74190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74190 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200004021008ffff1ffff805821008 - 74190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4144 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7419 -instret:4145 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7419 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 000000000000002d400000001fffff44000000 - 74200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 74200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74200 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 74200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4146 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7420 -instret:4147 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7420 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 000000000000016a000000001fffff44000000 - 74210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 74210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74210 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003c00000001fffff44000000 - 74210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74210 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 74210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015b0 -After delta: vaddr = 0x800015b0 - 74210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 400000002000056c15b0ffff1ffff805821008 -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 74220 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 74220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 74220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 1000000000000000040000001fffff44000000 - 74230 : [doFinishMem] DTlbResp { resp: <'h00000000800015b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015b0 o: 'h00000000000005a8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015b0, check_high: 'h000000000800015b8, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 74230 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000800000001fffff44000000 - 74230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 74240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 74240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74250 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74250 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000800000001fffff44000000 - 74250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 74260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74260 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 74260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6e <= 000000000000002d000000001fffff44000000 - 74270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 74270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74270 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 74270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 74280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74280 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 74280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 74290 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000003000000001fffff44000000 - 74290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74290 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 74290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4148 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7429 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 74300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 74300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74300 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 - 74300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4149 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7430 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 000000000000002d800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 74310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74310 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4150 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7431 -instret:4151 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7431 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 000000000000016c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 74320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74320 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003c00000001fffff44000000 - 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74320 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015b8 -After delta: vaddr = 0x800015b8 - 74320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4152 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7432 -instret:4153 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7432 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 400000002000056e15b8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74330 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000003000000001fffff44000000 - 74330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800015b8 o: 'h00000000000005b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015b8 o: 'h00000000000005b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4154 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7433 -instret:4155 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7433 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000400000001fffff44000000 - 74340 : [doFinishMem] DTlbResp { resp: <'h00000000800015b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015b8 o: 'h00000000000005b0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015b8, check_high: 'h000000000800015c0, check_inclusive: True } }, specBits: 'h004 } - 74340 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 - 74340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4156 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7434 -instret:4157 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7434 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 74350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4158 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7435 -instret:4159 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7435 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74360 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000c00000001fffff44000000 - 74360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4160 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7436 -instret:4161 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7436 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 74370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4162 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7437 -instret:4163 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7437 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 57 <= 000000000000002d000000001fffff44000000 - 74380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 74380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4164 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7438 -instret:4165 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7438 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000001000000001fffff44000000 - 74390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 74390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74390 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4166 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7439 -instret:4167 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7439 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 74400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 74400 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000003000000001fffff44000000 - 74400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74400 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 74410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 74410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74410 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200004021008ffff1ffff805821008 - 74410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 000000000000002dc00000001fffff44000000 - 74420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 74420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74420 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 000000000000016e000000001fffff44000000 - 74430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 74430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74430 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003c00000001fffff44000000 - 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74430 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015c0 -After delta: vaddr = 0x800015c0 - 74430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 75 <= 400000002000057015c0ffff1ffff805821008 - 74440 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000003000000001fffff44000000 - 74440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800015c0 o: 'h00000000000005b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015c0 o: 'h00000000000005b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 1000000000000000040000001fffff44000000 - 74450 : [doFinishMem] DTlbResp { resp: <'h00000000800015c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015c0 o: 'h00000000000005b8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015c0, check_high: 'h000000000800015c8, check_inclusive: True } }, specBits: 'h00c } - 74450 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74450 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000001000000001fffff44000000 - 74450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 74460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74460 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74470 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 - 74470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 74480 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000001000000001fffff44000000 - 74480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 02 <= 000000000000002d000000001fffff44000000 - 74490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 74490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4168 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7449 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 74500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74500 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 74500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4169 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7450 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74510 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000003000000001fffff44000000 - 74510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4170 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7451 -instret:4171 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7451 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 74520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4172 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7452 -instret:4173 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7452 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 000000000000002e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4174 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7453 -instret:4175 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7453 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000170000000001fffff44000000 - 74540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 74540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015c8 -After delta: vaddr = 0x800015c8 - 74540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4176 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7454 -instret:4177 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7454 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 400000002000057215c8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 74550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h00000000800015c8 o: 'h00000000000005c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015c8 o: 'h00000000000005c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74550 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 74550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4178 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7455 -instret:4179 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7455 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74560 : [doFinishMem] DTlbResp { resp: <'h00000000800015c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015c8 o: 'h00000000000005c0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015c8, check_high: 'h000000000800015d0, check_inclusive: True } }, specBits: 'h018 } - 74560 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 67 <= 40000000200004021008ffff1ffff805821008 - 74560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74560 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 74560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4180 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7456 -instret:4181 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7456 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 74570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 74570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74570 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003c00000001fffff44000000 - 74570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4182 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7457 -instret:4183 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7457 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 74580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74580 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 74580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4184 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7458 -instret:4185 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7458 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000000400000001fffff44000000 - 74590 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000003000000001fffff44000000 - 74590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 74590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800015b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4186 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7459 -instret:4187 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7459 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 74600 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001400000001fffff44000000 - 74600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 74610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74620 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74620 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001400000001fffff44000000 - 74620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3777 calling cycle - 74630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 74630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74630 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 74630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5a <= 000000000000002d000000001fffff44000000 - 74640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 74640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74640 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000c00000001fffff44000000 - 74640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74650 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 74660 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000003000000001fffff44000000 -instret:4188 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7466 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4189 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7467 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 000000000000002e400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4190 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7468 -instret:4191 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7468 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000172000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015d0 -After delta: vaddr = 0x800015d0 - 74690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4192 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7469 -instret:4193 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7469 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 400000002000057415d0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800015d0 o: 'h00000000000005c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015d0 o: 'h00000000000005c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4194 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7470 -instret:4195 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7470 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74710 : [doFinishMem] DTlbResp { resp: <'h00000000800015d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015d0 o: 'h00000000000005c8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015d0, check_high: 'h000000000800015d8, check_inclusive: True } }, specBits: 'h030 } - 74710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4196 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7471 -instret:4197 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7471 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 74720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4198 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7472 -instret:4199 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7472 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 74730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74730 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4200 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7473 -instret:4201 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7473 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 74740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 74740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74740 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6f <= 40000000200004021008ffff1ffff805821008 - 74740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74740 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4202 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7474 -instret:4203 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7474 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 74750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74750 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003c00000001fffff44000000 - 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74750 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4204 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7475 -instret:4205 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7475 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000400000001fffff44000000 - 74760 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 74760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 74760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4206 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7476 -instret:4207 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7476 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 74770 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001800000001fffff44000000 - 74770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 74780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 74780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74790 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74790 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000001800000001fffff44000000 - 74790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 74790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 74790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 74800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 74800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74800 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 74800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74810 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001640, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 5c <= 000000000000002d000000001fffff44000000 - 74810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 74810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74810 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001000000001fffff44000000 - 74810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74820 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 74820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 74830 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000003000000001fffff44000000 -instret:4208 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7483 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4209 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7484 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000002e800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4210 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7485 -instret:4211 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7485 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000174000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015d8 -After delta: vaddr = 0x800015d8 - 74860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4212 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7486 -instret:4213 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7486 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 400000002000057615d8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h00000000800015d8 o: 'h00000000000005d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015d8 o: 'h00000000000005d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 74870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4214 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7487 -instret:4215 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7487 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74880 : [doFinishMem] DTlbResp { resp: <'h00000000800015d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015d8 o: 'h00000000000005d0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015d8, check_high: 'h000000000800015e0, check_inclusive: True } }, specBits: 'h024 } - 74880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 74880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 74880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4216 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7488 -instret:4217 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7488 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 74890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4218 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7489 -instret:4219 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7489 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 74900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 74900 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 74900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4220 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7490 -instret:4221 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7490 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 74910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 74910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74910 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200004021008ffff1ffff805821008 - 74910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 74910 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 74910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4222 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7491 -instret:4223 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7491 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 74920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74920 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003c00000001fffff44000000 - 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 74920 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4224 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7492 -instret:4225 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7492 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000000400000001fffff44000000 - 74930 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4226 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7493 -instret:4227 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7493 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 74940 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001c00000001fffff44000000 - 74940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 74940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 74950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 74960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74960 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001c00000001fffff44000000 - 74960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 74960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 74970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 74970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 74970 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 74970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6b <= 000000000000002d000000001fffff44000000 - 74980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 74980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 74980 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001400000001fffff44000000 - 74980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 74980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 74990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 74990 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 75000 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000003000000001fffff44000000 -instret:4228 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7500 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4229 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7501 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 000000000000002ec00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4230 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7502 -instret:4231 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7502 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000176000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015e0 -After delta: vaddr = 0x800015e0 - 75030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4232 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7503 -instret:4233 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7503 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 400000002000057815e0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800015e0 o: 'h00000000000005d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015e0 o: 'h00000000000005d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4234 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7504 -instret:4235 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7504 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75050 : [doFinishMem] DTlbResp { resp: <'h00000000800015e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015e0 o: 'h00000000000005d8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015e0, check_high: 'h000000000800015e8, check_inclusive: True } }, specBits: 'h00c } - 75050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4236 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7505 -instret:4237 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7505 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 75060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4238 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7506 -instret:4239 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7506 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 75070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75070 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4240 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7507 -instret:4241 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7507 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 75080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75080 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200004021008ffff1ffff805821008 - 75080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75080 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4242 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7508 -instret:4243 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7508 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75090 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000003c00000001fffff44000000 - 75090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75090 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 75090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4244 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7509 -instret:4245 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7509 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000000400000001fffff44000000 - 75100 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000003000000001fffff44000000 - 75100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4246 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7510 -instret:4247 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7510 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75110 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 75110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75130 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75130 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002000000001fffff44000000 - 75130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75140 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 75140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7a <= 000000000000002d000000001fffff44000000 - 75150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 75150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75150 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001800000001fffff44000000 - 75150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75160 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 75160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75170 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000003000000001fffff44000000 -instret:4248 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7517 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4249 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7518 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 000000000000002f000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4250 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7519 -instret:4251 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7519 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000178000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015e8 -After delta: vaddr = 0x800015e8 - 75200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4252 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7520 -instret:4253 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7520 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 400000002000057a15e8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h00000000800015e8 o: 'h00000000000005e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015e8 o: 'h00000000000005e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4254 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7521 -instret:4255 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7521 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75220 : [doFinishMem] DTlbResp { resp: <'h00000000800015e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015e8 o: 'h00000000000005e0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015e8, check_high: 'h000000000800015f0, check_inclusive: True } }, specBits: 'h018 } - 75220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4256 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7522 -instret:4257 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7522 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 75230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4258 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7523 -instret:4259 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7523 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 75240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75240 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4260 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7524 -instret:4261 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7524 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 75250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75250 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 51 <= 40000000200004021008ffff1ffff805821008 - 75250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75250 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 75250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4262 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7525 -instret:4263 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7525 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75260 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000003c00000001fffff44000000 - 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75260 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4264 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7526 -instret:4265 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7526 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000000400000001fffff44000000 - 75270 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000003000000001fffff44000000 - 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4266 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7527 -instret:4267 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7527 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75280 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000002400000001fffff44000000 - 75280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001640, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 75290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 75290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75300 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75300 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000002400000001fffff44000000 - 75300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 75310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75310 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 68 <= 000000000000002d000000001fffff44000000 - 75320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 75320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75320 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001c00000001fffff44000000 - 75320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75330 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 75340 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 -instret:4268 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7534 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4269 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7535 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 000000000000002f400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4270 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7536 -instret:4271 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7536 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 000000000000017a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015f0 -After delta: vaddr = 0x800015f0 - 75370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4272 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7537 -instret:4273 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7537 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 400000002000057c15f0ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h00000000800015f0 o: 'h00000000000005e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015f0 o: 'h00000000000005e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4274 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7538 -instret:4275 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7538 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75390 : [doFinishMem] DTlbResp { resp: <'h00000000800015f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015f0 o: 'h00000000000005e8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015f0, check_high: 'h000000000800015f8, check_inclusive: True } }, specBits: 'h030 } - 75390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4276 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7539 -instret:4277 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7539 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 75400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4278 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7540 -instret:4279 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7540 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 75410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75410 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 75410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4280 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7541 -instret:4281 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7541 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 75420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75420 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0c <= 40000000200004021008ffff1ffff805821008 - 75420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75420 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 75420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4282 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7542 -instret:4283 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7542 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75430 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000003c00000001fffff44000000 - 75430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75430 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 75430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4284 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7543 -instret:4285 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7543 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000400000001fffff44000000 - 75440 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 75440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800015e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4286 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7544 -instret:4287 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7544 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75450 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002800000001fffff44000000 - 75450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 75460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75470 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75470 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000 - 75470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 75480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75480 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 75480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 70 <= 000000000000002d000000001fffff44000000 - 75490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 75490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75490 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002000000001fffff44000000 - 75490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75500 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 75500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 75510 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000003000000001fffff44000000 -instret:4288 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7551 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4289 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7552 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 000000000000002f800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4290 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7553 -instret:4291 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7553 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 000000000000017c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800015f8 -After delta: vaddr = 0x800015f8 - 75540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4292 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7554 -instret:4293 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7554 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 400000002000057e15f8ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h00000000800015f8 o: 'h00000000000005f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800015f8 o: 'h00000000000005f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800015f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4294 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7555 -instret:4295 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7555 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75560 : [doFinishMem] DTlbResp { resp: <'h00000000800015f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800015f8 o: 'h00000000000005f0 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h00000000800015f8, check_high: 'h00000000080001600, check_inclusive: True } }, specBits: 'h024 } - 75560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4296 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7556 -instret:4297 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7556 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 75570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4298 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7557 -instret:4299 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7557 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 75580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75580 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4300 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7558 -instret:4301 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7558 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 75590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75590 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200004021008ffff1ffff805821008 - 75590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4302 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7559 -instret:4303 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7559 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003c00000001fffff44000000 - 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4304 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7560 -instret:4305 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7560 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000000400000001fffff44000000 - 75610 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000003000000001fffff44000000 - 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800015e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4306 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7561 -instret:4307 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7561 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75620 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002c00000001fffff44000000 - 75620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 75630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75640 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002c00000001fffff44000000 - 75640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 75650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75650 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 46 <= 000000000000002d000000001fffff44000000 - 75660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 75660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75660 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002400000001fffff44000000 - 75660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000003000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75670 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 75680 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000003000000001fffff44000000 -instret:4308 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7568 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4309 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7569 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000000000002fc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4310 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7570 -instret:4311 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7570 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 000000000000017e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001600 -After delta: vaddr = 0x80001600 - 75710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4312 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7571 -instret:4313 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7571 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 40000000200005801600ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001600 o: 'h00000000000005f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001600 o: 'h00000000000005f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001600, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4314 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7572 -instret:4315 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7572 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75730 : [doFinishMem] DTlbResp { resp: <'h0000000080001600,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001600 o: 'h00000000000005f8 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001600, check_high: 'h00000000080001608, check_inclusive: True } }, specBits: 'h00c } - 75730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4316 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7573 -instret:4317 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7573 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 75740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4318 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7574 -instret:4319 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7574 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 75750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75750 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 75750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4320 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7575 -instret:4321 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7575 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 75760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75760 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4b <= 40000000200004021008ffff1ffff805821008 - 75760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75760 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 75760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4322 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7576 -instret:4323 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7576 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75770 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003c00000001fffff44000000 - 75770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 75770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800015f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4324 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7577 -instret:4325 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7577 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000000400000001fffff44000000 - 75780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000003000000001fffff44000000 - 75780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800015f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800015f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4326 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7578 -instret:4327 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7578 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75790 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000003000000001fffff44000000 - 75790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75810 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75810 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 75810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75820 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 75820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 000000000000002d000000001fffff44000000 - 75830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 75830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75830 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002800000001fffff44000000 - 75830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000d o: 'h000000000000000d b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 75840 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 75840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 75850 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000003000000001fffff44000000 -instret:4328 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7585 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4329 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7586 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000030000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4330 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7587 -instret:4331 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7587 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000180000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001608 -After delta: vaddr = 0x80001608 - 75880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4332 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7588 -instret:4333 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7588 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 40000000200005821608ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001608 o: 'h0000000000000600 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001608 o: 'h0000000000000600 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001608, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 75890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4334 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7589 -instret:4335 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7589 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75900 : [doFinishMem] DTlbResp { resp: <'h0000000080001608,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001608 o: 'h0000000000000600 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001608, check_high: 'h00000000080001610, check_inclusive: True } }, specBits: 'h018 } - 75900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 75900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 75900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4336 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7590 -instret:4337 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7590 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 75910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 75910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4338 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7591 -instret:4339 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7591 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 75920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 75920 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4340 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7592 -instret:4341 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7592 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 75930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 75930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75930 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200004021008ffff1ffff805821008 - 75930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 75930 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } - 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4342 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7593 -instret:4343 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7593 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800015f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 75940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75940 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 56 <= 0000000000000003c00000001fffff44000000 - 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 75940 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800015f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4344 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7594 -instret:4345 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7594 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000400000001fffff44000000 - 75950 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000003000000001fffff44000000 - 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800015f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800015f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4346 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7595 -instret:4347 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7595 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 75960 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000003400000001fffff44000000 - 75960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 75960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 75970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 75970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 75980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 75980 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000003400000001fffff44000000 - 75980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 75980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 75990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 75990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 75990 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 75990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 55 <= 000000000000002d000000001fffff44000000 - 76000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 76000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76000 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000002c00000001fffff44000000 - 76000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000e o: 'h000000000000000e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76010 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 76010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 76020 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000003000000001fffff44000000 -instret:4348 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7602 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4349 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7603 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000030400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4350 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7604 -instret:4351 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7604 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000182000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001610 -After delta: vaddr = 0x80001610 - 76050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4352 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7605 -instret:4353 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7605 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200005841610ffff1ffff805821008 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001610 o: 'h0000000000000608 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001610 o: 'h0000000000000608 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001610, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 76060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4354 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7606 -instret:4355 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7606 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76070 : [doFinishMem] DTlbResp { resp: <'h0000000080001610,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001610 o: 'h0000000000000608 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001008, authority_top: 'h00000000080001608, authority_idx: 'h0b, check_low: 'h0000000080001610, check_high: 'h00000000080001618, check_inclusive: True } }, specBits: 'h030 } - 76070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 76070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4356 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7607 -instret:4357 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7607 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 76080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 76080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4358 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7608 -instret:4359 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7608 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 76090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 76090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 76090 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 76090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4360 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7609 -instret:4361 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7609 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 76100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 76100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76100 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 01 <= 40000000200004021008ffff1ffff805821008 - 76100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 76100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 76100 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 76100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4362 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7610 -instret:4363 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7610 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001600, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 76110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 76110 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000003c00000001fffff44000000 - 76110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 76110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 76110 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 76110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4364 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7611 -instret:4365 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7611 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 0000000000000000400000001fffff44000000 - 76120 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 76120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 76120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4366 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7612 -instret:4367 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7612 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 76130 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003800000001fffff44000000 - 76130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 76140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 76140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 76140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76150 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000003800000001fffff44000000 - 76150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -[doDeqStQ_fault] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001608, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Valid tagged CapException CSR_XCapCause { cheri_exc_reg: 'h0b, cheri_exc_code: cheriExcLengthViolation }, pcHash: 'h8092 } - 76150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 76150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3786 calling cycle - 76160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 76160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 76160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4a <= 000000000000002d000000001fffff44000000 - 76170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 76170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 76170 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 76180 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001680, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 1: r 60 <= 0000000000000003c00000001fffff44000000 - 76180 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000003000000001fffff44000000 - 76180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000f o: 'h000000000000000f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76180 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 76190 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:4368 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7620 calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000030800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } - 76210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4369 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7621 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:4370 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7623 calling cycle calling cycle calling cycle +instret:587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3795 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 76310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7ff, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 76330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:4371 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 7633 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 76340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 76340 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 76340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4372 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 7634 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 76350 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000003c00000001fffff44000000 - 76350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 76360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000000000001fffff44000000 - 76370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 76370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 76370 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 76370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4373 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7637 -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000004000000001fffff44000000 - 76380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 76380 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000004000000001fffff44000000 - 76380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 76390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:4374 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 7639 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 76400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4375 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 7640 -instret:4376 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 7640 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 76410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 76410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 76420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 76420 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 76420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 76430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76430 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 76430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 76430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 76430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 76440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 76440 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 76440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 76440 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 76440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 76450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 76450 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76450 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 - 76450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 76450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 76450 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 76450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 76460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 76460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76460 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000004000000001fffff44000000 - 76460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 76460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 76460 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 76460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76470 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 76470 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000004000000001fffff44000000 - 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 76470 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76480 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000003000000001fffff44000000 - 76480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4377 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7648 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000004c; 'h3; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } - 76490 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000 - 76490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4378 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 7649 +instret:588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3804 calling cycle -[ROB incorrectSpec] 'h3 ; InstTag { way: 'h0, ptr: 'h01, t: 'h02 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:4379 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7651 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 76570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 76570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 76580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 76590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -instret:4380 PC:0x1ffff000000000000000000008000004c instr:0x06e0006f iType:J [doCommitNormalInst [0]] 7659 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 00000000200003dc000000001fffff44000000 - 76600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 76600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 76600 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 76600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 - 76610 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 000000002000015f000000001fffff44000000 - 76610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 76610 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76620 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h002 } - 76620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76620 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000020000400000000001fffff44000000 - 76620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000020000400000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 76630 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h002 } - 76630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 76630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 76630 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 76630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } -instret:4381 PC:0x1ffff00000000000000000000800000ba instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 7663 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000057c; 'h1; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } - 76640 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000020000006000000001fffff44000000 - 76640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 76640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 76640 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 76640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:4382 PC:0x1ffff00000000000000000000800000bc instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 7664 -instret:4383 PC:0x1ffff00000000000000000000800000be instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 7664 -calling cycle -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h03, t: 'h07 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 76660 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001680, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 76660 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:4384 PC:0x1ffff00000000000000000000800000c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 7666 -calling cycle - 76670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76670 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 76670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080001680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 76670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff78, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff78, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff78, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 76730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffa9c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff78, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 calling cycle - 76750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 76750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h857c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 76750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h857c } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000002000000001fffff44000000 - 76760 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 76760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h8580 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 76760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h857c } - 76760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h857c } - 76760 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 76760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8580 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000020000161800000001fffff44000000 - 76770 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 76770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8580 } - 76770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8580 } - 76770 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 76770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0a, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 0: r 6f <= 0000000020000163800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } - 76780 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200005841610ffff1ffff806441610 - 76780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0a, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4385 PC:0x1ffff000000000000000000008000057c instr:0xf7843583 iType:Ld [doCommitNormalInst [0]] 7680 -calling cycle -instret:4386 PC:0x1ffff0000000000000000000080000580 instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 7681 -instret:4387 PC:0x1ffff0000000000000000000080000584 instr:0x00004621 iType:Alu [doCommitNormalInst [1]] 7681 -calling cycle -instret:4388 PC:0x1ffff0000000000000000000080000586 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 7682 -instret:4389 PC:0x1ffff000000000000000000008000058a instr:0xa9c080e7 iType:Jr [doCommitNormalInst [1]] 7682 -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 76860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 00000000200003cc000000001fffff44000000 - 76870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000058e o: 'h000000008000058e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 76870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 00000000200003dc000000001fffff44000000 - 76880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 76880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 76880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4390 PC:0x1ffff0000000000000000000080000022 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 7688 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 76890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 76890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 76890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4391 PC:0x1ffff0000000000000000000080000024 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 7689 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 } - 76900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 76900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -instret:4392 PC:0x1ffff0000000000000000000080000026 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 7690 -instret:4393 PC:0x1ffff0000000000000000000080000028 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 7690 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3ff, localHist: 'h1ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000000000001fffff44000000 - 76910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 76910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } - 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4394 PC:0x1ffff000000000000000000008000002a instr:0xfea44023 iType:St [doCommitNormalInst [0]] 7691 -calling cycle - 76920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 } - 76920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -instret:4395 PC:0x1ffff000000000000000000008000002e instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 7692 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 76930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } - 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4396 PC:0x1ffff0000000000000000000080000032 instr:0xfcc42c23 iType:St [doCommitNormalInst [0]] 7693 -instret:4397 PC:0x1ffff0000000000000000000080000036 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 7693 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h802a } - 76940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -instret:4398 PC:0x1ffff0000000000000000000080000038 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 7694 -instret:4399 PC:0x1ffff000000000000000000008000003c instr:0x0040006f iType:J [doCommitNormalInst [1]] 7694 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 76950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 76950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } - 76950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 76950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h9ff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802e } - 76960 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 - 76960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 76960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 76970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } - 76970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f4c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802e } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 76970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8032 } - 76980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 76980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 76980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 76980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 76990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h002 } - 76990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 76990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 76990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 76990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } - 76990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 76990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 76990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 76990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 76990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8038 } - 77000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77000 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 77000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00a } - 77010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77010 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 77010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 77020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00a } - 77020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77020 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200005841610ffff1ffff806441610 - 77020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } - 77020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8038 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } - 77030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77030 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 77030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77030 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 77030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77040 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002000000001fffff44000000 - 77040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 77040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 77040 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 77040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000000400000001fffff44000000 - 77050 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000000000001fffff44000000 - 77050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77060 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000000000001fffff44000000 - 77060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hcff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00b } - 77070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4400 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7707 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77080 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 - 77080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4401 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 7708 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7b <= 0000000000000000000000001fffff44000000 - 77090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 77090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4402 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7709 -instret:4403 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7709 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 77100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4404 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 7710 -instret:4405 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 7710 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 - 77110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 77110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77110 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 77110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4406 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 7711 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 77120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 77120 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002000000001fffff44000000 - 77120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77120 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000000000000001fffff44000000 - 77130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 77130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77130 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200005841610ffff1ffff806441610 - 77130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000000000001fffff44000000 - 77140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 77140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77140 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001610 -After delta: vaddr = 0x80001610 - 77140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 40000000200005841610ffff1ffff806441610 - 77150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 77150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77150 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 - 77150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001610, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000000000000400000001fffff44000000 - 77160 : [doFinishMem] DTlbResp { resp: <'h0000000080001610,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001610, check_high: 'h00000000080001618, check_inclusive: True } }, specBits: 'h008 } - 77160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77160 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77170 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000002000000001fffff44000000 - 77170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he7f, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 77180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77180 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000400000001fffff44000000 - 77180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4407 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7718 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 77190 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 77190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4408 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7719 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 77200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4409 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7720 -instret:4410 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7720 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 77210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4411 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7721 -instret:4412 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7721 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000000800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 0b <= 0000000000000000000000001fffff44000000 - 77220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 77220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77220 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4413 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7722 -instret:4414 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7722 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 77230 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 77230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77230 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4415 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7723 -instret:4416 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7723 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 77240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77240 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 72 <= 40000000200005841610ffff1ffff806441610 - 77240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4417 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7724 -instret:4418 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7724 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 77250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77250 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 77250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4419 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7725 -instret:4420 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7725 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000000400000001fffff44000000 - 77260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 77260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77260 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 77260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77260 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 77260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4421 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7726 -instret:4422 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7726 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 5a <= 0000000000000002000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001610, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 77270 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 77270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001618 -After delta: vaddr = 0x80001618 - 77270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4423 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7727 -instret:4424 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7727 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200005861618ffff1ffff806441610 -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 - 77280 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000800000001fffff44000000 - 77280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001618 o: 'h0000000000000008 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001618 o: 'h0000000000000008 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001618, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 77280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4425 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7728 -instret:4426 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7728 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf3f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77290 : [doFinishMem] DTlbResp { resp: <'h0000000080001618,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001618 o: 'h0000000000000008 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001618, check_high: 'h00000000080001620, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 77290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 77300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 77300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 77310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77310 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000000800000001fffff44000000 - 77310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 41 <= 0000000000000000000000001fffff44000000 - 77320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 77320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77320 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 77320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 77330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77330 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 77330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77330 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 77330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 77340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77340 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 77340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77340 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 77340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 77350 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0c <= 40000000200005841610ffff1ffff806441610 - 77350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77350 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 77350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4427 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7735 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 77360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 77360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77360 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 - 77360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4428 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7736 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 77370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77370 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 77370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4429 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7737 -instret:4430 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7737 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 0000000000000004000000001fffff44000000 -[RFile] wr_ 1: r 75 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77380 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 - 77380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001620 -After delta: vaddr = 0x80001620 - 77380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4431 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7738 -instret:4432 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7738 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 1000000000000000040000001fffff44000000 -[RFile] wr_ 1: r 49 <= 40000000200005881620ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77390 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000c00000001fffff44000000 - 77390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001620 o: 'h0000000000000010 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001620 o: 'h0000000000000010 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001620, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4433 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7739 -instret:4434 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7739 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf9f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77400 : [doFinishMem] DTlbResp { resp: <'h0000000080001620,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001620 o: 'h0000000000000010 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001620, check_high: 'h00000000080001628, check_inclusive: True } }, specBits: 'h004 } - 77400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4435 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7740 -instret:4436 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7740 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 77410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4437 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7741 -instret:4438 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7741 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 77420 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000c00000001fffff44000000 - 77420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4439 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7742 -instret:4440 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7742 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4d <= 0000000000000000000000001fffff44000000 - 77430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 77430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4441 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7743 -instret:4442 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7743 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001618, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 77440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77440 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4443 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7744 -instret:4444 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7744 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000001000000001fffff44000000 - 77450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 77450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77450 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 77450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77450 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4445 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7745 -instret:4446 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7745 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 77460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 77460 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200005841610ffff1ffff806441610 - 77460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77460 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000c00000001fffff44000000 - 77470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 77470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77470 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000000000001fffff44000000 - 77470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000006000000001fffff44000000 - 77480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 77480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77480 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001628 -After delta: vaddr = 0x80001628 - 77480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 400000002000058a1628ffff1ffff806441610 - 77490 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 77490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001628 o: 'h0000000000000018 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001628 o: 'h0000000000000018 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001628, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000000400000001fffff44000000 - 77500 : [doFinishMem] DTlbResp { resp: <'h0000000080001628,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001628 o: 'h0000000000000018 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001628, check_high: 'h00000000080001630, check_inclusive: True } }, specBits: 'h00c } - 77500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77500 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000001000000001fffff44000000 - 77500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfcf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 1000000000000000040000001fffff44000000 - 77510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 77510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77510 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77520 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000000800000001fffff44000000 - 77520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 77530 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001000000001fffff44000000 - 77530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 61 <= 0000000000000000000000001fffff44000000 - 77540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 77540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4447 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7754 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77550 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4448 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7755 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77560 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 77560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4449 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7756 -instret:4450 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7756 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 77570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4451 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7757 -instret:4452 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7757 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4453 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7758 -instret:4454 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7758 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000008000000001fffff44000000 - 77590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 77590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001630 -After delta: vaddr = 0x80001630 - 77590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4455 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7759 -instret:4456 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7759 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 400000002000058c1630ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 77600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001630 o: 'h0000000000000020 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001630 o: 'h0000000000000020 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001630, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77600 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 77600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4457 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7760 -instret:4458 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7760 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77610 : [doFinishMem] DTlbResp { resp: <'h0000000080001630,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001630 o: 'h0000000000000020 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001630, check_high: 'h00000000080001638, check_inclusive: True } }, specBits: 'h018 } - 77610 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200005841610ffff1ffff806441610 - 77610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77610 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 77610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4459 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7761 -instret:4460 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7761 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 77620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77620 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000000000001fffff44000000 - 77620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4461 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7762 -instret:4462 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7762 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001620, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 77630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77630 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 77630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4463 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7763 -instret:4464 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7763 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000000400000001fffff44000000 - 77640 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 77640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 77640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4465 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7764 -instret:4466 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7764 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 77650 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000001400000001fffff44000000 - 77650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfe7, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 77660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 77660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77670 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77670 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001400000001fffff44000000 - 77670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3813 calling cycle - 77680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 77680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77680 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 77680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 42 <= 0000000000000000000000001fffff44000000 - 77690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 77690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77690 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000c00000001fffff44000000 - 77690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77700 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 77700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 77710 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002000000001fffff44000000 -instret:4467 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7771 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4468 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7772 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4469 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7773 -instret:4470 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7773 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 000000000000000a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001638 -After delta: vaddr = 0x80001638 - 77740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4471 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7774 -instret:4472 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7774 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 400000002000058e1638ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001638 o: 'h0000000000000028 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001638 o: 'h0000000000000028 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001638, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4473 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7775 -instret:4474 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7775 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77760 : [doFinishMem] DTlbResp { resp: <'h0000000080001638,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001638 o: 'h0000000000000028 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001638, check_high: 'h00000000080001640, check_inclusive: True } }, specBits: 'h030 } - 77760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4475 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7776 -instret:4476 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7776 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 77770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4477 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7777 -instret:4478 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7777 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 77780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77780 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4479 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7778 -instret:4480 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7778 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 77790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77790 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200005841610ffff1ffff806441610 - 77790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77790 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4481 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7779 -instret:4482 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7779 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001628, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 77800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77800 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000000000001fffff44000000 - 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77800 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4483 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7780 -instret:4484 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7780 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 - 77810 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4485 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7781 -instret:4486 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7781 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 77820 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001800000001fffff44000000 - 77820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff3, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 77830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77840 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77840 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000001800000001fffff44000000 - 77840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 77850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 77850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 77850 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 05 <= 0000000000000000000000001fffff44000000 - 77860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 77860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77860 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 77860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 77870 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 77870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 77880 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002000000001fffff44000000 -instret:4487 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7788 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4488 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7789 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4489 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7790 -instret:4490 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7790 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 000000000000000c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001640 -After delta: vaddr = 0x80001640 - 77910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4491 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7791 -instret:4492 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7791 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 40000000200005901640ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001640 o: 'h0000000000000030 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001640 o: 'h0000000000000030 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001640, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 77920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4493 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7792 -instret:4494 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7792 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77930 : [doFinishMem] DTlbResp { resp: <'h0000000080001640,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001640 o: 'h0000000000000030 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001640, check_high: 'h00000000080001648, check_inclusive: True } }, specBits: 'h024 } - 77930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 77930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 77930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4495 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7793 -instret:4496 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7793 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 77940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 77940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 77940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4497 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7794 -instret:4498 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7794 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 77950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 77950 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 77950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 77950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4499 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7795 -instret:4500 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7795 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 77960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 77960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 77960 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 59 <= 40000000200005841610ffff1ffff806441610 - 77960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 77960 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 77960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4501 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7796 -instret:4502 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7796 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 77970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001630, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 77970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 77970 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 77970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 77970 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 77970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4503 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7797 -instret:4504 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7797 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 77980 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 77980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 77980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 77980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 77980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 77980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 77980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4505 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7798 -instret:4506 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7798 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 77990 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001c00000001fffff44000000 - 77990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 77990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 77990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff9, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 78000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 78000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78010 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78010 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000001c00000001fffff44000000 - 78010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 78020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 78020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78020 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 73 <= 0000000000000000000000001fffff44000000 - 78030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 78030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78030 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001400000001fffff44000000 - 78030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 78050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002000000001fffff44000000 -instret:4507 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7805 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4508 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7806 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4509 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7807 -instret:4510 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7807 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 000000000000000e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001648 -After delta: vaddr = 0x80001648 - 78080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4511 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7808 -instret:4512 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7808 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 40000000200005921648ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001648 o: 'h0000000000000038 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001648 o: 'h0000000000000038 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001648, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 78090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4513 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7809 -instret:4514 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7809 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78100 : [doFinishMem] DTlbResp { resp: <'h0000000080001648,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001648 o: 'h0000000000000038 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001648, check_high: 'h00000000080001650, check_inclusive: True } }, specBits: 'h00c } - 78100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 78100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4515 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7810 -instret:4516 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7810 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 78110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4517 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7811 -instret:4518 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7811 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 78120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78120 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4519 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7812 -instret:4520 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7812 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 78130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 78130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78130 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 53 <= 40000000200005841610ffff1ffff806441610 - 78130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78130 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4521 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7813 -instret:4522 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7813 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001638, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 78140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78140 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 - 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78140 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4523 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7814 -instret:4524 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7814 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000000400000001fffff44000000 - 78150 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4525 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7815 -instret:4526 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7815 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 78160 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002000000001fffff44000000 - 78160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffc, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 78170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78180 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78180 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002000000001fffff44000000 - 78180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 78190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 78190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78190 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 78190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 45 <= 0000000000000000000000001fffff44000000 - 78200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 78200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78200 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001800000001fffff44000000 - 78200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78210 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 78210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 78220 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002000000001fffff44000000 -instret:4527 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7822 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4528 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7823 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4529 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7824 -instret:4530 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7824 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000010000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001650 -After delta: vaddr = 0x80001650 - 78250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4531 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7825 -instret:4532 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7825 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 40000000200005941650ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001650, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 78260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4533 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7826 -instret:4534 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7826 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78270 : [doFinishMem] DTlbResp { resp: <'h0000000080001650,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001650, check_high: 'h00000000080001658, check_inclusive: True } }, specBits: 'h018 } - 78270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 78270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4535 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7827 -instret:4536 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7827 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 78280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4537 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7828 -instret:4538 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7828 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 78290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78290 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 78290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4539 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7829 -instret:4540 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7829 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 78300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 78300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78300 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200005841610ffff1ffff806441610 - 78300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78300 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 78300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4541 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7830 -instret:4542 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7830 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001640, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 78310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78310 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 78310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78310 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 78310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4543 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7831 -instret:4544 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7831 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000400000001fffff44000000 - 78320 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002000000001fffff44000000 - 78320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 78320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4545 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7832 -instret:4546 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7832 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 78330 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002400000001fffff44000000 - 78330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 78340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800016c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78350 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002400000001fffff44000000 - 78350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800016c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 78350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 78350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 78360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 78360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78360 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78370 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800016c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800016c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 5b <= 0000000000000000000000001fffff44000000 - 78370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 78370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78370 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001c00000001fffff44000000 - 78370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78380 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 78390 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000002000000001fffff44000000 -instret:4547 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7839 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4548 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7840 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4549 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7841 -instret:4550 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7841 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 0000000000000012000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001658 -After delta: vaddr = 0x80001658 - 78420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4551 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7842 -instret:4552 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7842 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005961658ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001658, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 78430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4553 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7843 -instret:4554 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7843 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78440 : [doFinishMem] DTlbResp { resp: <'h0000000080001658,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001658, check_high: 'h00000000080001660, check_inclusive: True } }, specBits: 'h030 } - 78440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 78440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4555 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7844 -instret:4556 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7844 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 78450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4557 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7845 -instret:4558 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7845 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 78460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 78460 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4559 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7846 -instret:4560 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7846 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 78470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 78470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78470 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200005841610ffff1ffff806441610 - 78470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 78470 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4561 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7847 -instret:4562 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7847 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001648, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 78480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78480 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 - 78480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 78480 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 78480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4563 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7848 -instret:4564 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7848 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000000400000001fffff44000000 - 78490 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002000000001fffff44000000 - 78490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 78490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4565 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7849 -instret:4566 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7849 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 78500 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002800000001fffff44000000 - 78500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 78510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 78510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78520 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002800000001fffff44000000 - 78520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 78530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 78530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78530 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 78530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 43 <= 0000000000000000000000001fffff44000000 - 78540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 78540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78540 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002000000001fffff44000000 - 78540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78550 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 78550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 78560 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000002000000001fffff44000000 -instret:4567 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7856 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff000000000000000000008000006a; 'h4; InstTag { way: 'h0, ptr: 'h00, t: 'h00 } -instret:4568 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7857 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h0, ptr: 'h00, t: 'h00 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +instret:590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3822 calling cycle -instret:4569 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7859 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 78660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 78670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3831 calling cycle - 78680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fc, localHist: 'h2ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 78690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 78690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:4570 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 7869 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 78700 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4571 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 7870 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 78710 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000000000001fffff44000000 - 78710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 78720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h1bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 - 78730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78730 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4572 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7873 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000400000001fffff44000000 - 78740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 78740 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 78740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 78750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4573 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 7875 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 78760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 78760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:4574 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 7876 -instret:4575 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 7876 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 78770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ff, localHist: 'h2ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00d } - 78780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78780 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78790 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 78790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00e } - 78800 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78800 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 - 78800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h00c } - 78810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 78810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 78810 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 78810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haff, localHist: 'h1bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 - 78820 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 78820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78820 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 78820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000000800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78830 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000003000000001fffff44000000 - 78830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h07f, spec_tag: tagged Valid 'h7, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 78840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4576 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 7884 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 78850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800016c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 78850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 78850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h0ef, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4577 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 7885 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h0ef, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h025 } - 78860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h025 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 78860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800016c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 78860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0e7 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h0f7, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4578 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7886 -instret:4579 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7886 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h57f, localHist: 'h2ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h0f7, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h0f7, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h024 } - 78870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h0a6 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0b6 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h0b6, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4580 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 7887 -instret:4581 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 7887 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h0bf, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h0be, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h026 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 78880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 78880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 78880 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 78880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 78880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:4582 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 7888 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h036 } - 78890 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002000000001fffff44000000 - 78890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 78890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 78890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h026 } - 78900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78900 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000800000001fffff44000000 - 78900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h026, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 78900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'habf, localHist: 'h1bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h06f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000000000001fffff44000000 - 78910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 78910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 78910 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 78910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h07f, spec_tag: tagged Valid 'h7, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 78920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02e } - 78920 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 - 78920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 78920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 78920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 78920 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 78920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 78920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h026 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h06e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h0fe, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78930 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000003000000001fffff44000000 - 78930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h026 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 78930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h06e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 78940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h026 } - 78940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 78940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4583 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7894 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h0ff, spec_tag: tagged Valid 'h8, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h1ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h08, t: 'h10 } - 78950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02e } - 78950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 78950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0bf } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 78950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h1bf, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4584 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7895 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h08, t: 'h10 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:4585 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7897 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 79010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3840 calling cycle - 79020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 79030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 79040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 79050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79050 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4586 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 7905 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 79060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 79060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79060 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200005841610ffff1ffff806441610 - 79060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79060 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 79070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 79070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79070 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 - 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79070 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79080 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002000000001fffff44000000 - 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 79080 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4587 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7908 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79090 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000000000001fffff44000000 - 79090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4588 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 7909 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4589 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7910 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h2dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 79110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 79120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 79120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 79120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 64 <= 0000000000000002000000001fffff44000000 - 79130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 79130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 - 79130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 79140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4590 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 7914 -instret:4591 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 7914 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 79150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79150 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 79150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000000400000001fffff44000000 - 79160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 79160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79160 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 - 79160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79160 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 79160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000002000000001fffff44000000 - 79170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 79170 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200005841610ffff1ffff806441610 - 79170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 79170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000010000000001fffff44000000 - 79180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 79180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 - 79180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001650 -After delta: vaddr = 0x80001650 - 79180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4592 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 7918 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 40000000200005941650ffff1ffff806441610 - 79190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 79190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001650, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79190 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 79190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4593 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7919 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000000400000001fffff44000000 - 79200 : [doFinishMem] DTlbResp { resp: <'h0000000080001650,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001650 o: 'h0000000000000040 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001650, check_high: 'h00000000080001658, check_inclusive: True } }, specBits: 'h000 } - 79200 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000002000000001fffff44000000 - 79200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4594 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 7920 -instret:4595 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 7920 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 1000000000000000040000001fffff44000000 - 79210 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000400000001fffff44000000 - 79210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4596 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 7921 -instret:4597 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 7921 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001650, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 79220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4598 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 7922 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79230 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 - 79230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 79230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4599 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7923 -instret:4600 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7923 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 79240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4601 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7924 -instret:4602 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7924 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 08 <= 0000000000000002000000001fffff44000000 - 79250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 79250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000000800000001fffff44000000 - 79260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 79260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79260 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 79270 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 79270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79270 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 79280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 79280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79280 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 61 <= 40000000200005841610ffff1ffff806441610 - 79280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000002400000001fffff44000000 - 79290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 79290 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79290 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000000000012000000001fffff44000000 - 79300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 79300 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79300 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000400000001fffff44000000 - 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79300 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001658 -After delta: vaddr = 0x80001658 - 79300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200005961658ffff1ffff806441610 - 79310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79310 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000400000001fffff44000000 - 79310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001658, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79320 : [doFinishMem] DTlbResp { resp: <'h0000000080001658,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001658 o: 'h0000000000000048 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001658, check_high: 'h00000000080001660, check_inclusive: True } }, specBits: 'h004 } - 79320 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 79320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 79330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79330 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000800000001fffff44000000 - 79330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4603 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7933 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 79340 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000000800000001fffff44000000 - 79340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4604 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7934 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00b } - 79350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4605 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7935 -instret:4606 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7935 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 79360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4607 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7936 -instret:4608 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7936 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 5a <= 0000000000000002000000001fffff44000000 - 79370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 79370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4609 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7937 -instret:4610 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7937 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 79380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 79380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79380 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4611 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7938 -instret:4612 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 79390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79390 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200005841610ffff1ffff806441610 - 79390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4613 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7939 -instret:4614 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7939 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 79400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79400 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4615 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7940 -instret:4616 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7940 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000002800000001fffff44000000 - 79410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 79410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79410 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79410 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4617 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7941 -instret:4618 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000014000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001658, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 79420 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 79420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001660 -After delta: vaddr = 0x80001660 - 79420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4619 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7942 -instret:4620 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7942 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 67 <= 40000000200005981660ffff1ffff806441610 - 79430 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000c00000001fffff44000000 - 79430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001660 o: 'h0000000000000050 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001660 o: 'h0000000000000050 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001660, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 79430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4621 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7943 -instret:4622 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7943 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h36e, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 1000000000000000040000001fffff44000000 - 79440 : [doFinishMem] DTlbResp { resp: <'h0000000080001660,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001660 o: 'h0000000000000050 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001660, check_high: 'h00000000080001668, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 79440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 79450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 79450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 79460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79460 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000c00000001fffff44000000 - 79460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5d <= 0000000000000002000000001fffff44000000 - 79470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 79470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79470 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 79470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 79480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79480 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000800000001fffff44000000 - 79480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79480 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 79480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 79490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79490 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 79490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79490 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 79490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 79500 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 05 <= 40000000200005841610ffff1ffff806441610 - 79500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79500 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 79500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4623 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7950 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 79510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 79510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79510 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000400000001fffff44000000 - 79510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4624 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7951 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000016000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 79520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79520 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 79520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001668 -After delta: vaddr = 0x80001668 - 79520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4625 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7952 -instret:4626 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7952 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 72 <= 400000002000059a1668ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79530 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 79530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001668 o: 'h0000000000000058 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001668 o: 'h0000000000000058 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001668, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4627 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7953 -instret:4628 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7953 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79540 : [doFinishMem] DTlbResp { resp: <'h0000000080001668,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001668 o: 'h0000000000000058 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001668, check_high: 'h00000000080001670, check_inclusive: True } }, specBits: 'h010 } - 79540 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000001000000001fffff44000000 - 79540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4629 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7954 -instret:4630 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7954 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h36e, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 79550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4631 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7955 -instret:4632 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7955 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79560 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001000000001fffff44000000 - 79560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4633 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7956 -instret:4634 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7956 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 79570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4635 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7957 -instret:4636 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7957 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 78 <= 0000000000000002000000001fffff44000000 - 79580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 79580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4637 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7958 -instret:4638 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7958 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000001400000001fffff44000000 - 79590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001660, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 79590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79590 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 79590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4639 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7959 -instret:4640 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7959 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 79600 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 79600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79600 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4641 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7960 -instret:4642 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7960 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 79610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 79610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79610 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200005841610ffff1ffff806441610 - 79610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000003000000001fffff44000000 - 79620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 79620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79620 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000018000000001fffff44000000 - 79630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 79630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79630 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000400000001fffff44000000 - 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79630 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001670 -After delta: vaddr = 0x80001670 - 79630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 0c <= 400000002000059c1670ffff1ffff806441610 - 79640 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002000000001fffff44000000 - 79640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001670 o: 'h0000000000000060 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001670 o: 'h0000000000000060 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001670, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 1000000000000000040000001fffff44000000 - 79650 : [doFinishMem] DTlbResp { resp: <'h0000000080001670,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001670 o: 'h0000000000000060 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001670, check_high: 'h00000000080001678, check_inclusive: True } }, specBits: 'h014 } - 79650 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79650 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001400000001fffff44000000 - 79650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h36e, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 79660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79660 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79670 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000c00000001fffff44000000 - 79670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 79680 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001400000001fffff44000000 - 79680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 4a <= 0000000000000002000000001fffff44000000 - 79690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 79690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4643 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7969 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79700 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4644 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7970 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79710 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002000000001fffff44000000 - 79710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4645 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7971 -instret:4646 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7971 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 79720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4647 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7972 -instret:4648 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7972 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000003400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4649 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7973 -instret:4650 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7973 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 000000000000001a000000001fffff44000000 - 79740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 79740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001678 -After delta: vaddr = 0x80001678 - 79740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4651 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7974 -instret:4652 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7974 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 400000002000059e1678ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 79750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001678 o: 'h0000000000000068 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001678 o: 'h0000000000000068 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001678, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79750 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 79750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4653 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7975 -instret:4654 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7975 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79760 : [doFinishMem] DTlbResp { resp: <'h0000000080001678,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001678 o: 'h0000000000000068 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001678, check_high: 'h00000000080001680, check_inclusive: True } }, specBits: 'h00c } - 79760 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 65 <= 40000000200005841610ffff1ffff806441610 - 79760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79760 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 79760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4655 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7976 -instret:4656 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7976 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 79770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79770 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000400000001fffff44000000 - 79770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4657 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7977 -instret:4658 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7977 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001668, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 79780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79780 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 79780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4659 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7978 -instret:4660 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7978 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000000400000001fffff44000000 - 79790 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 79790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 79790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4661 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7979 -instret:4662 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7979 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 79800 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001800000001fffff44000000 - 79800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h36e, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 79810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 79810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79820 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79820 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001800000001fffff44000000 - 79820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 79830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 79830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 79830 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 79830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 0000000000000002000000001fffff44000000 - 79840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 79840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79840 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001000000001fffff44000000 - 79840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 79850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 79850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 79860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002000000001fffff44000000 -instret:4663 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7986 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4664 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 7987 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5e <= 0000000000000003800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4665 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 7988 -instret:4666 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 7988 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 000000000000001c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001680 -After delta: vaddr = 0x80001680 - 79890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4667 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 7989 -instret:4668 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 7989 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 40000000200005a01680ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001680 o: 'h0000000000000070 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001680 o: 'h0000000000000070 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001680, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 79900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4669 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 7990 -instret:4670 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 7990 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79910 : [doFinishMem] DTlbResp { resp: <'h0000000080001680,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001680 o: 'h0000000000000070 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001680, check_high: 'h00000000080001688, check_inclusive: True } }, specBits: 'h028 } - 79910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 79910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 79910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4671 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 7991 -instret:4672 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 7991 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 79920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 79920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4673 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 7992 -instret:4674 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 7992 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 79930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 79930 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4675 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 7993 -instret:4676 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 7993 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 79940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 79940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79940 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200005841610ffff1ffff806441610 - 79940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 79940 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4677 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 7994 -instret:4678 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 7994 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001670, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 79950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79950 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000400000001fffff44000000 - 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 79950 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4679 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 7995 -instret:4680 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 7995 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000400000001fffff44000000 - 79960 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4681 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 7996 -instret:4682 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 7996 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 79970 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 79970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 79970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 79980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 79980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 79980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 79990 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 79990 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000001c00000001fffff44000000 - 79990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 79990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 79990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 80000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 80000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80000 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 0000000000000002000000001fffff44000000 - 80010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 80010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80010 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001400000001fffff44000000 - 80010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80020 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 80030 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000002000000001fffff44000000 -instret:4683 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8003 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4684 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8004 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000003c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4685 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8005 -instret:4686 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8005 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 000000000000001e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001688 -After delta: vaddr = 0x80001688 - 80060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4687 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8006 -instret:4688 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8006 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 40000000200005a21688ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001688 o: 'h0000000000000078 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001688 o: 'h0000000000000078 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001688, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 80070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4689 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8007 -instret:4690 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8007 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80080 : [doFinishMem] DTlbResp { resp: <'h0000000080001688,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001688 o: 'h0000000000000078 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001688, check_high: 'h00000000080001690, check_inclusive: True } }, specBits: 'h030 } - 80080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 80080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4691 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8008 -instret:4692 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8008 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 80090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4693 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8009 -instret:4694 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8009 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 80100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80100 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 80100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4695 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8010 -instret:4696 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8010 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 80110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 80110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80110 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200005841610ffff1ffff806441610 - 80110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80110 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 80110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4697 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8011 -instret:4698 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8011 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001678, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 80120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80120 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 - 80120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80120 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 80120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4699 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8012 -instret:4700 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8012 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000000400000001fffff44000000 - 80130 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 80130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 80130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4701 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8013 -instret:4702 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8013 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 80140 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002000000001fffff44000000 - 80140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 80150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 80150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80160 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002000000001fffff44000000 - 80160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 80170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 80170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80170 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 80170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 0000000000000002000000001fffff44000000 - 80180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 80180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80180 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001800000001fffff44000000 - 80180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80190 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 80200 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002000000001fffff44000000 -instret:4703 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8020 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4704 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8021 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000004000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4705 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8022 -instret:4706 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8022 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000020000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001690 -After delta: vaddr = 0x80001690 - 80230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4707 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8023 -instret:4708 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8023 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200005a41690ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001690, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 80240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4709 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8024 -instret:4710 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8024 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80250 : [doFinishMem] DTlbResp { resp: <'h0000000080001690,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001690, check_high: 'h00000000080001698, check_inclusive: True } }, specBits: 'h014 } - 80250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 80250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4711 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8025 -instret:4712 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8025 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 80260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4713 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8026 -instret:4714 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8026 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 80270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80270 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4715 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8027 -instret:4716 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8027 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 80280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 80280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80280 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 53 <= 40000000200005841610ffff1ffff806441610 - 80280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80280 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4717 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8028 -instret:4718 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8028 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001680, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 80290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80290 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000400000001fffff44000000 - 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80290 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4719 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8029 -instret:4720 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8029 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 80300 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002000000001fffff44000000 - 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4721 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8030 -instret:4722 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8030 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 80310 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002400000001fffff44000000 - 80310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 80320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80330 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002400000001fffff44000000 - 80330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 80330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 80340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 80340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80340 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 80340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80350 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001700, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 47 <= 0000000000000002000000001fffff44000000 - 80350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 80350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80350 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001c00000001fffff44000000 - 80350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80360 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 80360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 80370 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002000000001fffff44000000 -instret:4723 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8037 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4724 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8038 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000000000004400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4725 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8039 -instret:4726 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8039 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000022000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001698 -After delta: vaddr = 0x80001698 - 80400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4727 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8040 -instret:4728 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8040 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200005a61698ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001698, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 80410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4729 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8041 -instret:4730 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8041 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80420 : [doFinishMem] DTlbResp { resp: <'h0000000080001698,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001698, check_high: 'h000000000800016a0, check_inclusive: True } }, specBits: 'h00c } - 80420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 80420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4731 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8042 -instret:4732 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8042 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 80430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4733 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8043 -instret:4734 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8043 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 80440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 80440 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 80440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4735 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8044 -instret:4736 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8044 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 80450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 80450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80450 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200005841610ffff1ffff806441610 - 80450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 80450 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 80450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4737 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8045 -instret:4738 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8045 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001688, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 80460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80460 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 80460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 80460 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 80460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4739 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8046 -instret:4740 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8046 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000400000001fffff44000000 - 80470 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000002000000001fffff44000000 - 80470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 80470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4741 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8047 -instret:4742 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8047 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 80480 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000002800000001fffff44000000 - 80480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 80490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 80490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80500 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002800000001fffff44000000 - 80500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 80510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 80510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80510 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 49 <= 0000000000000002000000001fffff44000000 - 80520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 80520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80520 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 - 80520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80530 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 80540 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002000000001fffff44000000 -instret:4743 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8054 +instret:593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3849 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h2; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } -instret:4744 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8055 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h18, t: 'h30 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:4745 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8057 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3858 calling cycle - 80640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 80650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 80660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 80670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 80670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:4746 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 8067 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 80680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 80680 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 80680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4747 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8068 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 80690 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 - 80690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 80700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h1db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000000000000001fffff44000000 - 80710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80710 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 80710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4748 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8071 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000000800000001fffff44000000 - 80720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 80720 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000003000000001fffff44000000 - 80720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 80730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4749 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8073 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 80740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 80740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:4750 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 8074 -instret:4751 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 8074 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 80750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h5ff, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00d } - 80760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80760 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 80760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80770 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 80770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 80770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00e } - 80780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80780 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000800000001fffff44000000 - 80780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h00c } - 80790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 80790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 80790 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 80790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haff, localHist: 'h1db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000000000000001fffff44000000 - 80800 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000800000001fffff44000000 - 80800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80800 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 80800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80810 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000003000000001fffff44000000 - 80810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h07f, spec_tag: tagged Valid 'h7, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 80820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4752 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8082 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 80830 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001700, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 80830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 80830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h0ef, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4753 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8083 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h0ef, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h025 } - 80840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h025 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0e7 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h0f7, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4754 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8084 -instret:4755 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8084 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h57f, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h0f7, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h0f7, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h024 } - 80850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h0a6 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0b6 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h0b6, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4756 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 8085 -instret:4757 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 8085 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h0bf, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h0be, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h026 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 80860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 80860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 80860 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c - 80860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:4758 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 8086 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h036 } - 80870 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002000000001fffff44000000 - 80870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h026 } - 80880 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80880 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 - 80880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h026, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 80880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'habf, localHist: 'h1db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h06f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000000000001fffff44000000 - 80890 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 80890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 80890 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h07f, spec_tag: tagged Valid 'h7, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 80900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02e } - 80900 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 - 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 80900 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 80900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h026 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h06e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h0fe, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80910 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000003000000001fffff44000000 - 80910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h026 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 80910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h06e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 80920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h026 } - 80920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 80920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h0ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4759 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8092 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h0ff, spec_tag: tagged Valid 'h8, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h1ff, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006e; 'h2; InstTag { way: 'h0, ptr: 'h00, t: 'h00 } - 80930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02e } - 80930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 80930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h0bf } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 80930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h1bf, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4760 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8093 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h00, t: 'h00 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:4761 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8095 calling cycle calling cycle +instret:595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3867 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 80990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 81000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 81010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h001 } - 81020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 81030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81030 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 81030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4762 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [0]] 8103 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 81040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 81040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81040 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5a <= 40000000200005841610ffff1ffff806441610 - 81040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 81040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 81050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 81050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000800000001fffff44000000 - 81050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81050 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 81050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81060 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002000000001fffff44000000 - 81060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 81060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 81060 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 81060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4763 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8106 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81070 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000000000000001fffff44000000 - 81070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4764 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 8107 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4765 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8108 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h2ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 81090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 81100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 81100 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 81100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 45 <= 0000000000000004000000001fffff44000000 - 81110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 81110 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000000000001fffff44000000 - 81110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 81120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4766 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 8112 -instret:4767 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 8112 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 81130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81130 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000000400000001fffff44000000 - 81140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 81140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81140 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 81140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81140 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000004000000001fffff44000000 - 81150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 81150 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200005841610ffff1ffff806441610 - 81150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81150 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000020000000001fffff44000000 - 81160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 81160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81160 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000800000001fffff44000000 - 81160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001690 -After delta: vaddr = 0x80001690 - 81160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4768 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 8116 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 40000000200005a41690ffff1ffff806441610 - 81170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 81170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001690, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81170 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4769 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8117 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 81180 : [doFinishMem] DTlbResp { resp: <'h0000000080001690,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001690 o: 'h0000000000000080 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001690, check_high: 'h00000000080001698, check_inclusive: True } }, specBits: 'h000 } - 81180 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000002000000001fffff44000000 - 81180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4770 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 8118 -instret:4771 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 8118 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 1000000000000000040000001fffff44000000 - 81190 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000400000001fffff44000000 - 81190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4772 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 8119 -instret:4773 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 8119 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001690, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 81200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4774 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8120 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81210 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 81210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4775 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8121 -instret:4776 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8121 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } - 81220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4777 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8122 -instret:4778 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8122 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6a <= 0000000000000004000000001fffff44000000 - 81230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 81230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000000800000001fffff44000000 - 81240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 81240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81240 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 81250 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 81250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81250 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 81260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 81260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81260 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 78 <= 40000000200005841610ffff1ffff806441610 - 81260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000004400000001fffff44000000 - 81270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 81270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81270 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 0000000000000022000000001fffff44000000 - 81280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 81280 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81280 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 - 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81280 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001698 -After delta: vaddr = 0x80001698 - 81280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005a61698ffff1ffff806441610 - 81290 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81290 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000000400000001fffff44000000 - 81290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001698, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81290 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 81290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81300 : [doFinishMem] DTlbResp { resp: <'h0000000080001698,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001698 o: 'h0000000000000088 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001698, check_high: 'h000000000800016a0, check_inclusive: True } }, specBits: 'h004 } - 81300 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 81300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 81310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81310 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000800000001fffff44000000 - 81310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4779 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8131 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 81320 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000000800000001fffff44000000 - 81320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4780 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8132 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00b } - 81330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4781 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8133 -instret:4782 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8133 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 81340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4783 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8134 -instret:4784 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8134 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 46 <= 0000000000000004000000001fffff44000000 - 81350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 81350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81350 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 81350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4785 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8135 -instret:4786 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8135 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 81360 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 81360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81360 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 81360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4787 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8136 -instret:4788 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8136 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h018 } - 81370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81370 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200005841610ffff1ffff806441610 - 81370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4789 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8137 -instret:4790 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8137 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 81380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81380 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 81380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4791 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8138 -instret:4792 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8138 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h018, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000004800000001fffff44000000 - 81390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 81390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81390 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000800000001fffff44000000 - 81390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81390 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 81390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4793 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8139 -instret:4794 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8139 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000024000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001698, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 81400 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002000000001fffff44000000 - 81400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016a0 -After delta: vaddr = 0x800016a0 - 81400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4795 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8140 -instret:4796 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8140 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 01 <= 40000000200005a816a0ffff1ffff806441610 - 81410 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000c00000001fffff44000000 - 81410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800016a0 o: 'h0000000000000090 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016a0 o: 'h0000000000000090 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 81410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4797 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8141 -instret:4798 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8141 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h376, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 1000000000000000040000001fffff44000000 - 81420 : [doFinishMem] DTlbResp { resp: <'h00000000800016a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016a0 o: 'h0000000000000090 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016a0, check_high: 'h000000000800016a8, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 81420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 81430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 81440 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81440 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000c00000001fffff44000000 - 81440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 77 <= 0000000000000004000000001fffff44000000 - 81450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 81450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81450 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 81450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 81460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81460 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000800000001fffff44000000 - 81460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81460 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 81470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81470 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 81470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81470 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 81480 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200005841610ffff1ffff806441610 - 81480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81480 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4799 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8148 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000004c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 81490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 81490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81490 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000800000001fffff44000000 - 81490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4800 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8149 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000026000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 81500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81500 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016a8 -After delta: vaddr = 0x800016a8 - 81500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4801 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8150 -instret:4802 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8150 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 61 <= 40000000200005aa16a8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81510 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 81510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000000800016a8 o: 'h0000000000000098 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016a8 o: 'h0000000000000098 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4803 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8151 -instret:4804 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8151 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81520 : [doFinishMem] DTlbResp { resp: <'h00000000800016a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016a8 o: 'h0000000000000098 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016a8, check_high: 'h000000000800016b0, check_inclusive: True } }, specBits: 'h010 } - 81520 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000001000000001fffff44000000 - 81520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4805 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8152 -instret:4806 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8152 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h376, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 81530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4807 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8153 -instret:4808 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8153 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81540 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000001000000001fffff44000000 - 81540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4809 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8154 -instret:4810 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8154 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 81550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4811 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8155 -instret:4812 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8155 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 44 <= 0000000000000004000000001fffff44000000 - 81560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 81560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4813 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8156 -instret:4814 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8156 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000001400000001fffff44000000 - 81570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 81570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81570 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4815 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8157 -instret:4816 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8157 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 81580 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 81580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81580 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 81580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4817 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8158 -instret:4818 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8158 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 81590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 81590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81590 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200005841610ffff1ffff806441610 - 81590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 81590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 0000000000000005000000001fffff44000000 - 81600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 81600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81600 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 81600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000028000000001fffff44000000 - 81610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 81610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81610 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000800000001fffff44000000 - 81610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81610 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 81610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016b0 -After delta: vaddr = 0x800016b0 - 81610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 42 <= 40000000200005ac16b0ffff1ffff806441610 - 81620 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 - 81620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800016b0 o: 'h00000000000000a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016b0 o: 'h00000000000000a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 81620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 1000000000000000040000001fffff44000000 - 81630 : [doFinishMem] DTlbResp { resp: <'h00000000800016b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016b0 o: 'h00000000000000a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016b0, check_high: 'h000000000800016b8, check_inclusive: True } }, specBits: 'h014 } - 81630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81630 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001400000001fffff44000000 - 81630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h376, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 81640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81640 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 81640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81650 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000000c00000001fffff44000000 - 81650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 81660 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001400000001fffff44000000 - 81660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 55 <= 0000000000000004000000001fffff44000000 - 81670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 81670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4819 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8167 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 81680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81680 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 81680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4820 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8168 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81690 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002000000001fffff44000000 - 81690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4821 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8169 -instret:4822 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8169 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 81700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4823 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8170 -instret:4824 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8170 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000005400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4825 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8171 -instret:4826 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8171 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 000000000000002a000000001fffff44000000 - 81720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 81720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016b8 -After delta: vaddr = 0x800016b8 - 81720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4827 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8172 -instret:4828 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8172 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 40000000200005ae16b8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 81730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800016b8 o: 'h00000000000000a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016b8 o: 'h00000000000000a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81730 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 81730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4829 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8173 -instret:4830 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8173 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81740 : [doFinishMem] DTlbResp { resp: <'h00000000800016b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016b8 o: 'h00000000000000a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016b8, check_high: 'h000000000800016c0, check_inclusive: True } }, specBits: 'h00c } - 81740 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 79 <= 40000000200005841610ffff1ffff806441610 - 81740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81740 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4831 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8174 -instret:4832 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8174 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 81750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000800000001fffff44000000 - 81750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4833 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8175 -instret:4834 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8175 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 81760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81760 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4835 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8176 -instret:4836 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8176 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000000400000001fffff44000000 - 81770 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4837 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8177 -instret:4838 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8177 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 81780 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001800000001fffff44000000 - 81780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h376, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 81790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81800 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81800 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001800000001fffff44000000 - 81800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 81810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 81810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81810 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 75 <= 0000000000000004000000001fffff44000000 - 81820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 81820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81820 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001000000001fffff44000000 - 81820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 81830 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 81840 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002000000001fffff44000000 -instret:4839 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8184 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4840 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8185 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 0000000000000005800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4841 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8186 -instret:4842 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8186 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 000000000000002c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016c0 -After delta: vaddr = 0x800016c0 - 81870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4843 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8187 -instret:4844 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8187 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 40000000200005b016c0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800016c0 o: 'h00000000000000b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016c0 o: 'h00000000000000b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 81880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4845 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8188 -instret:4846 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8188 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81890 : [doFinishMem] DTlbResp { resp: <'h00000000800016c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016c0 o: 'h00000000000000b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016c0, check_high: 'h000000000800016c8, check_inclusive: True } }, specBits: 'h028 } - 81890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 81890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 81890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4847 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8189 -instret:4848 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8189 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 81900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 81900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4849 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8190 -instret:4850 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8190 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 81910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 81910 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 81910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4851 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8191 -instret:4852 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8191 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 81920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 81920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81920 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0b <= 40000000200005841610ffff1ffff806441610 - 81920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 81920 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 81920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4853 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8192 -instret:4854 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8192 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 81930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81930 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000800000001fffff44000000 - 81930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 81930 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 81930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4855 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8193 -instret:4856 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8193 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000000400000001fffff44000000 - 81940 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 81940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 81940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800016b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4857 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8194 -instret:4858 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8194 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 81950 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001c00000001fffff44000000 - 81950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 81950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 81960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 81960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 81960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 81960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 81970 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81970 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000001c00000001fffff44000000 - 81970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 81970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 81980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 81980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 81980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 81980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 81980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 81980 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 81980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 81980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000004000000001fffff44000000 - 81990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 81990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 81990 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001400000001fffff44000000 - 81990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 81990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82000 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 82000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 82010 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000002000000001fffff44000000 -instret:4859 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8201 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4860 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8202 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000005c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4861 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8203 -instret:4862 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8203 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 000000000000002e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016c8 -After delta: vaddr = 0x800016c8 - 82040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4863 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8204 -instret:4864 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8204 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 40000000200005b216c8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800016c8 o: 'h00000000000000b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016c8 o: 'h00000000000000b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4865 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8205 -instret:4866 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8205 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82060 : [doFinishMem] DTlbResp { resp: <'h00000000800016c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016c8 o: 'h00000000000000b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016c8, check_high: 'h000000000800016d0, check_inclusive: True } }, specBits: 'h030 } - 82060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4867 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8206 -instret:4868 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8206 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 82070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4869 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8207 -instret:4870 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8207 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 82080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82080 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4871 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8208 -instret:4872 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8208 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 82090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 82090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82090 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 64 <= 40000000200005841610ffff1ffff806441610 - 82090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82090 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4873 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8209 -instret:4874 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8209 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 82100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82100 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000800000001fffff44000000 - 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82100 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4875 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8210 -instret:4876 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8210 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000 - 82110 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4877 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8211 -instret:4878 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8211 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 82120 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002000000001fffff44000000 - 82120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffd, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 82130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82140 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000002000000001fffff44000000 - 82140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 82150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 82150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 0000000000000004000000001fffff44000000 - 82160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 82160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001800000001fffff44000000 - 82160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000002400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82170 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 82180 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002000000001fffff44000000 -instret:4879 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8218 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4880 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8219 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000006000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4881 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8220 -instret:4882 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8220 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 0000000000000030000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016d0 -After delta: vaddr = 0x800016d0 - 82210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4883 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8221 -instret:4884 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8221 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005b416d0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4885 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8222 -instret:4886 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8222 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82230 : [doFinishMem] DTlbResp { resp: <'h00000000800016d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016d0, check_high: 'h000000000800016d8, check_inclusive: True } }, specBits: 'h014 } - 82230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4887 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8223 -instret:4888 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8223 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 82240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4889 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8224 -instret:4890 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 82250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82250 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 82250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4891 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8225 -instret:4892 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 82260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 82260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82260 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200005841610ffff1ffff806441610 - 82260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82260 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 82260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4893 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8226 -instret:4894 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8226 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 82270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82270 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 - 82270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82270 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 82270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4895 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8227 -instret:4896 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8227 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 82280 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000002000000001fffff44000000 - 82280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 82280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4897 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8228 -instret:4898 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8228 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 82290 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002400000001fffff44000000 - 82290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffe, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 82300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 82300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82310 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002400000001fffff44000000 - 82310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 82310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 82310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 82320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 82320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82320 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 82320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001740, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 2: r 43 <= 0000000000000004000000001fffff44000000 - 82330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 82330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82330 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000001c00000001fffff44000000 - 82330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000002800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82340 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 82340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 82350 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002000000001fffff44000000 -instret:4899 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8235 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4900 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8236 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 0000000000000006400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4901 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8237 -instret:4902 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8237 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000000000032000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016d8 -After delta: vaddr = 0x800016d8 - 82380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4903 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8238 -instret:4904 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8238 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 40000000200005b616d8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4905 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8239 -instret:4906 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8239 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82400 : [doFinishMem] DTlbResp { resp: <'h00000000800016d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016d8, check_high: 'h000000000800016e0, check_inclusive: True } }, specBits: 'h00c } - 82400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4907 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8240 -instret:4908 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8240 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 82410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4909 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8241 -instret:4910 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8241 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 82420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82420 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 82420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4911 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8242 -instret:4912 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8242 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 82430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 82430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82430 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200005841610ffff1ffff806441610 - 82430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82430 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4913 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8243 -instret:4914 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8243 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 82440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82440 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000800000001fffff44000000 - 82440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82440 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 82440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4915 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8244 -instret:4916 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8244 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000000400000001fffff44000000 - 82450 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002000000001fffff44000000 - 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4917 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8245 -instret:4918 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8245 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 82460 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000002800000001fffff44000000 - 82460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 82470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82480 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82480 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002800000001fffff44000000 - 82480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3876 calling cycle - 82490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 82490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82490 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 67 <= 0000000000000004000000001fffff44000000 - 82500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 82500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82500 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002000000001fffff44000000 - 82500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000002c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82510 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 82520 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002000000001fffff44000000 -instret:4919 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8252 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000006a; 'h2; InstTag { way: 'h0, ptr: 'h10, t: 'h20 } -instret:4920 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8253 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h10, t: 'h20 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:4921 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8255 calling cycle calling cycle calling cycle calling cycle +instret:597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3885 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 82620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 82630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 82640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3bf, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 82650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h002 } - 82650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:4922 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [0]] 8265 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 82660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 82660 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 82660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:4923 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8266 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 82670 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000800000001fffff44000000 - 82670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 82680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000000000000001fffff44000000 - 82690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 82690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 82690 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 82690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4924 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8269 -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000000c00000001fffff44000000 - 82700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 82700 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000003000000001fffff44000000 - 82700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h00a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 82710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } - 82710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:4925 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8271 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 82720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4926 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 8272 -instret:4927 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [1]] 8272 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 82730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82740 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00d } - 82750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82750 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 82750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 82760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } - 82760 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82760 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 82770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 82770 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82770 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 40000000200005841610ffff1ffff806441610 - 82770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 82770 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 82780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 82780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82780 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000c00000001fffff44000000 - 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82780 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82790 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82790 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000c00000001fffff44000000 - 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82790 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82800 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000002000000001fffff44000000 - 82800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4928 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8280 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001740, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 82810 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000000000001fffff44000000 - 82810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4929 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8281 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 1000000000000000040000001fffff44000000 - 82820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h005 } - 82820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080001740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4930 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8282 -instret:4931 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8282 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82830 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000 - 82830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4932 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 8283 -instret:4933 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 8283 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h006 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 82840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:4934 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 8284 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 0000000000000006000000001fffff44000000 - 82850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 82850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 82850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 82850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000400000001fffff44000000 - 82860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 82860 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82860 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 82870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 82870 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82870 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002000000001fffff44000000 - 82870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 82870 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 82870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 82880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82880 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 - 82880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82880 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000006000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 82890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82890 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 77 <= 40000000200005841610ffff1ffff806441610 - 82890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 82890 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 82890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000030000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 82900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82900 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 - 82900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 82900 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 82900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016d0 -After delta: vaddr = 0x800016d0 - 82900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4935 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8290 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 40000000200005b416d0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 82910 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000002000000001fffff44000000 - 82910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4936 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8291 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82920 : [doFinishMem] DTlbResp { resp: <'h00000000800016d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016d0 o: 'h00000000000000c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016d0, check_high: 'h000000000800016d8, check_inclusive: True } }, specBits: 'h000 } - 82920 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000400000001fffff44000000 - 82920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h011 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4937 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8292 -instret:4938 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8292 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h1dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h013, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h011 } - 82930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 82930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h013 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h013, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4939 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8293 -instret:4940 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8293 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 82940 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 82940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h012 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4941 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8294 -instret:4942 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8294 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h012 } - 82950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h012 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 82950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4943 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8295 -instret:4944 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8295 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 4f <= 0000000000000006000000001fffff44000000 - 82960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h010 } - 82960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 82960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4945 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8296 -instret:4946 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8296 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000000800000001fffff44000000 - 82970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 82970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 82970 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 82970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 82970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 82970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4947 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8297 -instret:4948 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8297 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 82980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h010 } - 82980 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 82980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 82980 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 82980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 82980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4949 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8298 -instret:4950 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8298 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 82990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 82990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 82990 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 44 <= 40000000200005841610ffff1ffff806441610 - 82990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 82990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 82990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4951 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8299 -instret:4952 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8299 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000006400000001fffff44000000 - 83000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 83000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83000 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h010, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4953 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8300 -instret:4954 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8300 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 0000000000000032000000001fffff44000000 - 83010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 83010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83010 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 - 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83010 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016d8 -After delta: vaddr = 0x800016d8 - 83010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200005b616d8ffff1ffff806441610 -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 83020 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 - 83020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 1000000000000000040000001fffff44000000 - 83030 : [doFinishMem] DTlbResp { resp: <'h00000000800016d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016d8 o: 'h00000000000000c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016d8, check_high: 'h000000000800016e0, check_inclusive: True } }, specBits: 'h010 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83030 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000800000001fffff44000000 - 83030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 83040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83050 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000800000001fffff44000000 - 83050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 83060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83060 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 58 <= 0000000000000006000000001fffff44000000 - 83070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 83070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83070 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000400000001fffff44000000 - 83070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 83080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83080 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 83080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 83090 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 83090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83090 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 83090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4955 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8309 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 83100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 83100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83100 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200005841610ffff1ffff806441610 - 83100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4956 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8310 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000006800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 83110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83110 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 83110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4957 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8311 -instret:4958 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8311 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000034000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 83120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83120 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000000c00000001fffff44000000 - 83120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 83120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016e0 -After delta: vaddr = 0x800016e0 - 83120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4959 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8312 -instret:4960 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 40000000200005b816e0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000002000000001fffff44000000 - 83130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800016e0 o: 'h00000000000000d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016e0 o: 'h00000000000000d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4961 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8313 -instret:4962 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8313 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000400000001fffff44000000 - 83140 : [doFinishMem] DTlbResp { resp: <'h00000000800016e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016e0 o: 'h00000000000000d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016e0, check_high: 'h000000000800016e8, check_inclusive: True } }, specBits: 'h004 } - 83140 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000c00000001fffff44000000 - 83140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4963 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8314 -instret:4964 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8314 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 83150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4965 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8315 -instret:4966 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8315 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83160 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000000c00000001fffff44000000 - 83160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4967 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8316 -instret:4968 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8316 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 83170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4969 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8317 -instret:4970 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8317 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 74 <= 0000000000000006000000001fffff44000000 - 83180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 83180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4971 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8318 -instret:4972 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8318 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 0000000000000001000000001fffff44000000 - 83190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 83190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83190 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 83190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4973 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8319 -instret:4974 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8319 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 83200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 83200 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 83200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83200 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 83200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 83210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 83210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83210 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200005841610ffff1ffff806441610 - 83210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000006c00000001fffff44000000 - 83220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83220 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 83220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000036000000001fffff44000000 - 83230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 83230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83230 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 83230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83230 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 83230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016e8 -After delta: vaddr = 0x800016e8 - 83230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 78 <= 40000000200005ba16e8ffff1ffff806441610 - 83240 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 83240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800016e8 o: 'h00000000000000d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016e8 o: 'h00000000000000d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 1000000000000000040000001fffff44000000 - 83250 : [doFinishMem] DTlbResp { resp: <'h00000000800016e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016e8 o: 'h00000000000000d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016e8, check_high: 'h000000000800016f0, check_inclusive: True } }, specBits: 'h00c } - 83250 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83250 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001000000001fffff44000000 - 83250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 83260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83260 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 83260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83270 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 - 83270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 83280 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001000000001fffff44000000 - 83280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 66 <= 0000000000000006000000001fffff44000000 - 83290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 83290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:4975 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8329 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83300 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4976 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8330 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83310 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 83310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4977 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8331 -instret:4978 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8331 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h078, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 83320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4979 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8332 -instret:4980 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8332 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000007000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4981 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8333 -instret:4982 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8333 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000038000000001fffff44000000 - 83340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 83340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016f0 -After delta: vaddr = 0x800016f0 - 83340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:4983 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8334 -instret:4984 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8334 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 40000000200005bc16f0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 83350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800016f0 o: 'h00000000000000e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016f0 o: 'h00000000000000e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83350 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 83350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:4985 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8335 -instret:4986 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8335 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83360 : [doFinishMem] DTlbResp { resp: <'h00000000800016f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016f0 o: 'h00000000000000e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016f0, check_high: 'h000000000800016f8, check_inclusive: True } }, specBits: 'h018 } - 83360 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4c <= 40000000200005841610ffff1ffff806441610 - 83360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83360 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4987 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8336 -instret:4988 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8336 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 83370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 83370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83370 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000c00000001fffff44000000 - 83370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:4989 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8337 -instret:4990 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8337 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 83380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83380 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:4991 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8338 -instret:4992 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8338 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 83390 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 83390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800016e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:4993 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8339 -instret:4994 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8339 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83400 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001400000001fffff44000000 - 83400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h2ee, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 83410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83420 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83420 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001400000001fffff44000000 - 83420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 83430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 83430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83430 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 83430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000006000000001fffff44000000 - 83440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 83440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83440 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000000c00000001fffff44000000 - 83440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83450 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 83450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 83460 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002000000001fffff44000000 -instret:4995 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8346 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:4996 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8347 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000007400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4997 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8348 -instret:4998 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8348 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 000000000000003a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800016f8 -After delta: vaddr = 0x800016f8 - 83490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:4999 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8349 -instret:5000 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8349 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 40000000200005be16f8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800016f8 o: 'h00000000000000e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800016f8 o: 'h00000000000000e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800016f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5001 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8350 -instret:5002 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8350 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83510 : [doFinishMem] DTlbResp { resp: <'h00000000800016f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800016f8 o: 'h00000000000000e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800016f8, check_high: 'h00000000080001700, check_inclusive: True } }, specBits: 'h030 } - 83510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5003 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8351 -instret:5004 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8351 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 83520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5005 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8352 -instret:5006 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8352 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 83530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83530 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 83530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5007 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8353 -instret:5008 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8353 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 83540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 83540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83540 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0a <= 40000000200005841610ffff1ffff806441610 - 83540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 83540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5009 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8354 -instret:5010 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8354 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 83550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000000c00000001fffff44000000 - 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83550 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5011 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8355 -instret:5012 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8355 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000000400000001fffff44000000 - 83560 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 83560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800016e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5013 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8356 -instret:5014 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8356 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83570 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001800000001fffff44000000 - 83570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 83580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83590 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83590 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000001800000001fffff44000000 - 83590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3894 calling cycle - 83600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 83600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83600 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 0000000000000006000000001fffff44000000 - 83610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 83610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83610 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001000000001fffff44000000 - 83610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83620 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 83620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 83630 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002000000001fffff44000000 -instret:5015 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8363 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5016 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8364 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000007800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5017 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8365 -instret:5018 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8365 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 000000000000003c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001700 -After delta: vaddr = 0x80001700 - 83660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5019 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8366 -instret:5020 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8366 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 40000000200005c01700ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001700 o: 'h00000000000000f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001700 o: 'h00000000000000f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001700, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5021 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8367 -instret:5022 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8367 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83680 : [doFinishMem] DTlbResp { resp: <'h0000000080001700,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001700 o: 'h00000000000000f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001700, check_high: 'h00000000080001708, check_inclusive: True } }, specBits: 'h024 } - 83680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5023 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8368 -instret:5024 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8368 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 83690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5025 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8369 -instret:5026 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8369 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 83700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83700 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 83700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5027 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8370 -instret:5028 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8370 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 83710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 83710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83710 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200005841610ffff1ffff806441610 - 83710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 83710 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5029 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8371 -instret:5030 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8371 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 83720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83720 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000c00000001fffff44000000 - 83720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83720 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 83720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5031 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8372 -instret:5032 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8372 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000000400000001fffff44000000 - 83730 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800016f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5033 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8373 -instret:5034 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8373 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83740 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 83740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h377, globalTaken: False, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 83750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83760 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83760 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000001c00000001fffff44000000 - 83760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 83770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83770 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 83770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 02 <= 0000000000000006000000001fffff44000000 - 83780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 83780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83780 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001400000001fffff44000000 - 83780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83790 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 83790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 83800 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002000000001fffff44000000 -instret:5035 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8380 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5036 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8381 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000007c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5037 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8382 -instret:5038 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8382 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 000000000000003e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001708 -After delta: vaddr = 0x80001708 - 83830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5039 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8383 -instret:5040 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8383 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 40000000200005c21708ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001708 o: 'h00000000000000f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001708 o: 'h00000000000000f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001708, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5041 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8384 -instret:5042 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8384 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83850 : [doFinishMem] DTlbResp { resp: <'h0000000080001708,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001708 o: 'h00000000000000f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001708, check_high: 'h00000000080001710, check_inclusive: True } }, specBits: 'h00c } - 83850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5043 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8385 -instret:5044 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8385 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 83860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5045 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8386 -instret:5046 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8386 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 83870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 83870 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 83870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5047 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8387 -instret:5048 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8387 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01e } - 83880 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000c00000001fffff44000000 - 83880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5049 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8388 -instret:5050 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8388 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800016f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 83890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5051 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8389 -instret:5052 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8389 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000000000000001fffff44000000 - 83900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 83900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 83900 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 83900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800016f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5053 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8390 -instret:5054 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8390 -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000001000000001fffff44000000 - 83910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 83910 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000003000000001fffff44000000 - 83910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800016f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 83910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800016f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 83910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 83920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 83930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 83930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 83930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 83940 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 83940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 83950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 83950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 83950 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 83950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 83950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 83950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 83960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 83960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83960 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000001800000001fffff44000000 - 83960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 83960 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 83960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 83960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 83970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 83970 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 - 83970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 83970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 83970 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 83970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 83980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 83980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 83980 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 58 <= 40000000200005841610ffff1ffff806441610 - 83980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5055 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8398 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 83990 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 83990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 83990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 83990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 83990 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 83990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5056 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8399 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84000 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002000000001fffff44000000 - 84000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5057 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8400 -instret:5058 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8400 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5059 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8401 -instret:5060 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8401 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5061 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8402 -instret:5062 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8402 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 84030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03a } - 84030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5063 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8403 -instret:5064 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8403 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84040 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 -instret:5065 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8404 -instret:5066 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8404 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 0000000000000008000000001fffff44000000 - 84050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5067 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8405 -instret:5068 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8405 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000000400000001fffff44000000 - 84060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5069 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8406 -instret:5070 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8406 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001700, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 84070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5071 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8407 -instret:5072 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8407 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h377, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03a } - 84080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 84080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5073 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8408 -instret:5074 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8408 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000008000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 84090 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 - 84090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000040000000001fffff44000000 - 84100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03a } - 84100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 84100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001710 -After delta: vaddr = 0x80001710 - 84100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005c41710ffff1ffff806441610 - 84110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03a } - 84110 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001710 o: 'h0000000000000100 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001710 o: 'h0000000000000100 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001710, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 84110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 84110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000400000001fffff44000000 - 84120 : [doFinishMem] DTlbResp { resp: <'h0000000080001710,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001710 o: 'h0000000000000100 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001710, check_high: 'h00000000080001718, check_inclusive: True } }, specBits: 'h03a } - 84120 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 84120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 84120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 84130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001780, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 84130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03a } - 84130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001c00000001fffff44000000 - 84130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 84130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84130 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 84130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 84130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07a } - 84140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84140 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000002000000001fffff44000000 - 84140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 84150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84150 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 84150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5075 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8415 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 84160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 84160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84160 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 74 <= 40000000200005841610ffff1ffff806441610 - 84160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5076 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8416 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84170 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000001000000001fffff44000000 - 84170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84170 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 84170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5077 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8417 -instret:5078 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8417 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84180 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000002000000001fffff44000000 - 84180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5079 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8418 -instret:5080 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8418 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5081 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8419 -instret:5082 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8419 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 84200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 84200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5083 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8420 -instret:5084 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8420 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84210 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000400000001fffff44000000 -instret:5085 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8421 -instret:5086 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8421 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5087 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8422 -instret:5088 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8422 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h073, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 4d <= 0000000000000008000000001fffff44000000 - 84230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5089 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8423 -instret:5090 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8423 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h077, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001708, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 84240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h077, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5091 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8424 -instret:5092 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8424 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h077, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h077, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 84250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 84250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h076 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h076, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5093 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8425 -instret:5094 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8425 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 84260 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 - 84260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h076 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h076 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000008400000001fffff44000000 - 84270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 84270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 84270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 84270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000042000000001fffff44000000 - 84280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h072 } - 84280 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 84280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001718 -After delta: vaddr = 0x80001718 - 84280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 01 <= 40000000200005c61718ffff1ffff806441610 - 84290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 84290 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001718 o: 'h0000000000000108 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001718 o: 'h0000000000000108 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001718, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84290 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 84290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 84300 : [doFinishMem] DTlbResp { resp: <'h0000000080001718,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001718 o: 'h0000000000000108 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001718, check_high: 'h00000000080001720, check_inclusive: True } }, specBits: 'h072 } - 84300 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84300 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002000000001fffff44000000 - 84300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84300 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 84300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 84300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 84310 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 84310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84310 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 84310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 84320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84320 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 66 <= 40000000200005841610ffff1ffff806441610 - 84320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5095 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8432 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 84330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84330 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000001000000001fffff44000000 - 84330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5096 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8433 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84340 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 84340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5097 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8434 -instret:5098 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 8434 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 84350 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 84350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5099 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8435 -instret:5100 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 8435 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 84360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5101 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8436 -instret:5102 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 8436 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 84370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h06a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 84370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5103 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 8437 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h06a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 84380 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000800000001fffff44000000 - 84380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 84380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h06b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84390 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h06b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 45 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 59 <= 0000000000000008000000001fffff44000000 - 84400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 84400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 84400 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 84400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 4f <= 1000000000000000040000001fffff44000000 - 84410 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000001000000001fffff44000000 - 84410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h06a } - 84420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84430 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000800000001fffff44000000 -instret:5104 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8443 calling cycle -[RFile] wr_ 0: r 43 <= 0000000000000008800000001fffff44000000 - 84440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5105 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8444 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h06a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000044000000001fffff44000000 - 84450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h04a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001720 -After delta: vaddr = 0x80001720 -instret:5106 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8445 -instret:5107 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8445 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h04a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 40000000200005c81720ffff1ffff806441610 - 84460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001720 o: 'h0000000000000110 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001720 o: 'h0000000000000110 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001720, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h04a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5108 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 8446 -instret:5109 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 8446 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h04a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h04b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84470 : [doFinishMem] DTlbResp { resp: <'h0000000080001720,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001720 o: 'h0000000000000110 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001720, check_high: 'h00000000080001728, check_inclusive: True } }, specBits: 'h04a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 84470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h04b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:5110 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 8447 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1bb, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h04b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h04b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000000c00000001fffff44000000 - 84480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 84480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h04b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h04f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04a } - 84490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 84500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04b } - 84500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84500 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 84500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 84510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h04a } - 84510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84510 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 84510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84520 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 84520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84530 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 -instret:5111 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8453 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5112 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8454 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5113 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8455 -instret:5114 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8455 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 84560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5115 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8456 -instret:5116 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8456 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 84570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 84570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5117 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8457 -instret:5118 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8457 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h04c } - 84580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5119 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8458 -instret:5120 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8458 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h04c } - 84590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84590 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 84590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5121 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8459 -instret:5122 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8459 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h04c } - 84600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84600 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 53 <= 40000000200005841610ffff1ffff806441610 - 84600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 84600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5123 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8460 -instret:5124 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8460 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h04c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 84610 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001780, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 84610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04c } - 84610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84610 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000001000000001fffff44000000 - 84610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84610 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 84610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5125 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8461 -instret:5126 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8461 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h04d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h04d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001710, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 84620 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002000000001fffff44000000 - 84620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84620 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 84620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 84620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h04d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5127 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8462 -instret:5128 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8462 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h04d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h04d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000000400000001fffff44000000 - 84630 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000c00000001fffff44000000 - 84630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 84630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5129 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8463 -instret:5130 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8463 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 84640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h04f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04c } - 84650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 84650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h05e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84660 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84660 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 - 84660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 4e <= 0000000000000008000000001fffff44000000 - 84670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04c } - 84670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84670 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 84670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h04c } - 84680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84680 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000400000001fffff44000000 - 84680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84690 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 84690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04c } - 84700 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 -instret:5131 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8470 -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000008c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 84710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h04c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5132 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8471 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h05c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000000000046000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001728 -After delta: vaddr = 0x80001728 - 84720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5133 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8472 -instret:5134 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8472 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 44 <= 40000000200005ca1728ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001728 o: 'h0000000000000118 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001728 o: 'h0000000000000118 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001728, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 84730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5135 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8473 -instret:5136 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8473 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84740 : [doFinishMem] DTlbResp { resp: <'h0000000080001728,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001728 o: 'h0000000000000118 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001728, check_high: 'h00000000080001730, check_inclusive: True } }, specBits: 'h00c } - 84740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 84740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 84740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5137 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8474 -instret:5138 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8474 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 84750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5139 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8475 -instret:5140 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8475 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 84760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84760 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 84760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5141 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8476 -instret:5142 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8476 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 84770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84770 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200005841610ffff1ffff806441610 - 84770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 84770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5143 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8477 -instret:5144 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8477 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 84780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 84780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000001000000001fffff44000000 - 84780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84780 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 84780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5145 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8478 -instret:5146 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8478 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001718, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 84790 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 84790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5147 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8479 -instret:5148 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8479 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000000400000001fffff44000000 - 84800 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001000000001fffff44000000 - 84800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 84800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5149 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8480 -instret:5150 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8480 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 84810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3bb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 84820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 84820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84830 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84830 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001000000001fffff44000000 - 84830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 6e <= 0000000000000008000000001fffff44000000 - 84840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 84840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 84840 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 84840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 84850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84850 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000800000001fffff44000000 - 84850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 84860 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 84860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 84870 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 -instret:5151 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8487 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5152 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8488 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000000000009000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5153 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8489 -instret:5154 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8489 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000048000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001730 -After delta: vaddr = 0x80001730 - 84900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5155 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8490 -instret:5156 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8490 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 40000000200005cc1730ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001730 o: 'h0000000000000120 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001730 o: 'h0000000000000120 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001730, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 84910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5157 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8491 -instret:5158 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8491 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84920 : [doFinishMem] DTlbResp { resp: <'h0000000080001730,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001730 o: 'h0000000000000120 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001730, check_high: 'h00000000080001738, check_inclusive: True } }, specBits: 'h014 } - 84920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 84920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 84920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5159 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8492 -instret:5160 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8492 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 84930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 84930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 84930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5161 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8493 -instret:5162 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8493 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 84940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 84940 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 84940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5163 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8494 -instret:5164 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8494 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 84950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 84950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 84950 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 02 <= 40000000200005841610ffff1ffff806441610 - 84950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 84950 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 84950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5165 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8495 -instret:5166 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8495 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001720, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 84960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84960 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001000000001fffff44000000 - 84960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 84960 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 84960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5167 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8496 -instret:5168 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8496 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 - 84970 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002000000001fffff44000000 - 84970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 84970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5169 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8497 -instret:5170 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8497 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 84980 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 84980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 84980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 84980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3dd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 84990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 84990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 84990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 84990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 84990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 84990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 84990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 84990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 84990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85000 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85000 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 85000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 85000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 85010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 85010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85010 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 85010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7b <= 0000000000000008000000001fffff44000000 - 85020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 85020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85020 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000000c00000001fffff44000000 - 85020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85030 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 85030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 85040 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002000000001fffff44000000 -instret:5171 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8504 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5172 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8505 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000009400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5173 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8506 -instret:5174 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8506 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 000000000000004a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001738 -After delta: vaddr = 0x80001738 - 85070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5175 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8507 -instret:5176 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8507 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 40000000200005ce1738ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001738 o: 'h0000000000000128 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001738 o: 'h0000000000000128 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001738, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 85080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5177 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8508 -instret:5178 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8508 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85090 : [doFinishMem] DTlbResp { resp: <'h0000000080001738,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001738 o: 'h0000000000000128 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001738, check_high: 'h00000000080001740, check_inclusive: True } }, specBits: 'h030 } - 85090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 85090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 85090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5179 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8509 -instret:5180 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8509 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 85100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 85100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5181 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8510 -instret:5182 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8510 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 85110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 85110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 85110 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 85110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5183 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8511 -instret:5184 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8511 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 85120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 85120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85120 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 51 <= 40000000200005841610ffff1ffff806441610 - 85120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 85120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 85120 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 85120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5185 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8512 -instret:5186 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8512 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001728, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 85130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 85130 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001000000001fffff44000000 - 85130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 85130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 85130 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 85130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5187 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8513 -instret:5188 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8513 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000000000000400000001fffff44000000 - 85140 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 85140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 85140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5189 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8514 -instret:5190 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8514 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 85150 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001800000001fffff44000000 - 85150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2dd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 85160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 85160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 85160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85170 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85170 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000001800000001fffff44000000 - 85170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 85170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 85180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 85180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85180 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 85180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7d <= 0000000000000008000000001fffff44000000 - 85190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 85190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85190 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001000000001fffff44000000 - 85190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85200 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 85200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 85210 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000002000000001fffff44000000 -instret:5191 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8521 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5192 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8522 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000009800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h028, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5193 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8523 -instret:5194 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8523 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 000000000000004c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h028 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001740 -After delta: vaddr = 0x80001740 - 85240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5195 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8524 -instret:5196 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8524 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 40000000200005d01740ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001740 o: 'h0000000000000130 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001740 o: 'h0000000000000130 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h028 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001740, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 85250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5197 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8525 -instret:5198 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8525 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85260 : [doFinishMem] DTlbResp { resp: <'h0000000080001740,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001740 o: 'h0000000000000130 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001740, check_high: 'h00000000080001748, check_inclusive: True } }, specBits: 'h028 } - 85260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 85260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 85260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5199 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8526 -instret:5200 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8526 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 85270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 85270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5201 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8527 -instret:5202 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8527 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 85280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 85280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 85280 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 85280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5203 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8528 -instret:5204 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8528 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 85290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 85290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85290 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6a <= 40000000200005841610ffff1ffff806441610 - 85290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 85290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 85290 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 85290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5205 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8529 -instret:5206 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8529 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001730, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 85300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 85300 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001000000001fffff44000000 - 85300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 85300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 85300 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 85300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5207 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8530 -instret:5208 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8530 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000000400000001fffff44000000 - 85310 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 85310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 85310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5209 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8531 -instret:5210 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8531 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 85320 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001c00000001fffff44000000 - 85320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3dd, globalTaken: False, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 85330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 85330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 85330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85340 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85340 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001c00000001fffff44000000 - 85340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 85340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 85350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85350 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 85350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 68 <= 0000000000000008000000001fffff44000000 - 85360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 85360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85360 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000001400000001fffff44000000 - 85360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 85360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 85370 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 85370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 85380 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002000000001fffff44000000 -instret:5211 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8538 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5212 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8539 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000009c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5213 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8540 -instret:5214 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8540 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 000000000000004e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001748 -After delta: vaddr = 0x80001748 - 85410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5215 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8541 -instret:5216 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8541 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 49 <= 40000000200005d21748ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001748 o: 'h0000000000000138 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001748 o: 'h0000000000000138 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001748, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5217 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8542 -instret:5218 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8542 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85430 : [doFinishMem] DTlbResp { resp: <'h0000000080001748,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001748 o: 'h0000000000000138 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001748, check_high: 'h00000000080001750, check_inclusive: True } }, specBits: 'h00c } - 85430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5219 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8543 -instret:5220 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8543 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3ef, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 85440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 85440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5221 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8544 -instret:5222 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8544 -calling cycle - 85450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 85450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 85450 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 85450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5223 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8545 -instret:5224 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8545 -calling cycle - 85460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01e } - 85460 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000001000000001fffff44000000 - 85460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5225 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8546 -instret:5226 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8546 -calling cycle - 85470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001738, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 85470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5227 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8547 -instret:5228 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8547 -calling cycle - 85480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 85480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 85480 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 85480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 85480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5229 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8548 -instret:5230 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8548 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000001400000001fffff44000000 - 85490 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000003000000001fffff44000000 - 85490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 85490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 85500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 85500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 85500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 85500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 85510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 85510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 calling cycle - 85520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h03d } - 85520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 85520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 1: r 0c <= 00000000200003dc000000001fffff44000000 - 85530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h03c } - 85530 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85530 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 85530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 85540 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85540 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001800000001fffff44000000 - 85540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 85540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 85540 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 85540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000e2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85550 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000020000163800000001fffff44000000 - 85550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 85550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 85550 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 85550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85560 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000020000400000000001fffff44000000 - 85560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5231 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8556 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 85570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 -instret:5232 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8557 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ca }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 0000000020000164800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc -instret:5233 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8558 -instret:5234 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8558 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 1: r 7a <= 0000000020000166800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000674; 'h0; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } - 85590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h034 } - 85590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h858e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } -instret:5235 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8559 -instret:5236 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8559 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h08, t: 'h11 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 85610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } - 85610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } - 85610 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 85610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5237 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8561 -instret:5238 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8561 -calling cycle - 85620 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200004021008ffff1ffff805821008 -instret:5239 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8562 -instret:5240 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8562 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5241 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8563 -instret:5242 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8563 -calling cycle -instret:5243 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8564 -instret:5244 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8564 -calling cycle -instret:5245 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8565 -instret:5246 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8565 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001740, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 85660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5247 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8566 -instret:5248 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8566 -calling cycle - 85670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 85670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5249 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8567 -instret:5250 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8567 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 85680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -calling cycle - 85690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 85690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 85690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800017c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -calling cycle - 85700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800017c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 85700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 85700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 85710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85710 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 85710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 85720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800017c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800017c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 85720 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000001c00000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5251 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8574 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5252 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8575 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5253 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8576 -instret:5254 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8576 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5255 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8577 -instret:5256 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8577 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5257 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8578 -instret:5258 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8578 -calling cycle -instret:5259 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8579 -instret:5260 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8579 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5261 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8580 -instret:5262 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8580 +instret:599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3903 calling cycle -instret:5263 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8581 -instret:5264 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8581 calling cycle -instret:5265 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8582 -instret:5266 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8582 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001748, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 85830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5267 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8583 -instret:5268 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8583 calling cycle - 85840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 85840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5269 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8584 -instret:5270 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8584 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 85850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } calling cycle - 85860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 85860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 85870 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 85880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 85880 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 85880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 85890 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000002000000001fffff44000000 +instret:600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3912 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5271 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8591 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5272 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8592 calling cycle -instret:5273 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8593 -instret:5274 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 8593 calling cycle -instret:5275 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8594 -instret:5276 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 8594 calling cycle -instret:5277 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8595 -instret:5278 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 8595 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 85960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5279 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 8596 calling cycle - 85970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 85970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 85970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 85980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 85980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } +instret:601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3921 calling cycle - 85990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 85990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 85990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 85990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 85990 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 85990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 86000 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000001400000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5280 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8602 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h5; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } -instret:5281 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8603 calling cycle -[ROB incorrectSpec] 'h5 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:5282 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8605 calling cycle calling cycle +instret:602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3930 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 86120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 86130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h1ee, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000000000001fffff44000000 - 86140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 86150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 86150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:5283 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8615 -instret:5284 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 8615 -calling cycle - 86160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 86160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5285 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8616 -instret:5286 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [1]] 8616 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 86170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86180 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 86180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86190 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 86190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 86190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86200 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800017c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 86200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 86200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 86210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 86210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800017c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 86210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 86220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86220 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 86220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 86230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86230 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 - 86230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86230 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 86230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86240 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86240 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 59 <= 40000000200005841610ffff1ffff806441610 - 86240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86240 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 86240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86250 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86250 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 86250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86250 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 86250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } -instret:5287 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8625 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 86260 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002000000001fffff44000000 - 86260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 86260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 86260 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 86260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5288 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8626 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1ee, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 86270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86270 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000000000000001fffff44000000 - 86270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:5289 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8627 -instret:5290 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8627 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 86280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 86280 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 86280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5291 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8628 -instret:5292 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8628 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 86290 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000000000001fffff44000000 - 86290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5293 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8629 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 86300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 73 <= 000000000000000a000000001fffff44000000 - 86310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 86310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86310 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 86310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000400000001fffff44000000 - 86320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 86320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86320 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002000000001fffff44000000 - 86320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86320 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 86320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5294 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 8632 -instret:5295 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 8632 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 86330 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200005841610ffff1ffff806441610 - 86330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86330 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 86330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 86340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86340 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000001400000001fffff44000000 - 86340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 000000000000000a000000001fffff44000000 - 86350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 86350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86350 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 86350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000050000000001fffff44000000 -[RFile] wr_ 1: r 63 <= 0000000000000000400000001fffff44000000 - 86360 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000002000000001fffff44000000 - 86360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001750 -After delta: vaddr = 0x80001750 - 86360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5296 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 8636 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 1000000000000000040000001fffff44000000 -[RFile] wr_ 1: r 67 <= 40000000200005d41750ffff1ffff806441610 - 86370 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000400000001fffff44000000 - 86370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001750 o: 'h0000000000000140 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001750 o: 'h0000000000000140 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001750, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5297 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8637 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86380 : [doFinishMem] DTlbResp { resp: <'h0000000080001750,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001750 o: 'h0000000000000140 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001750, check_high: 'h00000000080001758, check_inclusive: True } }, specBits: 'h000 } - 86380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5298 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 8638 -instret:5299 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 8638 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 86390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5300 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 8639 -instret:5301 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 8639 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001750, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 86400 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 86400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5302 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8640 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 5d <= 000000000000000a000000001fffff44000000 - 86410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 86410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 86410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5303 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8641 -instret:5304 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8641 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 86420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86420 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 86420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5305 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8642 -instret:5306 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8642 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000000800000001fffff44000000 - 86430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 86430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86430 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 86430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86430 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 86430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 86440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 86440 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6e <= 40000000200005841610ffff1ffff806441610 - 86440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86440 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 86440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 000000000000000a400000001fffff44000000 - 86450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 86450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86450 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000001400000001fffff44000000 - 86450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 86450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000000000052000000001fffff44000000 - 86460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 86460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86460 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 86460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001758 -After delta: vaddr = 0x80001758 - 86460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 40000000200005d61758ffff1ffff806441610 - 86470 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86470 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 86470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001758 o: 'h0000000000000148 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001758 o: 'h0000000000000148 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001758, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86470 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 86470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000000400000001fffff44000000 - 86480 : [doFinishMem] DTlbResp { resp: <'h0000000080001758,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001758 o: 'h0000000000000148 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001758, check_high: 'h00000000080001760, check_inclusive: True } }, specBits: 'h008 } - 86480 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000400000001fffff44000000 - 86480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 86490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86490 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000800000001fffff44000000 - 86490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86500 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000000800000001fffff44000000 - 86500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5307 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8650 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 86510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 86510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5308 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8651 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 57 <= 000000000000000a000000001fffff44000000 - 86520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 86520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5309 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8652 -instret:5310 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8652 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 86530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86530 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 86530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5311 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8653 -instret:5312 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8653 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 86540 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 86540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86540 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 86540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5313 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8654 -instret:5314 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8654 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 86550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 86550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86550 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200005841610ffff1ffff806441610 - 86550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5315 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8655 -instret:5316 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8655 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 000000000000000a800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 86560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86560 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 86560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5317 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8656 -instret:5318 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8656 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000054000000001fffff44000000 - 86570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 86570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86570 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000001400000001fffff44000000 - 86570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86570 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 86570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001760 -After delta: vaddr = 0x80001760 - 86570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5319 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8657 -instret:5320 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8657 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 78 <= 40000000200005d81760ffff1ffff806441610 - 86580 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002000000001fffff44000000 - 86580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001760 o: 'h0000000000000150 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001760 o: 'h0000000000000150 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001760, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5321 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8658 -instret:5322 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8658 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 1000000000000000040000001fffff44000000 - 86590 : [doFinishMem] DTlbResp { resp: <'h0000000080001760,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001760 o: 'h0000000000000150 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001760, check_high: 'h00000000080001768, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001758, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 86590 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000c00000001fffff44000000 - 86590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5323 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8659 -instret:5324 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8659 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 86600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 86600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5325 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8660 -instret:5326 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8660 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 86610 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000c00000001fffff44000000 - 86610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 86620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 86620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7a <= 000000000000000a000000001fffff44000000 - 86630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 86630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 0000000000000001000000001fffff44000000 - 86640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 86640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86640 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 86640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 86650 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86650 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000800000001fffff44000000 - 86650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86650 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 86650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 86660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86660 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 86660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86660 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 86660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 000000000000000ac00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 86670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86670 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200005841610ffff1ffff806441610 - 86670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86670 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 86670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5327 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8667 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 86680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 86680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86680 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000001400000001fffff44000000 - 86680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86680 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 86680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5328 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8668 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 0000000000000056000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86690 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 - 86690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001768 -After delta: vaddr = 0x80001768 - 86690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5329 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8669 -instret:5330 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8669 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 66 <= 40000000200005da1768ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86700 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001000000001fffff44000000 - 86700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001768 o: 'h0000000000000158 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001768 o: 'h0000000000000158 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001768, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5331 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8670 -instret:5332 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8670 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2f7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86710 : [doFinishMem] DTlbResp { resp: <'h0000000080001768,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001768 o: 'h0000000000000158 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001768, check_high: 'h00000000080001770, check_inclusive: True } }, specBits: 'h010 } - 86710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5333 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8671 -instret:5334 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8671 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 86720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5335 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8672 -instret:5336 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8672 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 86730 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001000000001fffff44000000 - 86730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5337 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8673 -instret:5338 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8673 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7f <= 000000000000000a000000001fffff44000000 - 86740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 86740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5339 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8674 -instret:5340 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8674 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 86750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86750 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 86750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5341 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8675 -instret:5342 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8675 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000001400000001fffff44000000 - 86760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001760, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 86760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86760 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 86760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86760 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 86760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5343 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8676 -instret:5344 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8676 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 86770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 86770 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 68 <= 40000000200005841610ffff1ffff806441610 - 86770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86770 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 86770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5345 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8677 -instret:5346 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8677 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 000000000000000b000000001fffff44000000 - 86780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 86780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86780 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001400000001fffff44000000 - 86780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 86780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 0000000000000058000000001fffff44000000 - 86790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 86790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86790 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 86790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001770 -After delta: vaddr = 0x80001770 - 86790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 53 <= 40000000200005dc1770ffff1ffff806441610 - 86800 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000002000000001fffff44000000 - 86800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001770 o: 'h0000000000000160 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001770 o: 'h0000000000000160 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001770, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 86800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 - 86810 : [doFinishMem] DTlbResp { resp: <'h0000000080001770,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001770 o: 'h0000000000000160 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001770, check_high: 'h00000000080001778, check_inclusive: True } }, specBits: 'h018 } - 86810 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86810 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000001400000001fffff44000000 - 86810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h37b, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 86820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86820 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 86820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86830 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000000c00000001fffff44000000 - 86830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 86840 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001400000001fffff44000000 - 86840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 64 <= 000000000000000a000000001fffff44000000 - 86850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 86850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5347 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8685 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 86860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 86860 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 86860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5348 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8686 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86870 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002000000001fffff44000000 - 86870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5349 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8687 -instret:5350 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8687 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 86880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 86880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5351 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8688 -instret:5352 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8688 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 000000000000000b400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 86890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 86890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5353 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8689 -instret:5354 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8689 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 000000000000005a000000001fffff44000000 - 86900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 86900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001778 -After delta: vaddr = 0x80001778 - 86900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5355 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8690 -instret:5356 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8690 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 40000000200005de1778ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 86910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 86910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001778 o: 'h0000000000000168 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001778 o: 'h0000000000000168 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001778, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 86910 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 86910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5357 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8691 -instret:5358 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8691 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86920 : [doFinishMem] DTlbResp { resp: <'h0000000080001778,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001778 o: 'h0000000000000168 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001778, check_high: 'h00000000080001780, check_inclusive: True } }, specBits: 'h00c } - 86920 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5f <= 40000000200005841610ffff1ffff806441610 - 86920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 86920 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 86920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5359 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8692 -instret:5360 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8692 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 86930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 86930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86930 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001400000001fffff44000000 - 86930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5361 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8693 -instret:5362 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8693 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001768, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 86940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 86940 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 86940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5363 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8694 -instret:5364 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8694 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 0000000000000000400000001fffff44000000 - 86950 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 86950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 86950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5365 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8695 -instret:5366 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8695 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 86960 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001800000001fffff44000000 - 86960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 86960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h37b, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 86970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 86970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 86970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 86970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 86970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 86980 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 86980 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001800000001fffff44000000 - 86980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 86980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 86990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 86990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 86990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 86990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 86990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 86990 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 86990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 86990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0c <= 000000000000000a000000001fffff44000000 - 87000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 87000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87000 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001000000001fffff44000000 - 87000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87010 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 87010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 87020 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002000000001fffff44000000 -instret:5367 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8702 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5368 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8703 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 000000000000000b800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5369 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8704 -instret:5370 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8704 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 000000000000005c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001780 -After delta: vaddr = 0x80001780 - 87050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5371 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8705 -instret:5372 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8705 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 40000000200005e01780ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001780 o: 'h0000000000000170 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001780 o: 'h0000000000000170 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001780, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 87060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5373 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8706 -instret:5374 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8706 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87070 : [doFinishMem] DTlbResp { resp: <'h0000000080001780,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001780 o: 'h0000000000000170 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001780, check_high: 'h00000000080001788, check_inclusive: True } }, specBits: 'h024 } - 87070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 87070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 87070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5375 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8707 -instret:5376 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8707 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 87080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 87080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5377 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8708 -instret:5378 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8708 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 87090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 87090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 87090 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 87090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5379 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8709 -instret:5380 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8709 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 87100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 87100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87100 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200005841610ffff1ffff806441610 - 87100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 87100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 87100 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 87100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5381 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8710 -instret:5382 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8710 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001770, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 87110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 87110 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001400000001fffff44000000 - 87110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 87110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 87110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 87110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5383 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8711 -instret:5384 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8711 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000000400000001fffff44000000 - 87120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 87120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 87120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5385 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8712 -instret:5386 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8712 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 87130 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001c00000001fffff44000000 - 87130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h37b, globalTaken: False, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 87140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 87140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 87140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87150 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001c00000001fffff44000000 - 87150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 87150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 87160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87160 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 87160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 52 <= 000000000000000a000000001fffff44000000 - 87170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 87170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87170 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000001400000001fffff44000000 - 87170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7c <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87180 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 87180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 87190 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 -instret:5387 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8719 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5388 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8720 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 000000000000000bc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5389 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8721 -instret:5390 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8721 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 000000000000005e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001788 -After delta: vaddr = 0x80001788 - 87220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5391 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8722 -instret:5392 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8722 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 40000000200005e21788ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001788 o: 'h0000000000000178 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001788 o: 'h0000000000000178 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001788, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5393 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8723 -instret:5394 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8723 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87240 : [doFinishMem] DTlbResp { resp: <'h0000000080001788,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001788 o: 'h0000000000000178 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001788, check_high: 'h00000000080001790, check_inclusive: True } }, specBits: 'h030 } - 87240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5395 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8724 -instret:5396 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8724 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3f7, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 87250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 87250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5397 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8725 -instret:5398 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8725 -calling cycle - 87260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 87260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 87260 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 87260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5399 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8726 -instret:5400 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8726 -calling cycle - 87270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03a } - 87270 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000001400000001fffff44000000 - 87270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5401 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8727 -instret:5402 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8727 -calling cycle - 87280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001778, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 87280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5403 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8728 -instret:5404 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8728 -calling cycle - 87290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 87290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 87290 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 87290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 87290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5405 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8729 -instret:5406 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8729 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000001800000001fffff44000000 - 87300 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000003000000001fffff44000000 - 87300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 87300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 87310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 87310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 87320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 87320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 +instret:603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3939 calling cycle - 87330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h03d } - 87330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 1: r 42 <= 00000000200003dc000000001fffff44000000 - 87340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h03c } - 87340 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87340 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 87340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -calling cycle - 87350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87350 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001800000001fffff44000000 - 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 87350 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87360 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000020000163800000001fffff44000000 - 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 87360 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000d6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 87370 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000020000400000000001fffff44000000 - 87370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5407 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8737 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 87380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 -instret:5408 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8738 -calling cycle -[RFile] wr_ 1: r 49 <= 0000000020000167800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000058e; 'h1; InstTag { way: 'h0, ptr: 'h1f, t: 'h3e } - 87390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc -instret:5409 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8739 -instret:5410 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8739 calling cycle -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h1f, t: 'h3e } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5411 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8741 -instret:5412 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8741 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5413 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8742 -instret:5414 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8742 -calling cycle -instret:5415 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8743 -instret:5416 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8743 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5417 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8744 -instret:5418 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8744 -calling cycle -instret:5419 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8745 -instret:5420 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8745 -calling cycle -instret:5421 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8746 -instret:5422 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8746 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001780, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 87470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5423 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8747 -instret:5424 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8747 -calling cycle - 87480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 87480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5425 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8748 -instret:5426 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8748 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 87490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -calling cycle - 87500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 87500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -calling cycle - 87510 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 87510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 87510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle - 87520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87520 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 87520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 87530 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001800, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 87530 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001c00000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5427 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8755 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5428 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8756 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5429 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8757 -instret:5430 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8757 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5431 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8758 -instret:5432 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8758 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5433 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8759 -instret:5434 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8759 -calling cycle -instret:5435 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8760 -instret:5436 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8760 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5437 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8761 -instret:5438 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8761 calling cycle -instret:5439 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8762 -instret:5440 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8762 calling cycle -instret:5441 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8763 -instret:5442 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8763 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001788, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 87640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5443 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8764 -instret:5444 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8764 calling cycle - 87650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 87650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5445 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8765 -instret:5446 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8765 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 87660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } calling cycle - 87670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 87670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3948 calling cycle - 87680 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 87690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 87690 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 87690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 87700 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000002000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5447 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8772 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5448 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8773 calling cycle -instret:5449 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8774 -instret:5450 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 8774 calling cycle -instret:5451 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8775 -instret:5452 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 8775 calling cycle -instret:5453 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8776 -instret:5454 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 8776 +instret:605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3957 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 87770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5455 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 8777 calling cycle - 87780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 87780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 87780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 87790 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } calling cycle - 87800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 87800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 87800 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 87800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 87810 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000001800000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:5456 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8783 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 1] 'h1ffff0000000000000000000080000050; 'h2; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } -instret:5457 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8784 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h1c, t: 'h39 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +instret:606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3966 calling cycle -instret:5458 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8786 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 87930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 87940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h1bd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000000000000001fffff44000000 - 87950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 87950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3975 calling cycle - 87960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 87960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 87960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:5459 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8796 -instret:5460 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 8796 -calling cycle - 87970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 87970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5461 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8797 -instret:5462 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [1]] 8797 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 87980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 87980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 87990 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 87990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 87990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 87990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88000 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 88000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88010 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001800, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 88010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h005 } - 88010 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h004 } - 88020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080001800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 88030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88030 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 88040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88040 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88040 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88050 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200005841610ffff1ffff806441610 - 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88050 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88060 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001800000001fffff44000000 - 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88060 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } -instret:5463 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8806 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 88070 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002000000001fffff44000000 - 88070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } - 88070 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5464 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8807 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h1bd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 88080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88080 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 88080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } -instret:5465 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8808 -instret:5466 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8808 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a } - 88090 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5467 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8809 -instret:5468 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8809 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 88100 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000 - 88100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5469 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8810 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h000 } - 88110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 000000000000000c000000001fffff44000000 - 88120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h00c } - 88120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000400000001fffff44000000 - 88130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h008 } - 88130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002000000001fffff44000000 - 88130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88130 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5470 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [0]] 8813 -instret:5471 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [1]] 8813 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 88140 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200005841610ffff1ffff806441610 - 88140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 88150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001800000001fffff44000000 - 88150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000000c000000001fffff44000000 - 88160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 88160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88160 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 88160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000060000000001fffff44000000 -[RFile] wr_ 1: r 73 <= 0000000000000000400000001fffff44000000 - 88170 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000002000000001fffff44000000 - 88170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001790 -After delta: vaddr = 0x80001790 - 88170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5472 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 8817 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 1000000000000000040000001fffff44000000 -[RFile] wr_ 1: r 01 <= 40000000200005e41790ffff1ffff806441610 - 88180 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000400000001fffff44000000 - 88180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001790 o: 'h0000000000000180 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001790 o: 'h0000000000000180 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001790, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5473 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8818 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h2de, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88190 : [doFinishMem] DTlbResp { resp: <'h0000000080001790,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001790 o: 'h0000000000000180 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001790, check_high: 'h00000000080001798, check_inclusive: True } }, specBits: 'h000 } - 88190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h009 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5474 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [0]] 8819 -instret:5475 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [1]] 8819 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 88200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5476 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [0]] 8820 -instret:5477 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [1]] 8820 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00a } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001790, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 88210 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 88210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5478 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8821 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 77 <= 000000000000000c000000001fffff44000000 - 88220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h008 } - 88220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 88220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5479 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8822 -instret:5480 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8822 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 88230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88230 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 88230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5481 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8823 -instret:5482 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8823 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000000800000001fffff44000000 - 88240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h00c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 88240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88240 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 - 88240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88240 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 88240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 88250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 88250 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7f <= 40000000200005841610ffff1ffff806441610 - 88250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88250 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 88250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0a <= 000000000000000c400000001fffff44000000 - 88260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h00c } - 88260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88260 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000001800000001fffff44000000 - 88260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 88260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h00c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 0000000000000062000000001fffff44000000 - 88270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 88270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88270 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 88270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001798 -After delta: vaddr = 0x80001798 - 88270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200005e61798ffff1ffff806441610 - 88280 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88280 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 88280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001798 o: 'h0000000000000188 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001798 o: 'h0000000000000188 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001798, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88280 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 88280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000000400000001fffff44000000 - 88290 : [doFinishMem] DTlbResp { resp: <'h0000000080001798,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001798 o: 'h0000000000000188 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001798, check_high: 'h000000000800017a0, check_inclusive: True } }, specBits: 'h008 } - 88290 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000000400000001fffff44000000 - 88290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h2de, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00d } - 88300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88300 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000800000001fffff44000000 - 88300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88310 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000000800000001fffff44000000 - 88310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5483 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8831 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 88320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00e } - 88320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5484 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8832 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 0b <= 000000000000000c000000001fffff44000000 - 88330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h004 } - 88330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5485 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8833 -instret:5486 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8833 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 88340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88340 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 88340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5487 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8834 -instret:5488 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8834 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h004 } - 88350 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 88350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88350 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 88350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5489 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8835 -instret:5490 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8835 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 88360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h014 } - 88360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88360 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 64 <= 40000000200005841610ffff1ffff806441610 - 88360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5491 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8836 -instret:5492 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8836 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 000000000000000c800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 88370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 88370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5493 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8837 -instret:5494 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8837 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h014, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 0000000000000064000000001fffff44000000 - 88380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 88380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000001800000001fffff44000000 - 88380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88380 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 88380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017a0 -After delta: vaddr = 0x800017a0 - 88380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5495 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8838 -instret:5496 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8838 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h015, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 44 <= 40000000200005e817a0ffff1ffff806441610 - 88390 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002000000001fffff44000000 - 88390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000000800017a0 o: 'h0000000000000190 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017a0 o: 'h0000000000000190 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h015 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5497 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8839 -instret:5498 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8839 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h015, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 1000000000000000040000001fffff44000000 - 88400 : [doFinishMem] DTlbResp { resp: <'h00000000800017a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017a0 o: 'h0000000000000190 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017a0, check_high: 'h000000000800017a8, check_inclusive: True } }, specBits: 'h004 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001798, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 88400 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000c00000001fffff44000000 - 88400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h015 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5499 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8840 -instret:5500 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8840 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h2de, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h015 } - 88410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 88410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h017 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5501 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8841 -instret:5502 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8841 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 88420 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000c00000001fffff44000000 - 88420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h016 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h016 } - 88430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h016 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 88430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 40 <= 000000000000000c000000001fffff44000000 - 88440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h014 } - 88440 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h014 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000000000001000000001fffff44000000 - 88450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 88450 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h014 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88450 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 88450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h014 } - 88460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88460 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 - 88460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88460 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 88460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 88470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88470 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 88470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88470 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 88470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 000000000000000cc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 88480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88480 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0c <= 40000000200005841610ffff1ffff806441610 - 88480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88480 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 88480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5503 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8848 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 88490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 88490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88490 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001800000001fffff44000000 - 88490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88490 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 88490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h014, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5504 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8849 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 0000000000000066000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88500 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 88500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h010 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017a8 -After delta: vaddr = 0x800017a8 - 88500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5505 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8850 -instret:5506 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8850 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h019, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 6e <= 40000000200005ea17a8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88510 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000001000000001fffff44000000 - 88510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800017a8 o: 'h0000000000000198 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017a8 o: 'h0000000000000198 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h010 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h019 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5507 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8851 -instret:5508 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8851 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h2de, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 1000000000000000040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88520 : [doFinishMem] DTlbResp { resp: <'h00000000800017a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017a8 o: 'h0000000000000198 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017a8, check_high: 'h000000000800017b0, check_inclusive: True } }, specBits: 'h010 } - 88520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h019 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5509 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8852 -instret:5510 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8852 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h019 } - 88530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5511 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8853 -instret:5512 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8853 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01a } - 88540 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001000000001fffff44000000 - 88540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5513 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8854 -instret:5514 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8854 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 41 <= 000000000000000c000000001fffff44000000 - 88550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h018 } - 88550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5515 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8855 -instret:5516 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8855 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03c } - 88560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88560 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 88560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5517 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8856 -instret:5518 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8856 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000001400000001fffff44000000 - 88570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 88570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88570 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 88570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88570 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 88570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5519 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8857 -instret:5520 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8857 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 88580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h018 } - 88580 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 52 <= 40000000200005841610ffff1ffff806441610 - 88580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88580 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 88580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5521 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8858 -instret:5522 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8858 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000000000000d000000001fffff44000000 - 88590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 88590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88590 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000001800000001fffff44000000 - 88590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 88590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000068000000001fffff44000000 - 88600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 88600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88600 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 88600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017b0 -After delta: vaddr = 0x800017b0 - 88600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 1: r 7b <= 40000000200005ec17b0ffff1ffff806441610 - 88610 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002000000001fffff44000000 - 88610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800017b0 o: 'h00000000000001a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017b0 o: 'h00000000000001a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 88610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 - 88620 : [doFinishMem] DTlbResp { resp: <'h00000000800017b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017b0 o: 'h00000000000001a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017b0, check_high: 'h000000000800017b8, check_inclusive: True } }, specBits: 'h018 } - 88620 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88620 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001400000001fffff44000000 - 88620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h36f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01d } - 88630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88630 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 88630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88640 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000000c00000001fffff44000000 - 88640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 88650 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001400000001fffff44000000 - 88650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[RFile] wr_ 2: r 45 <= 000000000000000c000000001fffff44000000 - 88660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 88660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -instret:5523 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8866 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 88670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88670 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 88670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5524 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8867 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88680 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000002000000001fffff44000000 - 88680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5525 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8868 -instret:5526 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8868 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h00c } - 88690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5527 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8869 -instret:5528 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8869 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 000000000000000d400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5529 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8870 -instret:5530 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8870 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 000000000000006a000000001fffff44000000 - 88710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 88710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017b8 -After delta: vaddr = 0x800017b8 - 88710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5531 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8871 -instret:5532 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8871 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 40000000200005ee17b8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 88720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800017b8 o: 'h00000000000001a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017b8 o: 'h00000000000001a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88720 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 88720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5533 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8872 -instret:5534 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8872 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88730 : [doFinishMem] DTlbResp { resp: <'h00000000800017b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017b8 o: 'h00000000000001a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017b8, check_high: 'h000000000800017c0, check_inclusive: True } }, specBits: 'h00c } - 88730 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6b <= 40000000200005841610ffff1ffff806441610 - 88730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88730 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 88730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5535 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8873 -instret:5536 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8873 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 88740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88740 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000001800000001fffff44000000 - 88740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5537 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8874 -instret:5538 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8874 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 88750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88750 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 88750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5539 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8875 -instret:5540 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8875 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 0000000000000000400000001fffff44000000 - 88760 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 - 88760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 88760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5541 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8876 -instret:5542 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8876 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 88770 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001800000001fffff44000000 - 88770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h36f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 88780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 88780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88790 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88790 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001800000001fffff44000000 - 88790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 88800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 88800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88800 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 88800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 42 <= 000000000000000c000000001fffff44000000 - 88810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 88810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88810 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000001000000001fffff44000000 - 88810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88820 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 88820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 88830 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002000000001fffff44000000 -instret:5543 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8883 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5544 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8884 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 000000000000000d800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5545 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8885 -instret:5546 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8885 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 000000000000006c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017c0 -After delta: vaddr = 0x800017c0 - 88860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5547 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8886 -instret:5548 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8886 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 40000000200005f017c0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800017c0 o: 'h00000000000001b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017c0 o: 'h00000000000001b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 88870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5549 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8887 -instret:5550 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8887 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88880 : [doFinishMem] DTlbResp { resp: <'h00000000800017c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017c0 o: 'h00000000000001b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017c0, check_high: 'h000000000800017c8, check_inclusive: True } }, specBits: 'h024 } - 88880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 88880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 88880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5551 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8888 -instret:5552 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8888 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 88890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5553 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8889 -instret:5554 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8889 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 88900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 88900 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 88900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5555 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8890 -instret:5556 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8890 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 88910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 88910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88910 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200005841610ffff1ffff806441610 - 88910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 88910 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 88910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5557 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8891 -instret:5558 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8891 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 88920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88920 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000001800000001fffff44000000 - 88920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 88920 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 88920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5559 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8892 -instret:5560 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8892 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000000400000001fffff44000000 - 88930 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 88930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 88930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5561 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8893 -instret:5562 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8893 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 41 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 88940 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000001c00000001fffff44000000 - 88940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 88940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h36f, globalTaken: False, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 88950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 88950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 88950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 88950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88960 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000001c00000001fffff44000000 - 88960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 88960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 88970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 88970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 88970 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 88970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 88970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 05 <= 000000000000000c000000001fffff44000000 - 88980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 88980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 88980 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001400000001fffff44000000 - 88980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 88980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 88990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 88990 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 89000 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002000000001fffff44000000 -instret:5563 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8900 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5564 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8901 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 000000000000000dc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5565 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8902 -instret:5566 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8902 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 000000000000006e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017c8 -After delta: vaddr = 0x800017c8 - 89030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5567 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8903 -instret:5568 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8903 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 01 <= 40000000200005f217c8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h00000000800017c8 o: 'h00000000000001b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017c8 o: 'h00000000000001b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5569 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8904 -instret:5570 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8904 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89050 : [doFinishMem] DTlbResp { resp: <'h00000000800017c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017c8 o: 'h00000000000001b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017c8, check_high: 'h000000000800017d0, check_inclusive: True } }, specBits: 'h030 } - 89050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5571 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8905 -instret:5572 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8905 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3fb, globalTaken: True, localTaken: False, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 89060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5573 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8906 -instret:5574 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8906 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 89070 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5575 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8907 -instret:5576 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8907 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03a } - 89080 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001800000001fffff44000000 - 89080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5577 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8908 -instret:5578 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8908 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 89090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5579 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8909 -instret:5580 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8909 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h36f, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000000000000001fffff44000000 - 89100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 89100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 89100 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 89100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5581 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8910 -instret:5582 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8910 -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000001c00000001fffff44000000 - 89110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 89110 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000003000000001fffff44000000 - 89110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 89120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 89130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 89140 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 89140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89150 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 89160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 89160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89160 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000001800000001fffff44000000 - 89160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89160 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 89160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 89170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89170 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 89170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89170 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 89180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89180 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 0b <= 40000000200005841610ffff1ffff806441610 - 89180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5583 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8918 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 89190 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89190 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5584 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8919 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89200 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000002000000001fffff44000000 - 89200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5585 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8920 -instret:5586 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8920 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5587 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8921 -instret:5588 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8921 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5589 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8922 -instret:5590 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8922 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 89230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 89230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5591 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8923 -instret:5592 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8923 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89240 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000000000000001fffff44000000 -instret:5593 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8924 -instret:5594 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8924 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 000000000000000e000000001fffff44000000 - 89250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5595 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8925 -instret:5596 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8925 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 0000000000000000400000001fffff44000000 - 89260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5597 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8926 -instret:5598 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8926 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 89270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800017c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5599 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8927 -instret:5600 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8927 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 89280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800017c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 89280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800017c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5601 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8928 -instret:5602 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8928 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 000000000000000e000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 89290 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 - 89290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000070000000001fffff44000000 - 89300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 89300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 89300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017d0 -After delta: vaddr = 0x800017d0 - 89300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 40000000200005f417d0ffff1ffff806441610 - 89310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 89310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h00000000800017d0 o: 'h00000000000001c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017d0 o: 'h00000000000001c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 89310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 42 <= 0000000000000000400000001fffff44000000 - 89320 : [doFinishMem] DTlbResp { resp: <'h00000000800017d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017d0 o: 'h00000000000001c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017d0, check_high: 'h000000000800017d8, check_inclusive: True } }, specBits: 'h01e } - 89320 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89320 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 89320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 89320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 89330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001840, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 89330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 89330 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001c00000001fffff44000000 - 89330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89330 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 89340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89340 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002000000001fffff44000000 - 89340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 89350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89350 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5603 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8935 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 89360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 89360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89360 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 40 <= 40000000200005841610ffff1ffff806441610 - 89360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5604 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8936 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89370 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001c00000001fffff44000000 - 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5605 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8937 -instret:5606 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8937 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000002000000001fffff44000000 - 89380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5607 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8938 -instret:5608 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8938 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5609 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8939 -instret:5610 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8939 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 89400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04e } - 89400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5611 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8940 -instret:5612 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8940 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h04e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89410 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000000400000001fffff44000000 -instret:5613 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8941 -instret:5614 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5615 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8942 -instret:5616 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8942 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h04f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h04f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 74 <= 000000000000000e000000001fffff44000000 - 89430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5617 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8943 -instret:5618 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8943 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 89440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5619 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8944 -instret:5620 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8944 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04e } - 89450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5621 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8945 -instret:5622 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8945 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 89460 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 - 89460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 51 <= 000000000000000e400000001fffff44000000 - 89470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04e } - 89470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 89470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000072000000001fffff44000000 - 89480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h04e } - 89480 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 89480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h04e } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017d8 -After delta: vaddr = 0x800017d8 - 89480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h04e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 78 <= 40000000200005f617d8ffff1ffff806441610 - 89490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h06f } - 89490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800017d8 o: 'h00000000000001c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017d8 o: 'h00000000000001c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89490 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h04e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 89500 : [doFinishMem] DTlbResp { resp: <'h00000000800017d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017d8 o: 'h00000000000001c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017d8, check_high: 'h000000000800017e0, check_inclusive: True } }, specBits: 'h04e } - 89500 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89500 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000002000000001fffff44000000 - 89500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h04e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89500 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 89500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h06f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h04e } - 89510 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 89510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89510 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h06e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h06e } - 89520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89520 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 41 <= 40000000200005841610ffff1ffff806441610 - 89520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h06e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5623 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8952 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h06e } - 89530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89530 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000001c00000001fffff44000000 - 89530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5624 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8953 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h06e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89540 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 89540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5625 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8954 -instret:5626 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 8954 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 89550 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 89550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5627 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 8955 -instret:5628 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 8955 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 89560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5629 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 8956 -instret:5630 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 8956 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 89570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h066 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 89570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5631 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 8957 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h066, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 89580 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000800000001fffff44000000 - 89580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 89580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89590 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 73 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 08 <= 000000000000000e000000001fffff44000000 - 89600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 89600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 89600 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 89600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h067 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 77 <= 1000000000000000040000001fffff44000000 - 89610 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000001c00000001fffff44000000 - 89610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h067 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h066 } - 89620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89630 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000800000001fffff44000000 -instret:5632 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 8963 calling cycle -[RFile] wr_ 0: r 01 <= 000000000000000e800000001fffff44000000 - 89640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5633 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 8964 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000074000000001fffff44000000 - 89650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017e0 -After delta: vaddr = 0x800017e0 -instret:5634 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8965 -instret:5635 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8965 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 40000000200005f817e0ffff1ffff806441610 - 89660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800017e0 o: 'h00000000000001d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017e0 o: 'h00000000000001d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5636 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 8966 -instret:5637 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 8966 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h062, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89670 : [doFinishMem] DTlbResp { resp: <'h00000000800017e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017e0 o: 'h00000000000001d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017e0, check_high: 'h000000000800017e8, check_inclusive: True } }, specBits: 'h062 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 89670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:5638 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 8967 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h063, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000000c00000001fffff44000000 - 89680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 89680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h062 } - 89690 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 89700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h063 } - 89700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89700 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 89700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 89710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h062 } - 89710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89710 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000000000001fffff44000000 - 89710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89720 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89730 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 -instret:5639 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8973 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5640 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8974 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5641 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8975 -instret:5642 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8975 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 89760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5643 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8976 -instret:5644 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8976 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 89770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5645 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8977 -instret:5646 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8977 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h064 } - 89780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5647 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8978 -instret:5648 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8978 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h064 } - 89790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89790 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 89790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5649 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8979 -instret:5650 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8979 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 89800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89800 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 45 <= 40000000200005841610ffff1ffff806441610 - 89800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 89800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 89800 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 89800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5651 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8980 -instret:5652 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8980 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h064, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 89810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001840, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 89810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 89810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89810 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000001c00000001fffff44000000 - 89810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89810 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 89810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5653 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8981 -instret:5654 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8981 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 89820 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002000000001fffff44000000 - 89820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 89820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 89820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5655 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8982 -instret:5656 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8982 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h065, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000000000000400000001fffff44000000 - 89830 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000000c00000001fffff44000000 - 89830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 89830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800017d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h065 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5657 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 8983 -instret:5658 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 8983 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 89840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h065 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3b7, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 89850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 89850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 89850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h06e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89860 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89860 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000c00000001fffff44000000 - 89860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 6d <= 000000000000000e000000001fffff44000000 - 89870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 89870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 89870 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 89870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 89880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89880 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000400000001fffff44000000 - 89880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 5d <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 89890 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 89890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 89900 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002000000001fffff44000000 -instret:5659 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8990 -calling cycle -[RFile] wr_ 0: r 79 <= 000000000000000ec00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 89910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5660 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 8991 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 0000000000000076000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017e8 -After delta: vaddr = 0x800017e8 - 89920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5661 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 8992 -instret:5662 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 8992 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 40000000200005fa17e8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800017e8 o: 'h00000000000001d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017e8 o: 'h00000000000001d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 89930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5663 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 8993 -instret:5664 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 8993 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89940 : [doFinishMem] DTlbResp { resp: <'h00000000800017e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017e8 o: 'h00000000000001d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017e8, check_high: 'h000000000800017f0, check_inclusive: True } }, specBits: 'h024 } - 89940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 89940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 89940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5665 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 8994 -instret:5666 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 8994 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 89950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 89950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5667 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 8995 -instret:5668 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 8995 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 89960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 89960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 89960 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 89960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 89960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5669 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 8996 -instret:5670 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 8996 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 89970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 89970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 89970 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 42 <= 40000000200005841610ffff1ffff806441610 - 89970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 89970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 89970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 89970 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 89970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 89970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5671 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 8997 -instret:5672 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 8997 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 89980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 89980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 89980 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000001c00000001fffff44000000 - 89980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 89980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 89980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 89980 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 89980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5673 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 8998 -instret:5674 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 8998 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 89990 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 89990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 89990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5675 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 8999 -instret:5676 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 8999 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000000400000001fffff44000000 - 90000 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000001000000001fffff44000000 - 90000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800017d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5677 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9000 -instret:5678 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 90020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90030 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90030 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001000000001fffff44000000 - 90030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 5a <= 000000000000000e000000001fffff44000000 - 90040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 90040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90040 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 90040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 90050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90050 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000800000001fffff44000000 - 90050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90060 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 90060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 90070 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 -instret:5679 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9007 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5680 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9008 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 49 <= 000000000000000f000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5681 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9009 -instret:5682 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9009 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000078000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017f0 -After delta: vaddr = 0x800017f0 - 90100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5683 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9010 -instret:5684 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9010 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 40000000200005fc17f0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800017f0 o: 'h00000000000001e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017f0 o: 'h00000000000001e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 90110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5685 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9011 -instret:5686 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9011 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90120 : [doFinishMem] DTlbResp { resp: <'h00000000800017f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017f0 o: 'h00000000000001e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017f0, check_high: 'h000000000800017f8, check_inclusive: True } }, specBits: 'h00c } - 90120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 90120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5687 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9012 -instret:5688 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9012 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 90130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5689 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9013 -instret:5690 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9013 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 90140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90140 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 90140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5691 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9014 -instret:5692 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9014 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 90150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 90150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90150 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 05 <= 40000000200005841610ffff1ffff806441610 - 90150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90150 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 90150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5693 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9015 -instret:5694 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9015 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 90160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90160 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000001c00000001fffff44000000 - 90160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90160 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 90160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800017e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5695 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9016 -instret:5696 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9016 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000400000001fffff44000000 - 90170 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000002000000001fffff44000000 - 90170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800017e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800017e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5697 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9017 -instret:5698 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9017 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90180 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000001400000001fffff44000000 - 90180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 90190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90200 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90200 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000001400000001fffff44000000 - 90200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 90210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 90210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90210 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 90210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 6c <= 000000000000000e000000001fffff44000000 - 90220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 90220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90220 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000000c00000001fffff44000000 - 90220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90230 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 90230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 90240 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000002000000001fffff44000000 -instret:5699 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9024 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5700 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9025 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 000000000000000f400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5701 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9026 -instret:5702 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9026 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 000000000000007a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800017f8 -After delta: vaddr = 0x800017f8 - 90270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5703 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9027 -instret:5704 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9027 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 40000000200005fe17f8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h00000000800017f8 o: 'h00000000000001e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800017f8 o: 'h00000000000001e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800017f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 90280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5705 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9028 -instret:5706 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9028 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90290 : [doFinishMem] DTlbResp { resp: <'h00000000800017f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800017f8 o: 'h00000000000001e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800017f8, check_high: 'h00000000080001800, check_inclusive: True } }, specBits: 'h018 } - 90290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 90290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5707 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9029 -instret:5708 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9029 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 90300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5709 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9030 -instret:5710 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9030 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 90310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90310 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 90310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5711 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9031 -instret:5712 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9031 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 90320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 90320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90320 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200005841610ffff1ffff806441610 - 90320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90320 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 90320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5713 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9032 -instret:5714 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9032 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 90330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90330 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000001c00000001fffff44000000 - 90330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90330 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 90330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5715 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9033 -instret:5716 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9033 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000000400000001fffff44000000 - 90340 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 - 90340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800017e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5717 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9034 -instret:5718 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9034 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90350 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001800000001fffff44000000 - 90350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 90360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90370 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90370 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000001800000001fffff44000000 - 90370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3984 calling cycle - 90380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 90380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90380 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 90380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4a <= 000000000000000e000000001fffff44000000 - 90390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 90390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90390 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000001000000001fffff44000000 - 90390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90400 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 90400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 90410 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002000000001fffff44000000 -instret:5719 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9041 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5720 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9042 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 000000000000000f800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5721 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9043 -instret:5722 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9043 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 000000000000007c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001800 -After delta: vaddr = 0x80001800 - 90440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5723 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9044 -instret:5724 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9044 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 40000000200006001800ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001800 o: 'h00000000000001f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001800 o: 'h00000000000001f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001800, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 90450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5725 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9045 -instret:5726 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9045 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90460 : [doFinishMem] DTlbResp { resp: <'h0000000080001800,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001800 o: 'h00000000000001f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001800, check_high: 'h00000000080001808, check_inclusive: True } }, specBits: 'h030 } - 90460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 90460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5727 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9046 -instret:5728 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9046 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 90470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5729 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9047 -instret:5730 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9047 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 90480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90480 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5731 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9048 -instret:5732 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9048 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 90490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 90490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90490 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200005841610ffff1ffff806441610 - 90490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 90490 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 90490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5733 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9049 -instret:5734 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9049 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 90500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90500 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000001c00000001fffff44000000 - 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90500 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5735 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9050 -instret:5736 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9050 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 0000000000000000400000001fffff44000000 - 90510 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 90510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800017f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5737 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9051 -instret:5738 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9051 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90520 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000001c00000001fffff44000000 - 90520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3db, globalTaken: False, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 90530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90540 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90540 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000001c00000001fffff44000000 - 90540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 90550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90550 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 000000000000000e000000001fffff44000000 - 90560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 90560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90560 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001400000001fffff44000000 - 90560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 71 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90570 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 90580 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 -instret:5739 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9058 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5740 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9059 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 000000000000000fc00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5741 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9060 -instret:5742 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9060 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 52 <= 000000000000007e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001808 -After delta: vaddr = 0x80001808 - 90610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5743 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9061 -instret:5744 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9061 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 40000000200006021808ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001808 o: 'h00000000000001f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001808 o: 'h00000000000001f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001808, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5745 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9062 -instret:5746 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9062 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90630 : [doFinishMem] DTlbResp { resp: <'h0000000080001808,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001808 o: 'h00000000000001f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001808, check_high: 'h00000000080001810, check_inclusive: True } }, specBits: 'h024 } - 90630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5747 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9063 -instret:5748 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9063 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3fd, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 90640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5749 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9064 -instret:5750 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9064 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 90650 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5751 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9065 -instret:5752 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 90660 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000001c00000001fffff44000000 - 90660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5753 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9066 -instret:5754 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9066 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800017f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 90670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5755 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9067 -instret:5756 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9067 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h3ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000000000001fffff44000000 - 90680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 90680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 90680 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 90680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800017f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5757 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9068 -instret:5758 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9068 -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000002000000001fffff44000000 - 90690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 90690 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000003000000001fffff44000000 - 90690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800017f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800017f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 90710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 90720 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 90720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 90730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90730 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 90730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 90740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 90740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90740 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001800000001fffff44000000 - 90740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90740 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 90740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 90750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90750 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 90750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90750 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 90750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 90760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90760 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 08 <= 40000000200005841610ffff1ffff806441610 - 90760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5759 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9076 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 90770 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002000000001fffff44000000 - 90770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90770 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 90770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5760 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9077 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90780 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000002000000001fffff44000000 - 90780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5761 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9078 -instret:5762 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9078 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5763 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9079 -instret:5764 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9079 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5765 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9080 -instret:5766 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9080 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 90810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 90810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5767 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9081 -instret:5768 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9081 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90820 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000 -instret:5769 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9082 -instret:5770 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9082 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 02 <= 0000000000000010000000001fffff44000000 - 90830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5771 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9083 -instret:5772 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9083 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000000400000001fffff44000000 - 90840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5773 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9084 -instret:5774 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9084 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001800, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 90850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5775 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9085 -instret:5776 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9085 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 90860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 90860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 90860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5777 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9086 -instret:5778 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9086 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000010000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 90870 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 90870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000080000000001fffff44000000 - 90880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 90880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001810 -After delta: vaddr = 0x80001810 - 90880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200006041810ffff1ffff806441610 - 90890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 90890 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001810 o: 'h0000000000000200 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001810 o: 'h0000000000000200 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001810, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 90890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 90890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 90890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000000000000400000001fffff44000000 - 90900 : [doFinishMem] DTlbResp { resp: <'h0000000080001810,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001810 o: 'h0000000000000200 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001810, check_high: 'h00000000080001818, check_inclusive: True } }, specBits: 'h01e } - 90900 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 90900 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 90900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 90900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 90900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 90910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001880, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 90910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 90910 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000001c00000001fffff44000000 - 90910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 90910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 90910 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 90910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 90910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 90920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90920 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002000000001fffff44000000 - 90920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 90920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 90930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 90930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 90930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 90930 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 90930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5779 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9093 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 90940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 90940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 90940 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6d <= 40000000200005841610ffff1ffff806441610 - 90940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5780 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9094 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90950 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000002000000001fffff44000000 - 90950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 90950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 90950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 90950 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 90950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 90950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5781 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9095 -instret:5782 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9095 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90960 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000002000000001fffff44000000 - 90960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5783 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9096 -instret:5784 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9096 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5785 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9097 -instret:5786 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9097 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 90980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 90980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5787 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9098 -instret:5788 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9098 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h05a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 90990 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000000400000001fffff44000000 -instret:5789 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9099 -instret:5790 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9099 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5791 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9100 -instret:5792 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9100 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h05b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 4e <= 0000000000000010000000001fffff44000000 - 91010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5793 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9101 -instret:5794 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9101 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001808, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 91020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5795 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9102 -instret:5796 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9102 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h36d, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 91030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 91030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5797 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9103 -instret:5798 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9103 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 91040 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 91040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000010400000001fffff44000000 - 91050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 91050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 91050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 91050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 0000000000000082000000001fffff44000000 - 91060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05a } - 91060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 91060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001818 -After delta: vaddr = 0x80001818 - 91060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 7c <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 44 <= 40000000200006061818ffff1ffff806441610 - 91070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 91070 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001818 o: 'h0000000000000208 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001818 o: 'h0000000000000208 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001818, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91070 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 91070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 91080 : [doFinishMem] DTlbResp { resp: <'h0000000080001818,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001818 o: 'h0000000000000208 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001818, check_high: 'h00000000080001820, check_inclusive: True } }, specBits: 'h05a } - 91080 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91080 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000002000000001fffff44000000 - 91080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91080 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 91080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 91080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 91090 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 91090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91090 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 91090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 91100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91100 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5a <= 40000000200005841610ffff1ffff806441610 - 91100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5799 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9110 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 91110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91110 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002000000001fffff44000000 - 91110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5800 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9111 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91120 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 91120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5801 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9112 -instret:5802 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 9112 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91130 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 91130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5803 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9113 -instret:5804 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 9113 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 91140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5805 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 9114 -instret:5806 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 9114 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 91150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 91150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5807 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 9115 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91160 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000800000001fffff44000000 - 91160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 91160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91170 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 54 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 6a <= 0000000000000010000000001fffff44000000 - 91180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 91180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 91180 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 91180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 74 <= 1000000000000000040000001fffff44000000 - 91190 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 91190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 91200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91210 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000000800000001fffff44000000 -instret:5808 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 9121 calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000010800000001fffff44000000 - 91220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5809 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 9122 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 5b <= 0000000000000084000000001fffff44000000 - 91230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001820 -After delta: vaddr = 0x80001820 -instret:5810 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9123 -instret:5811 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9123 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 40000000200006081820ffff1ffff806441610 - 91240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001820 o: 'h0000000000000210 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001820 o: 'h0000000000000210 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001820, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5812 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 9124 -instret:5813 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 9124 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h062, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91250 : [doFinishMem] DTlbResp { resp: <'h0000000080001820,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001820 o: 'h0000000000000210 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001820, check_high: 'h00000000080001828, check_inclusive: True } }, specBits: 'h062 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 91250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:5814 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 9125 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h063, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000000c00000001fffff44000000 - 91260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 91260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h062 } - 91270 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 91280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h063 } - 91280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91280 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 91280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 91290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h062 } - 91290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91290 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000000000001fffff44000000 - 91290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91300 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 91300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91310 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 -instret:5815 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9131 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5816 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9132 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5817 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9133 -instret:5818 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9133 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 91340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5819 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9134 -instret:5820 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9134 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 91350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 91350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5821 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9135 -instret:5822 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9135 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h064 } - 91360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5823 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9136 -instret:5824 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9136 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h064 } - 91370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91370 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 91370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5825 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9137 -instret:5826 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9137 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 91380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91380 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6c <= 40000000200005841610ffff1ffff806441610 - 91380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 91380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5827 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9138 -instret:5828 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9138 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h064, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91390 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001880, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 91390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 91390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 91390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91390 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 91390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5829 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9139 -instret:5830 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9139 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001810, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 91400 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002000000001fffff44000000 - 91400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91400 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 91400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 91400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5831 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9140 -instret:5832 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9140 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h065, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000000400000001fffff44000000 - 91410 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000000c00000001fffff44000000 - 91410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 91410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h065 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5833 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9141 -instret:5834 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9141 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 91420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h065 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3f6, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 91430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 91430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h06e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91440 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91440 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000c00000001fffff44000000 - 91440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 50 <= 0000000000000010000000001fffff44000000 - 91450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 91450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91450 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 91450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 91460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91460 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000400000001fffff44000000 - 91460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91470 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 91470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 91480 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000002000000001fffff44000000 -instret:5835 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9148 -calling cycle -[RFile] wr_ 0: r 0a <= 0000000000000010c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 91490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5836 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9149 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 0000000000000086000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001828 -After delta: vaddr = 0x80001828 - 91500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5837 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9150 -instret:5838 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9150 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 400000002000060a1828ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001828 o: 'h0000000000000218 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001828 o: 'h0000000000000218 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001828, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 91510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5839 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9151 -instret:5840 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9151 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91520 : [doFinishMem] DTlbResp { resp: <'h0000000080001828,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001828 o: 'h0000000000000218 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001828, check_high: 'h00000000080001830, check_inclusive: True } }, specBits: 'h024 } - 91520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 91520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 91520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5841 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9152 -instret:5842 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9152 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 91530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5843 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9153 -instret:5844 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9153 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 91540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91540 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 91540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5845 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9154 -instret:5846 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9154 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 91550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91550 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4a <= 40000000200005841610ffff1ffff806441610 - 91550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91550 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 91550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5847 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9155 -instret:5848 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9155 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 91560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91560 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002000000001fffff44000000 - 91560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91560 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 91560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5849 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9156 -instret:5850 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9156 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001818, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 91570 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 91570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5851 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9157 -instret:5852 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9157 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000000400000001fffff44000000 - 91580 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000001000000001fffff44000000 - 91580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 91580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5853 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9158 -instret:5854 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9158 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 91590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3f6, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 91600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 91600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91610 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91610 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000001000000001fffff44000000 - 91610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 46 <= 0000000000000010000000001fffff44000000 - 91620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 91620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91620 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 91620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 91630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91630 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000000800000001fffff44000000 - 91630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91640 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 91640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 91650 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 -instret:5855 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9165 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5856 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9166 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 0000000000000011000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5857 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9167 -instret:5858 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9167 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000088000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001830 -After delta: vaddr = 0x80001830 - 91680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5859 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9168 -instret:5860 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9168 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 45 <= 400000002000060c1830ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001830 o: 'h0000000000000220 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001830 o: 'h0000000000000220 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001830, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 91690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5861 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9169 -instret:5862 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9169 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91700 : [doFinishMem] DTlbResp { resp: <'h0000000080001830,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001830 o: 'h0000000000000220 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001830, check_high: 'h00000000080001838, check_inclusive: True } }, specBits: 'h00c } - 91700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 91700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 91700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5863 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9170 -instret:5864 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9170 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 91710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5865 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9171 -instret:5866 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9171 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 91720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91720 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 91720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5867 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9172 -instret:5868 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9172 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 91730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91730 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7c <= 40000000200005841610ffff1ffff806441610 - 91730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91730 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 91730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5869 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9173 -instret:5870 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9173 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001820, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 91740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91740 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002000000001fffff44000000 - 91740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91740 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 91740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5871 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9174 -instret:5872 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9174 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 91750 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000002000000001fffff44000000 - 91750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 91750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5873 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9175 -instret:5874 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9175 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 91760 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000000000001400000001fffff44000000 - 91760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3b6, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 91770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 91770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91780 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91780 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000001400000001fffff44000000 - 91780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 91790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 91790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91790 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 91790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 63 <= 0000000000000010000000001fffff44000000 - 91800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 91800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91800 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000c00000001fffff44000000 - 91800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91810 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 91810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 91820 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000002000000001fffff44000000 -instret:5875 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9182 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5876 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9183 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 0000000000000011400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5877 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9184 -instret:5878 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9184 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 000000000000008a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001838 -After delta: vaddr = 0x80001838 - 91850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5879 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9185 -instret:5880 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9185 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 42 <= 400000002000060e1838ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001838 o: 'h0000000000000228 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001838 o: 'h0000000000000228 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001838, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 91860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5881 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9186 -instret:5882 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9186 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91870 : [doFinishMem] DTlbResp { resp: <'h0000000080001838,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001838 o: 'h0000000000000228 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001838, check_high: 'h00000000080001840, check_inclusive: True } }, specBits: 'h018 } - 91870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 91870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 91870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5883 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9187 -instret:5884 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9187 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 91880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5885 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9188 -instret:5886 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9188 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 91890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 91890 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 91890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5887 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9189 -instret:5888 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9189 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 91900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 91900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91900 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4b <= 40000000200005841610ffff1ffff806441610 - 91900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 91900 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 91900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5889 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9190 -instret:5890 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9190 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001828, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 91910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91910 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002000000001fffff44000000 - 91910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 91910 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 91910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5891 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9191 -instret:5892 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9191 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000000400000001fffff44000000 - 91920 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 - 91920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 91920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5893 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9192 -instret:5894 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9192 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 91930 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000001800000001fffff44000000 - 91930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 91930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2f6, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 91940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 91940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 91940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 91940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 91950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91950 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000001800000001fffff44000000 - 91950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 91950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 91960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 91960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 91960 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 91960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 91960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 55 <= 0000000000000010000000001fffff44000000 - 91970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 91970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 91970 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001000000001fffff44000000 - 91970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 91970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7b <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 91980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 91980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 91980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 91980 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 91980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 91990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 91990 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 -instret:5895 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9199 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5896 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9200 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000011800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5897 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9201 -instret:5898 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9201 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 000000000000008c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001840 -After delta: vaddr = 0x80001840 - 92020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5899 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9202 -instret:5900 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9202 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 40000000200006101840ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001840 o: 'h0000000000000230 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001840 o: 'h0000000000000230 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001840, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 92030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5901 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9203 -instret:5902 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9203 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92040 : [doFinishMem] DTlbResp { resp: <'h0000000080001840,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001840 o: 'h0000000000000230 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001840, check_high: 'h00000000080001848, check_inclusive: True } }, specBits: 'h030 } - 92040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 92040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5903 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9204 -instret:5904 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9204 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 92050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5905 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9205 -instret:5906 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9205 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 92060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92060 : [Ld resp] 'h03; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 92060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:5907 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9206 -instret:5908 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9206 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 92070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 92070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92070 : [doRespLdMem] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 77 <= 40000000200005841610ffff1ffff806441610 - 92070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 92070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 92070 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 92070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5909 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9207 -instret:5910 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9207 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001830, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 92080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92080 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002000000001fffff44000000 - 92080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92080 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 92080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5911 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9208 -instret:5912 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9208 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000000400000001fffff44000000 - 92090 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 92090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 92090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5913 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9209 -instret:5914 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9209 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 46 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 92100 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001c00000001fffff44000000 - 92100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fb, globalTaken: False, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 92110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 92110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92120 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92120 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000001c00000001fffff44000000 - 92120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 92130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92130 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 92130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 75 <= 0000000000000010000000001fffff44000000 - 92140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 92140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92140 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001400000001fffff44000000 - 92140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7d <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 92150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 92160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 -instret:5915 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9216 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5916 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9217 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000011c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5917 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9218 -instret:5918 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9218 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 000000000000008e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001848 -After delta: vaddr = 0x80001848 - 92190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5919 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9219 -instret:5920 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9219 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 40000000200006121848ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001848 o: 'h0000000000000238 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001848 o: 'h0000000000000238 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001848, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:5921 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9220 -instret:5922 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9220 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92210 : [doFinishMem] DTlbResp { resp: <'h0000000080001848,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001848 o: 'h0000000000000238 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001848, check_high: 'h00000000080001850, check_inclusive: True } }, specBits: 'h024 } - 92210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5923 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9221 -instret:5924 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9221 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3fe, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 92220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:5925 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9222 -instret:5926 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9222 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 92230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 92230 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 92230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:5927 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9223 -instret:5928 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9223 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 92240 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000002000000001fffff44000000 - 92240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5929 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9224 -instret:5930 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9224 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001838, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 92250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:5931 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9225 -instret:5932 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9225 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h3fb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000000000000000000001fffff44000000 - 92260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 92260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 92260 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 92260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5933 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9226 -instret:5934 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9226 -calling cycle -[RFile] wr_ 1: r 70 <= 0000000000000002400000001fffff44000000 - 92270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 92270 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000003000000001fffff44000000 - 92270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000009 o: 'h0000000000000009 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 92270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 92280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 92290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 92290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 92300 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 92300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92310 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 92310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92310 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 92310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 92320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 92320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92320 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001800000001fffff44000000 - 92320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92320 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 92320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 92330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92330 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 92330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92330 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 92330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 92340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92340 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 6a <= 40000000200005841610ffff1ffff806441610 - 92340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5935 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9234 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 92350 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002400000001fffff44000000 - 92350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92350 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 92350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5936 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9235 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92360 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000002000000001fffff44000000 - 92360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5937 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9236 -instret:5938 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9236 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5939 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9237 -instret:5940 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9237 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5941 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9238 -instret:5942 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9238 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 92390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 92390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5943 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9239 -instret:5944 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9239 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92400 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000 -instret:5945 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9240 -instret:5946 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9240 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 68 <= 0000000000000012000000001fffff44000000 - 92410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5947 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9241 -instret:5948 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9241 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 0000000000000000400000001fffff44000000 - 92420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5949 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9242 -instret:5950 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9242 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001840, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 92430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5951 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9243 -instret:5952 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9243 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3db, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 92440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 92440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5953 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9244 -instret:5954 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9244 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000012000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 92450 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000000000000001fffff44000000 - 92450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000000000090000000001fffff44000000 - 92460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 92460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 92460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001850 -After delta: vaddr = 0x80001850 - 92460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800018c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 40000000200006141850ffff1ffff806441610 - 92470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 92470 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001850 o: 'h0000000000000240 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001850 o: 'h0000000000000240 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001850, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800018c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 92470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 92470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000000000000400000001fffff44000000 - 92480 : [doFinishMem] DTlbResp { resp: <'h0000000080001850,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001850 o: 'h0000000000000240 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001850, check_high: 'h00000000080001858, check_inclusive: True } }, specBits: 'h01e } - 92480 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92480 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 92480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 92480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 92490 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800018c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800018c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 92490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 92490 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000001c00000001fffff44000000 - 92490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 92490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92490 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 92490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 92500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92500 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002000000001fffff44000000 - 92500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 92510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92510 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 92510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:5955 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9251 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 92520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 92520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92520 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 50 <= 40000000200005841610ffff1ffff806441610 - 92520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5956 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9252 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92530 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000002400000001fffff44000000 - 92530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92530 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 92530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5957 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9253 -instret:5958 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9253 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92540 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000002000000001fffff44000000 - 92540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5959 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9254 -instret:5960 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9254 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5961 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9255 -instret:5962 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9255 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 92560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 92560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:5963 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9256 -instret:5964 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9256 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h05a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92570 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000000400000001fffff44000000 -instret:5965 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9257 -instret:5966 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9257 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5967 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9258 -instret:5968 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9258 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h05b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 7a <= 0000000000000012000000001fffff44000000 - 92590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5969 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9259 -instret:5970 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9259 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001848, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 92600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:5971 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9260 -instret:5972 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9260 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h37b, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 92610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 92610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5973 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9261 -instret:5974 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9261 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 92620 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 92620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000012400000001fffff44000000 - 92630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 92630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 92630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 92630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 0000000000000092000000001fffff44000000 - 92640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05a } - 92640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 92640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001858 -After delta: vaddr = 0x80001858 - 92640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 66 <= 40000000200006161858ffff1ffff806441610 - 92650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 92650 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001858 o: 'h0000000000000248 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001858 o: 'h0000000000000248 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001858, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92650 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 92650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 92660 : [doFinishMem] DTlbResp { resp: <'h0000000080001858,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001858 o: 'h0000000000000248 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001858, check_high: 'h00000000080001860, check_inclusive: True } }, specBits: 'h05a } - 92660 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92660 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000002000000001fffff44000000 - 92660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92660 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 92660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 92670 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 92670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92670 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 92670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 92680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92680 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 46 <= 40000000200005841610ffff1ffff806441610 - 92680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5975 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9268 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 92690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92690 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002400000001fffff44000000 - 92690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:5976 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9269 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92700 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 92700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5977 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9270 -instret:5978 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 9270 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 92710 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 92710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:5979 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9271 -instret:5980 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 9271 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 92720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:5981 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 9272 -instret:5982 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 9272 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 92730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 92730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:5983 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 9273 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 92740 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000000800000001fffff44000000 - 92740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 92740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92750 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 4c <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 4f <= 0000000000000012000000001fffff44000000 - 92760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 92760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 92760 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 92760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 4e <= 1000000000000000040000001fffff44000000 - 92770 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002400000001fffff44000000 - 92770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 92780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3993 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92790 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000000800000001fffff44000000 -instret:5984 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 9279 calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000012800000001fffff44000000 - 92800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5985 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 9280 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 47 <= 0000000000000094000000001fffff44000000 - 92810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001860 -After delta: vaddr = 0x80001860 -instret:5986 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9281 -instret:5987 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9281 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7f <= 40000000200006181860ffff1ffff806441610 - 92820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001860 o: 'h0000000000000250 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001860 o: 'h0000000000000250 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001860, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5988 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 9282 -instret:5989 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 9282 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h062, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92830 : [doFinishMem] DTlbResp { resp: <'h0000000080001860,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001860 o: 'h0000000000000250 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001860, check_high: 'h00000000080001868, check_inclusive: True } }, specBits: 'h062 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 92830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:5990 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 9283 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1fd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h063, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000000c00000001fffff44000000 - 92840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 92840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h062 } - 92850 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 92860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h063 } - 92860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 92860 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } - 92860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 92870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h062 } - 92870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92870 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000000000001fffff44000000 - 92870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 92880 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 92880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92890 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 -instret:5991 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9289 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:5992 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9290 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5993 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9291 -instret:5994 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9291 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 92920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5995 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9292 -instret:5996 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9292 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 92930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 92930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:5997 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9293 -instret:5998 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9293 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h064 } - 92940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 92940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:5999 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9294 -instret:6000 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9294 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 92950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h064 } - 92950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 92950 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 92950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 92950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6001 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9295 -instret:6002 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9295 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 92960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 92960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 92960 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 63 <= 40000000200005841610ffff1ffff806441610 - 92960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 92960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 92960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 92960 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 92960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6003 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9296 -instret:6004 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9296 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h064, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 92970 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800018c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 92970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 92970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 92970 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002400000001fffff44000000 - 92970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 92970 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 92970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6005 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9297 -instret:6006 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9297 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001850, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 92980 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002000000001fffff44000000 - 92980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 92980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800018c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 92980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 92980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6007 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9298 -instret:6008 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9298 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h065, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000000400000001fffff44000000 - 92990 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7c <= 0000000000000000c00000001fffff44000000 - 92990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 92990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 92990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 92990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 92990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 92990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h065 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6009 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9299 -instret:6010 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9299 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h065 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3fd, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 93010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h06e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93020 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93020 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000c00000001fffff44000000 - 93020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 5b <= 0000000000000012000000001fffff44000000 - 93030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 93030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93030 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 93030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 93040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93040 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000400000001fffff44000000 - 93040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93050 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 93050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 93060 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000000000002000000001fffff44000000 -instret:6011 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9306 -calling cycle -[RFile] wr_ 0: r 51 <= 0000000000000012c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 93070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6012 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9307 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000096000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001868 -After delta: vaddr = 0x80001868 - 93080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6013 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9308 -instret:6014 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9308 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 400000002000061a1868ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001868 o: 'h0000000000000258 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001868 o: 'h0000000000000258 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001868, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 93090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6015 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9309 -instret:6016 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9309 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93100 : [doFinishMem] DTlbResp { resp: <'h0000000080001868,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001868 o: 'h0000000000000258 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001868, check_high: 'h00000000080001870, check_inclusive: True } }, specBits: 'h024 } - 93100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 93100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6017 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9310 -instret:6018 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9310 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 93110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6019 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9311 -instret:6020 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9311 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 93120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93120 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 93120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6021 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9312 -instret:6022 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 93130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93130 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 55 <= 40000000200005841610ffff1ffff806441610 - 93130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93130 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 93130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6023 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9313 -instret:6024 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9313 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 93140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 93140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93140 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002400000001fffff44000000 - 93140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93140 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 93140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6025 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9314 -instret:6026 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9314 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001858, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 93150 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 93150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6027 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9315 -instret:6028 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9315 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000000400000001fffff44000000 - 93160 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000001000000001fffff44000000 - 93160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 93160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6029 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9316 -instret:6030 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9316 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3ed, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 93180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93190 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000001000000001fffff44000000 - 93190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 58 <= 0000000000000012000000001fffff44000000 - 93200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 93200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93200 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 93200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 93210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93210 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000000800000001fffff44000000 - 93210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93220 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 93220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 93230 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 -instret:6031 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9323 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6032 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9324 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 0000000000000013000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6033 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9325 -instret:6034 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9325 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000098000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001870 -After delta: vaddr = 0x80001870 - 93260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6035 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9326 -instret:6036 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9326 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 400000002000061c1870ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001870 o: 'h0000000000000260 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001870 o: 'h0000000000000260 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001870, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 93270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6037 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9327 -instret:6038 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9327 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93280 : [doFinishMem] DTlbResp { resp: <'h0000000080001870,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001870 o: 'h0000000000000260 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001870, check_high: 'h00000000080001878, check_inclusive: True } }, specBits: 'h00c } - 93280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 93280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6039 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9328 -instret:6040 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9328 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 93290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6041 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9329 -instret:6042 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9329 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 93300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93300 : [Ld resp] 'h02; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 93300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6043 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9330 -instret:6044 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9330 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 93310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 93310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93310 : [doRespLdMem] 'h02; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 75 <= 40000000200005841610ffff1ffff806441610 - 93310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93310 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 93310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6045 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9331 -instret:6046 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9331 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001860, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 93320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93320 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002400000001fffff44000000 - 93320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93320 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 93320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6047 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9332 -instret:6048 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9332 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 93330 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000002000000001fffff44000000 - 93330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 93330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6049 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9333 -instret:6050 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9333 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93340 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000000000001400000001fffff44000000 - 93340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3bd, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 93350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93360 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93360 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000001400000001fffff44000000 - 93360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 93370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 93370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93370 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 93370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 73 <= 0000000000000012000000001fffff44000000 - 93380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 93380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93380 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000000c00000001fffff44000000 - 93380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93390 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 93390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 93400 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000002000000001fffff44000000 -instret:6051 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9340 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6052 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9341 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000013400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6053 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9342 -instret:6054 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9342 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 000000000000009a000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001878 -After delta: vaddr = 0x80001878 - 93430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6055 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9343 -instret:6056 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9343 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 400000002000061e1878ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001878 o: 'h0000000000000268 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001878 o: 'h0000000000000268 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001878, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 93440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6057 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9344 -instret:6058 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9344 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93450 : [doFinishMem] DTlbResp { resp: <'h0000000080001878,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001878 o: 'h0000000000000268 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001878, check_high: 'h00000000080001880, check_inclusive: True } }, specBits: 'h018 } - 93450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 93450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6059 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9345 -instret:6060 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9345 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 93460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6061 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9346 -instret:6062 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9346 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 93470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93470 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 93470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6063 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9347 -instret:6064 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9347 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 93480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 93480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93480 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 70 <= 40000000200005841610ffff1ffff806441610 - 93480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93480 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 93480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6065 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9348 -instret:6066 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9348 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001868, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 93490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93490 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002400000001fffff44000000 - 93490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93490 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 93490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6067 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9349 -instret:6068 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9349 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000000400000001fffff44000000 - 93500 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 - 93500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 93500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080001868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6069 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9350 -instret:6070 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9350 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93510 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000001800000001fffff44000000 - 93510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 93520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93530 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93530 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000001800000001fffff44000000 - 93530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 93540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 93540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93540 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 93540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 53 <= 0000000000000012000000001fffff44000000 - 93550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 93550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93550 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001000000001fffff44000000 - 93550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 64 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93560 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 93560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 93570 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002000000001fffff44000000 -instret:6071 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9357 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6072 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9358 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000013800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6073 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9359 -instret:6074 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9359 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7d <= 000000000000009c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001880 -After delta: vaddr = 0x80001880 - 93600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6075 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9360 -instret:6076 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9360 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 40000000200006201880ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001880 o: 'h0000000000000270 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001880 o: 'h0000000000000270 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001880, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 93610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6077 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9361 -instret:6078 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9361 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93620 : [doFinishMem] DTlbResp { resp: <'h0000000080001880,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001880 o: 'h0000000000000270 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001880, check_high: 'h00000000080001888, check_inclusive: True } }, specBits: 'h030 } - 93620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 93620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6079 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9362 -instret:6080 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9362 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 93630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6081 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9363 -instret:6082 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9363 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 93640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93640 : [Ld resp] 'h10; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 93640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6083 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9364 -instret:6084 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9364 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 93650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 93650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93650 : [doRespLdMem] 'h10; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 74 <= 40000000200005841610ffff1ffff806441610 - 93650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 93650 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 93650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6085 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9365 -instret:6086 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9365 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001870, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 93660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93660 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002400000001fffff44000000 - 93660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93660 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 93660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6087 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9366 -instret:6088 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9366 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000000400000001fffff44000000 - 93670 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 - 93670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 93670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6089 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9367 -instret:6090 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9367 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 58 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93680 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000000000001c00000001fffff44000000 - 93680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fe, globalTaken: False, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 93690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93700 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93700 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000001c00000001fffff44000000 - 93700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 93710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93710 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 93710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 71 <= 0000000000000012000000001fffff44000000 - 93720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 93720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93720 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001400000001fffff44000000 - 93720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93730 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 93730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 93740 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000000000002000000001fffff44000000 -instret:6091 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9374 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6092 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9375 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000013c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6093 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9376 -instret:6094 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9376 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 000000000000009e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001888 -After delta: vaddr = 0x80001888 - 93770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6095 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9377 -instret:6096 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9377 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 40000000200006221888ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001888 o: 'h0000000000000278 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001888 o: 'h0000000000000278 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001888, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:6097 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9378 -instret:6098 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9378 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93790 : [doFinishMem] DTlbResp { resp: <'h0000000080001888,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001888 o: 'h0000000000000278 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001888, check_high: 'h00000000080001890, check_inclusive: True } }, specBits: 'h024 } - 93790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6099 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9379 -instret:6100 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9379 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 93800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:6101 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9380 -instret:6102 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9380 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 93810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 93810 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 93810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:6103 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9381 -instret:6104 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9381 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 93820 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000002400000001fffff44000000 - 93820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6105 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9382 -instret:6106 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9382 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001878, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 93830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:6107 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9383 -instret:6108 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9383 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h3f6, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000000000000000000001fffff44000000 - 93840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 93840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 93840 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 93840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6109 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9384 -instret:6110 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9384 -calling cycle -[RFile] wr_ 1: r 69 <= 0000000000000002800000001fffff44000000 - 93850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 93850 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000003000000001fffff44000000 - 93850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 93850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 93850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 93860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 93870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 93870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 93870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 93880 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 93880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 93890 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 93890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 93890 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 93890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 93890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 93890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 93900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 93900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93900 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001800000001fffff44000000 - 93900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 93900 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 93900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 93900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 93900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 93910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 93910 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 93910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 93910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 93910 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 93910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 93920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 93920 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4f <= 40000000200005841610ffff1ffff806441610 - 93920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6111 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9392 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 93930 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002800000001fffff44000000 - 93930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 93930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 93930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 93930 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } - 93930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6112 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9393 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93940 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000002000000001fffff44000000 - 93940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6113 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9394 -instret:6114 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9394 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6115 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9395 -instret:6116 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9395 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6117 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9396 -instret:6118 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9396 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 93970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 93970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6119 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9397 -instret:6120 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9397 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 93980 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 -instret:6121 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9398 -instret:6122 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9398 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 52 <= 0000000000000014000000001fffff44000000 - 93990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6123 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9399 -instret:6124 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9399 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4e <= 0000000000000000400000001fffff44000000 - 94000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6125 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9400 -instret:6126 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9400 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001880, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 94010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6127 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9401 -instret:6128 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9401 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3de, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 94020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 94020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6129 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9402 -instret:6130 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9402 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000014000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 94030 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000000000000001fffff44000000 - 94030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 00000000000000a0000000001fffff44000000 - 94040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 94040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 94040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001890 -After delta: vaddr = 0x80001890 - 94040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 40000000200006241890ffff1ffff806441610 - 94050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 94050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001890 o: 'h0000000000000280 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001890 o: 'h0000000000000280 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001890, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 94050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 94050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000000400000001fffff44000000 - 94060 : [doFinishMem] DTlbResp { resp: <'h0000000080001890,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001890 o: 'h0000000000000280 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001890, check_high: 'h00000000080001898, check_inclusive: True } }, specBits: 'h01e } - 94060 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94060 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 94060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 94060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 94070 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001900, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 94070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 94070 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000001c00000001fffff44000000 - 94070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 94070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94070 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 94070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 94070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 94080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94080 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002000000001fffff44000000 - 94080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 94090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94090 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 94090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6131 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9409 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 94100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 94100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94100 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5b <= 40000000200005841610ffff1ffff806441610 - 94100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6132 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9410 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94110 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002800000001fffff44000000 - 94110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 94110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6133 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9411 -instret:6134 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9411 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94120 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000002000000001fffff44000000 - 94120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6135 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9412 -instret:6136 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9412 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6137 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9413 -instret:6138 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9413 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 94140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 94140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6139 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9414 -instret:6140 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9414 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h05a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94150 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000400000001fffff44000000 -instret:6141 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9415 -instret:6142 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9415 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6143 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9416 -instret:6144 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9416 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h05b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 40 <= 0000000000000014000000001fffff44000000 - 94170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6145 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9417 -instret:6146 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9417 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001888, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 94180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6147 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9418 -instret:6148 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9418 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 94190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 94190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6149 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9419 -instret:6150 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9419 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 94200 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000400000001fffff44000000 - 94200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000000000014400000001fffff44000000 - 94210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 94210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 94210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 94210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 00000000000000a2000000001fffff44000000 - 94220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05a } - 94220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 94220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001898 -After delta: vaddr = 0x80001898 - 94220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 6e <= 40000000200006261898ffff1ffff806441610 - 94230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 94230 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001898 o: 'h0000000000000288 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001898 o: 'h0000000000000288 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001898, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94230 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 94230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 94240 : [doFinishMem] DTlbResp { resp: <'h0000000080001898,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001898 o: 'h0000000000000288 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001898, check_high: 'h000000000800018a0, check_inclusive: True } }, specBits: 'h05a } - 94240 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94240 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000002000000001fffff44000000 - 94240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94240 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 94240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 94240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 94250 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 94250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94250 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 94260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94260 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 58 <= 40000000200005841610ffff1ffff806441610 - 94260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6151 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9426 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 94270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94270 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002800000001fffff44000000 - 94270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6152 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9427 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94280 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6153 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9428 -instret:6154 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 9428 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 94290 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 94290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6155 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9429 -instret:6156 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 9429 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 94300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6157 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 9430 -instret:6158 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 9430 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 94310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 94310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:6159 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 9431 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 94320 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000000800000001fffff44000000 - 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94330 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 02 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 4d <= 0000000000000014000000001fffff44000000 - 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 94340 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 7a <= 1000000000000000040000001fffff44000000 - 94350 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002800000001fffff44000000 - 94350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 94360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94370 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000000800000001fffff44000000 -instret:6160 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 9437 calling cycle -[RFile] wr_ 0: r 78 <= 0000000000000014800000001fffff44000000 - 94380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6161 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 9438 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12903 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12957 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12966 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12975 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12984 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12993 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:1999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21903 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21957 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21966 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21975 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21984 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21993 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:2999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30903 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30957 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30966 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30975 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30984 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30993 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:3999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39903 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39957 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39966 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39975 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39984 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39993 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:4999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48903 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48957 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48966 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48975 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48984 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48993 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49002 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49011 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49020 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49029 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49038 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49047 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49056 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49065 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49074 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49083 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49092 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49101 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49110 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49119 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49128 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49137 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49146 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49155 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49200 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49209 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49218 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49227 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49236 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49245 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49254 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49263 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49272 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49281 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49290 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49299 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49308 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49317 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49326 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49335 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49344 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49353 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49362 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49371 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49380 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49389 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49398 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49407 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49461 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49470 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49479 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49488 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49497 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49506 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49515 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49524 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49533 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49542 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49551 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49560 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49569 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49578 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49587 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49596 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49605 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49614 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49623 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49632 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49641 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49650 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49659 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49668 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49677 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49686 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49695 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49704 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49713 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49722 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49731 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49740 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49749 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49758 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49776 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49785 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49794 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49803 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49812 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49821 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49830 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49839 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49848 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49857 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49866 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49875 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49884 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49893 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49902 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49911 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49920 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49929 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49938 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49947 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49956 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49965 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49974 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49983 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49992 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50001 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50010 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50019 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50028 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50037 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50046 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50055 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50064 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50073 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50082 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50091 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50100 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50109 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50118 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50127 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50136 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50145 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50154 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50163 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50172 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50181 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50190 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50199 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50208 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50217 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50226 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50235 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50244 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50253 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50262 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50271 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50280 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50289 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50298 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50307 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50316 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50325 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50334 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50343 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50352 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50361 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50370 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50379 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50388 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50397 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50406 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50415 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50424 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50433 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50442 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50451 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50460 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50469 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50478 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50487 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50496 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50505 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50514 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50523 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50532 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50541 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50550 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50559 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50568 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50577 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50586 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50595 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50604 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50613 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50622 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50631 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50640 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50649 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50658 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50667 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50676 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50685 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50694 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50703 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50712 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50721 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50739 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50748 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50757 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50766 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50775 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50784 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50793 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50802 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50811 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50820 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50829 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50838 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50847 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50856 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50865 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50874 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50883 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50892 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50901 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50910 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50919 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50928 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50937 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50946 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50955 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50964 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50973 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50982 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50991 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51009 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51018 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51027 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51036 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51045 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51054 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51063 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51072 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51081 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51090 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51099 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51108 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51117 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51126 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51135 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51144 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51153 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51162 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51171 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51180 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51189 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51198 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51207 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51216 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51225 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51234 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51243 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51252 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51261 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51270 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51279 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51288 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51297 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51306 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51315 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51324 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51333 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51342 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51351 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51360 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51369 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51378 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51387 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51396 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51405 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51414 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51423 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51432 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51441 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51450 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51459 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51468 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51477 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51486 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51495 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51504 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51513 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51522 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51531 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51540 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51549 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51558 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51567 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51576 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51585 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51594 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51603 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51612 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51621 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51630 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51639 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51648 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51657 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51666 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51675 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51684 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51693 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51702 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51711 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51720 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51729 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51738 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51747 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51756 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51765 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51774 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51783 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51792 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51801 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51810 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51819 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51828 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51837 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51846 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51855 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51864 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51873 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51882 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51891 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51900 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51909 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51918 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51927 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51936 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51945 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51954 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51963 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51972 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51981 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51990 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51999 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52008 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52017 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52026 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52035 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52044 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52053 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52062 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52071 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52080 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52089 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52098 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52107 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52116 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52125 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52134 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52143 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52152 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52161 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52170 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52179 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52188 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52197 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52206 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52215 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52224 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52233 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52242 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52251 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52260 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52269 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52278 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52287 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52296 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52305 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52314 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52323 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52332 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52341 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52350 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52359 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52368 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52377 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52386 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52395 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52404 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52413 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52422 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52431 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52440 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52449 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52458 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52467 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52476 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52485 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52494 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:5999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52503 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52512 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52521 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52530 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52539 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52548 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52557 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52566 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52575 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52584 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52593 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52602 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52611 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52620 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52629 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52638 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52647 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52656 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52665 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52674 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52683 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52692 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52701 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52710 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52719 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52728 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52737 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52746 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52755 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52764 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52773 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52782 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52791 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52800 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52809 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52818 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52827 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52836 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52845 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52854 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52863 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52872 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52881 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52890 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52899 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52908 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52917 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52926 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52935 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52944 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52953 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52962 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52971 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52980 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52989 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52998 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53007 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53016 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53025 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53034 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53043 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53052 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53061 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53070 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53079 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53088 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53097 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53106 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53115 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53124 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53133 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53142 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53151 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53160 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53169 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53178 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53187 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53196 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53205 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53214 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53223 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53232 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53241 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53250 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53259 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53268 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53277 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53286 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53295 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53304 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53313 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53322 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53331 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53340 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53349 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53358 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53367 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53376 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53385 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53394 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53403 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53412 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53421 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53430 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53439 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53448 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53457 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53466 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53475 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53484 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53493 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53502 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53511 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53520 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53529 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53538 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53547 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53556 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53565 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53574 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53583 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53592 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53601 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53610 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53619 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53628 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53637 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53646 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53655 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53664 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53673 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53682 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53691 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53700 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53709 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53718 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53727 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53736 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53745 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53754 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53763 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53772 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53781 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53790 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53799 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53808 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53817 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53826 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53835 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53844 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53853 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53862 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53871 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53880 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53889 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53898 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53907 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53916 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53925 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53934 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53943 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53952 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53961 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53970 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53979 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53988 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53997 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54006 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54015 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54024 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54033 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54042 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54051 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54060 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54069 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54078 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54087 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54096 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54105 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54114 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54123 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54132 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54141 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54150 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54159 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54168 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54177 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54186 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54195 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54204 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54213 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54231 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54240 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54249 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54258 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54267 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54276 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54285 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54294 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54303 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54312 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54321 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54330 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54339 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54348 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54357 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54366 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54375 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54384 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54393 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54402 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54411 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54420 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54429 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54438 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54447 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54456 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54465 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54474 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54483 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54492 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54501 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54510 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54519 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54528 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54537 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54546 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54555 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54564 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54573 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54582 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54591 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54600 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54609 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54618 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54627 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54636 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54645 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54654 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54663 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54672 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54681 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54690 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54699 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54708 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54717 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54726 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54735 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54744 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54753 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54762 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54771 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54780 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54789 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54798 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54807 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54816 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54825 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54834 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54843 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54852 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54861 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54870 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54879 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54888 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54897 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54906 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54915 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54924 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54933 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54942 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54951 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54960 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54969 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54978 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54987 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54996 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55005 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55014 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55023 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55032 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55041 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55050 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55059 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55068 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55077 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55086 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55095 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55104 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55113 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55122 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55131 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55140 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55149 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55158 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55167 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55176 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55185 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55194 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55203 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55212 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55221 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55230 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55239 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55248 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55257 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55266 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55275 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55284 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55293 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55302 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55311 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55320 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55329 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55338 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55347 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55356 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55365 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55374 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55392 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55401 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55410 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55419 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55428 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55437 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55446 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55455 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55464 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55473 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55482 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55491 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55500 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55509 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55518 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55527 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55536 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55545 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55554 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55563 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55572 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55581 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55590 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55599 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55608 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55617 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55626 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55635 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55644 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55653 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55662 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55671 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55680 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55689 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55698 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55707 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55716 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55725 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55734 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55743 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55752 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55761 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55770 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55779 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55788 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55797 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55806 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55815 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55824 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55833 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55842 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55851 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55860 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55869 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55878 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55887 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55896 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55905 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55914 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55923 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55932 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55941 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55950 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55959 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55968 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55977 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55986 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55995 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56004 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56013 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56022 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56031 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56040 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56049 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56058 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56067 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56076 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56085 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56094 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56103 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56112 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56121 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56130 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56139 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56148 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56157 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56166 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56175 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56184 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56193 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56202 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56211 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56220 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56229 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56238 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56247 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56256 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56265 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56274 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56283 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56292 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56301 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56310 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56319 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56328 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56337 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56346 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56355 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56364 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56373 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56382 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56391 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56400 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56409 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56418 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56427 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56436 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56445 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56454 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56463 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56472 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56481 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56490 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56499 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56508 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56517 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56526 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56535 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56544 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56553 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56562 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56571 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56580 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56589 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56598 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56607 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56616 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56625 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56634 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56643 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56652 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56661 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56670 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56679 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56688 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56697 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56706 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56715 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56724 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56733 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56742 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56751 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56760 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56769 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56778 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56787 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56796 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56805 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56814 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56823 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56832 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56841 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56850 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56859 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56868 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56877 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56886 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56895 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56904 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56913 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56922 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56931 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56940 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56949 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56958 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56967 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56976 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56985 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56994 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57003 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57012 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57030 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57039 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57048 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57057 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57066 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57075 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57084 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57093 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57102 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57111 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57120 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57129 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57138 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57147 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57156 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57165 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57174 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57183 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57192 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57201 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57210 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57219 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57228 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57237 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57246 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57255 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57264 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57273 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57282 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57291 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57300 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57309 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57318 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57327 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57336 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57345 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57354 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57363 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57372 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57381 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57390 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57399 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57408 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57417 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57426 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57435 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57453 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57462 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57471 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57480 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57489 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57498 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57507 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57516 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57525 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57534 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57543 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57552 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57561 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57570 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57579 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57588 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57597 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57606 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57615 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57624 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57633 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57642 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57651 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57660 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57669 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57678 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57687 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57696 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57705 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57714 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57723 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57732 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57741 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57750 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57759 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57768 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57777 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57786 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57795 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57804 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57813 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57822 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57831 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57840 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57849 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57858 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57867 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57876 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57885 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57894 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57903 calling cycle -[RFile] wr_ 0: r 43 <= 00000000000000a4000000001fffff44000000 - 94390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018a0 -After delta: vaddr = 0x800018a0 -instret:6162 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9439 -instret:6163 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9439 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 400000002000062818a0ffff1ffff806441610 - 94400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800018a0 o: 'h0000000000000290 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018a0 o: 'h0000000000000290 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018a0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6164 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 9440 -instret:6165 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 9440 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h062, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94410 : [doFinishMem] DTlbResp { resp: <'h00000000800018a0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018a0 o: 'h0000000000000290 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018a0, check_high: 'h000000000800018a8, check_inclusive: True } }, specBits: 'h062 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 94410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:6166 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 9441 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h063, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000c00000001fffff44000000 - 94420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 94420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h062 } - 94430 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 94440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h063 } - 94440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94440 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 94440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 94450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h062 } - 94450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94450 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 94450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94460 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 94460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94470 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 -instret:6167 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9447 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6168 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9448 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6169 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9449 -instret:6170 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9449 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 94500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6171 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9450 -instret:6172 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9450 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 94510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 94510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6173 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9451 -instret:6174 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9451 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h064 } - 94520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6175 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9452 -instret:6176 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9452 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h064 } - 94530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94530 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 94530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6177 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9453 -instret:6178 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9453 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 94540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94540 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 73 <= 40000000200005841610ffff1ffff806441610 - 94540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 94540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6179 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9454 -instret:6180 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9454 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h064, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 94550 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001900, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 94550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 94550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002800000001fffff44000000 - 94550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94550 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 94550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6181 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9455 -instret:6182 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9455 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001890, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 94560 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002000000001fffff44000000 - 94560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 94560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080001900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 94560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6183 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9456 -instret:6184 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9456 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h065, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000000400000001fffff44000000 - 94570 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000c00000001fffff44000000 - 94570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 94570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h065 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6185 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9457 -instret:6186 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9457 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 94580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h065 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3fb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 94590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 94590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h06e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94600 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94600 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000c00000001fffff44000000 - 94600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 47 <= 0000000000000014000000001fffff44000000 - 94610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 94610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94610 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 94610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 94620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94620 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000000400000001fffff44000000 - 94620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4e <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94630 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 94630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 94640 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000002000000001fffff44000000 -instret:6187 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9464 -calling cycle -[RFile] wr_ 0: r 5f <= 0000000000000014c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 94650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6188 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9465 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 00000000000000a6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018a8 -After delta: vaddr = 0x800018a8 - 94660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6189 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9466 -instret:6190 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9466 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 400000002000062a18a8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800018a8 o: 'h0000000000000298 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018a8 o: 'h0000000000000298 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018a8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 94670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6191 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9467 -instret:6192 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9467 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94680 : [doFinishMem] DTlbResp { resp: <'h00000000800018a8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018a8 o: 'h0000000000000298 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018a8, check_high: 'h000000000800018b0, check_inclusive: True } }, specBits: 'h024 } - 94680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 94680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 94680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6193 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9468 -instret:6194 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9468 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 94690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6195 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9469 -instret:6196 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9469 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 94700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94700 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 94700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6197 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9470 -instret:6198 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9470 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 94710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94710 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 53 <= 40000000200005841610ffff1ffff806441610 - 94710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94710 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 94710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6199 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9471 -instret:6200 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9471 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 94720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 94720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94720 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000000000002800000001fffff44000000 - 94720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94720 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 94720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6201 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9472 -instret:6202 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9472 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001898, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 94730 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 94730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6203 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9473 -instret:6204 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9473 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000000400000001fffff44000000 - 94740 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000001000000001fffff44000000 - 94740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 94740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6205 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9474 -instret:6206 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9474 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 94750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3ef, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 94760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 94760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94770 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94770 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000001000000001fffff44000000 - 94770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 59 <= 0000000000000014000000001fffff44000000 - 94780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 94780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94780 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 94780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 94790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94790 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000800000001fffff44000000 - 94790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94800 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 94800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 94810 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 -instret:6207 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9481 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6208 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9482 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 0000000000000015000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6209 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9483 -instret:6210 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9483 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 00000000000000a8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018b0 -After delta: vaddr = 0x800018b0 - 94840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6211 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9484 -instret:6212 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9484 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 400000002000062c18b0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800018b0 o: 'h00000000000002a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018b0 o: 'h00000000000002a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 94850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6213 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9485 -instret:6214 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9485 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94860 : [doFinishMem] DTlbResp { resp: <'h00000000800018b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018b0 o: 'h00000000000002a0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018b0, check_high: 'h000000000800018b8, check_inclusive: True } }, specBits: 'h00c } - 94860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 94860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 94860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6215 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9486 -instret:6216 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9486 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 94870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6217 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9487 -instret:6218 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9487 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 94880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 94880 : [Ld resp] 'h0f; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6219 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9488 -instret:6220 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9488 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 94890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 94890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94890 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 71 <= 40000000200005841610ffff1ffff806441610 - 94890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 94890 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } - 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6221 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9489 -instret:6222 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9489 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018a0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 94900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94900 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6e <= 0000000000000002800000001fffff44000000 - 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 94900 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6223 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9490 -instret:6224 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9490 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6b <= 0000000000000000400000001fffff44000000 - 94910 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000002000000001fffff44000000 - 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6225 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9491 -instret:6226 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9491 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 94920 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000001400000001fffff44000000 - 94920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 94920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3bf, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 94930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 94940 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94940 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000001400000001fffff44000000 - 94940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 94940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 94950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 94950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 94950 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 94950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 54 <= 0000000000000014000000001fffff44000000 - 94960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 94960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 94960 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000c00000001fffff44000000 - 94960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 94960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 94970 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 94980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 94980 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000002000000001fffff44000000 -instret:6227 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9498 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6228 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9499 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0a <= 0000000000000015400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6229 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9500 -instret:6230 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9500 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 64 <= 00000000000000aa000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018b8 -After delta: vaddr = 0x800018b8 - 95010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6231 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9501 -instret:6232 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9501 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 400000002000062e18b8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800018b8 o: 'h00000000000002a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018b8 o: 'h00000000000002a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018b8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 95020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6233 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9502 -instret:6234 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9502 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95030 : [doFinishMem] DTlbResp { resp: <'h00000000800018b8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018b8 o: 'h00000000000002a8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018b8, check_high: 'h000000000800018c0, check_inclusive: True } }, specBits: 'h018 } - 95030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 95030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6235 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9503 -instret:6236 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9503 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 95040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6237 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9504 -instret:6238 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9504 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 95050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95050 : [Ld resp] 'h16; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6239 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9505 -instret:6240 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9505 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 95060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 95060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95060 : [doRespLdMem] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 69 <= 40000000200005841610ffff1ffff806441610 - 95060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 95060 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6241 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9506 -instret:6242 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9506 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018a8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 95070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95070 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000002800000001fffff44000000 - 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95070 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6243 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9507 -instret:6244 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9507 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000000400000001fffff44000000 - 95080 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 - 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6245 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9508 -instret:6246 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9508 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 47 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 95090 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000001800000001fffff44000000 - 95090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 95100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95110 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95110 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000001800000001fffff44000000 - 95110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 95120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 95120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 95120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7b <= 0000000000000014000000001fffff44000000 - 95130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 95130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001000000001fffff44000000 - 95130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95140 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 95140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 95150 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000002000000001fffff44000000 -instret:6247 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9515 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6248 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9516 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000000000015800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6249 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9517 -instret:6250 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9517 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 00000000000000ac000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018c0 -After delta: vaddr = 0x800018c0 - 95180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6251 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9518 -instret:6252 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9518 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 400000002000063018c0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h00000000800018c0 o: 'h00000000000002b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018c0 o: 'h00000000000002b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018c0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 95190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6253 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9519 -instret:6254 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9519 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95200 : [doFinishMem] DTlbResp { resp: <'h00000000800018c0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018c0 o: 'h00000000000002b0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018c0, check_high: 'h000000000800018c8, check_inclusive: True } }, specBits: 'h030 } - 95200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 95200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6255 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9520 -instret:6256 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9520 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 95210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6257 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9521 -instret:6258 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9521 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 95220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95220 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 95220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6259 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9522 -instret:6260 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9522 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 95230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 95230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95230 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4e <= 40000000200005841610ffff1ffff806441610 - 95230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 95230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 95230 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 95230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6261 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9523 -instret:6262 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9523 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 95240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95240 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000002800000001fffff44000000 - 95240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95240 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 95240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6263 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9524 -instret:6264 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9524 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000000400000001fffff44000000 - 95250 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 - 95250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 95250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6265 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9525 -instret:6266 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9525 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 59 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 95260 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000001c00000001fffff44000000 - 95260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fd, globalTaken: False, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 95270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 95270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95280 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95280 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000001c00000001fffff44000000 - 95280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 95290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95290 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 95290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7d <= 0000000000000014000000001fffff44000000 - 95300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 95300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95300 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000001400000001fffff44000000 - 95300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 42 <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95310 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 95310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 95320 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000002000000001fffff44000000 -instret:6267 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9532 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6268 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9533 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 0000000000000015c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6269 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9534 -instret:6270 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9534 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 00000000000000ae000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018c8 -After delta: vaddr = 0x800018c8 - 95350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6271 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9535 -instret:6272 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9535 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 400000002000063218c8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800018c8 o: 'h00000000000002b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018c8 o: 'h00000000000002b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018c8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:6273 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9536 -instret:6274 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9536 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95370 : [doFinishMem] DTlbResp { resp: <'h00000000800018c8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018c8 o: 'h00000000000002b8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018c8, check_high: 'h000000000800018d0, check_inclusive: True } }, specBits: 'h024 } - 95370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6275 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9537 -instret:6276 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9537 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 95380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:6277 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9538 -instret:6278 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9538 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 95390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 95390 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 95390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:6279 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9539 -instret:6280 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9539 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 95400 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002800000001fffff44000000 - 95400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6281 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9540 -instret:6282 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9540 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018b8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 95410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:6283 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9541 -instret:6284 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9541 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h3f7, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 0000000000000000000000001fffff44000000 - 95420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 95420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 95420 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 95420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6285 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9542 -instret:6286 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9542 -calling cycle -[RFile] wr_ 1: r 7e <= 0000000000000002c00000001fffff44000000 - 95430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 95430 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000003000000001fffff44000000 - 95430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000b o: 'h000000000000000b b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 95430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 95440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 95450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 95450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 95460 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 95460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95470 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 95470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95470 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 95470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 95480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 95480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95480 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000000000001800000001fffff44000000 - 95480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95480 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 95480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 95490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95490 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000002000000001fffff44000000 - 95490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95490 : [Ld resp] 'h11; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 95490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 95500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95500 : [doRespLdMem] 'h11; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 4d <= 40000000200005841610ffff1ffff806441610 - 95500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6287 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9550 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 95510 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000002c00000001fffff44000000 - 95510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95510 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 95510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6288 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9551 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95520 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000002000000001fffff44000000 - 95520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6289 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9552 -instret:6290 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9552 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6291 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9553 -instret:6292 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9553 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6293 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9554 -instret:6294 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9554 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 95550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 95550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6295 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9555 -instret:6296 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9555 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95560 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 -instret:6297 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9556 -instret:6298 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9556 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 05 <= 0000000000000016000000001fffff44000000 - 95570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6299 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9557 -instret:6300 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9557 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 0000000000000000400000001fffff44000000 - 95580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6301 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9558 -instret:6302 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9558 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018c0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 95590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800018c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6303 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9559 -instret:6304 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9559 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 95600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800018c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 95600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800018c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6305 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9560 -instret:6306 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9560 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000000000016000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 95610 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000000000000001fffff44000000 - 95610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 00000000000000b0000000001fffff44000000 - 95620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 95620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 95620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018d0 -After delta: vaddr = 0x800018d0 - 95620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 400000002000063418d0ffff1ffff806441610 - 95630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 95630 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h00000000800018d0 o: 'h00000000000002c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018d0 o: 'h00000000000002c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 95630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 95630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 7b <= 0000000000000000400000001fffff44000000 - 95640 : [doFinishMem] DTlbResp { resp: <'h00000000800018d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018d0 o: 'h00000000000002c0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018d0, check_high: 'h000000000800018d8, check_inclusive: True } }, specBits: 'h01e } - 95640 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95640 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 95640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 95640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 95650 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001940, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 95650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 95650 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000000000001c00000001fffff44000000 - 95650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 95650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95650 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 95650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 95660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95660 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000002000000001fffff44000000 - 95660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 95670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95670 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 95670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6307 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9567 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 95680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 95680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95680 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 47 <= 40000000200005841610ffff1ffff806441610 - 95680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6308 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9568 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95690 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002c00000001fffff44000000 - 95690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95690 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 95690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6309 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9569 -instret:6310 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9569 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95700 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000002000000001fffff44000000 - 95700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6311 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9570 -instret:6312 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9570 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6313 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9571 -instret:6314 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9571 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 95720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 95720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6315 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9572 -instret:6316 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9572 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h05a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95730 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000000000000400000001fffff44000000 -instret:6317 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9573 -instret:6318 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9573 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6319 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9574 -instret:6320 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9574 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h05b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 6d <= 0000000000000016000000001fffff44000000 - 95750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6321 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9575 -instret:6322 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9575 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018c8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 95760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6323 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9576 -instret:6324 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9576 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 95770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 95770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6325 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9577 -instret:6326 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9577 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 95780 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000000400000001fffff44000000 - 95780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 95780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4b <= 0000000000000016400000001fffff44000000 - 95790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 95790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 95790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 95790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 00000000000000b2000000001fffff44000000 - 95800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05a } - 95800 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 95800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018d8 -After delta: vaddr = 0x800018d8 - 95800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 7d <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 7f <= 400000002000063618d8ffff1ffff806441610 - 95810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 95810 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h00000000800018d8 o: 'h00000000000002c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018d8 o: 'h00000000000002c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018d8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 95810 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 95810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 95820 : [doFinishMem] DTlbResp { resp: <'h00000000800018d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018d8 o: 'h00000000000002c8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018d8, check_high: 'h000000000800018e0, check_inclusive: True } }, specBits: 'h05a } - 95820 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95820 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000002000000001fffff44000000 - 95820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 95820 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 95820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 95820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 95830 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000002000000001fffff44000000 - 95830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 95830 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 95830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 95840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95840 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 59 <= 40000000200005841610ffff1ffff806441610 - 95840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6327 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9584 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 95850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95850 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000002c00000001fffff44000000 - 95850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6328 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9585 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 95860 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 95860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6329 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9586 -instret:6330 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 9586 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 95870 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 95870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6331 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9587 -instret:6332 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 9587 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 95880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6333 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 9588 -instret:6334 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 9588 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 95890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 95890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 95890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:6335 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 9589 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 95900 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000000000000800000001fffff44000000 - 95900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 95900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 95900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95910 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 95910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 5d <= 0000000000000016000000001fffff44000000 - 95920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 95920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 95920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 95920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 95920 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 95920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 95920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 40 <= 1000000000000000040000001fffff44000000 - 95930 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002c00000001fffff44000000 - 95930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 95940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 95950 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000800000001fffff44000000 -instret:6336 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 9595 calling cycle -[RFile] wr_ 0: r 44 <= 0000000000000016800000001fffff44000000 - 95960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6337 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 9596 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 49 <= 00000000000000b4000000001fffff44000000 - 95970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018e0 -After delta: vaddr = 0x800018e0 -instret:6338 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9597 -instret:6339 PC:0x1ffff0000000000000000000080000050 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9597 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 400000002000063818e0ffff1ffff806441610 - 95980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h00000000800018e0 o: 'h00000000000002d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018e0 o: 'h00000000000002d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018e0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 95980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h062, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6340 PC:0x1ffff0000000000000000000080000054 instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 9598 -instret:6341 PC:0x1ffff0000000000000000000080000056 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 9598 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h062, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 95990 : [doFinishMem] DTlbResp { resp: <'h00000000800018e0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018e0 o: 'h00000000000002d0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018e0, check_high: 'h000000000800018e8, check_inclusive: True } }, specBits: 'h062 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } - 95990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h062 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 95990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 95990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -instret:6342 PC:0x1ffff000000000000000000008000005a instr:0x0040006f iType:J [doCommitNormalInst [0]] 9599 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hf7f, localHist: 'h1fe, globalTaken: True, localTaken: False, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h063, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 0000000000000000c00000001fffff44000000 - 96000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h062 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } - 96000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h063, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h062 } - 96010 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h063 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 96020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h063 } - 96020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h063 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96020 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 96020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 96030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h062 } - 96030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96030 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000 - 96030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96040 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 96040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96050 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000002000000001fffff44000000 -instret:6343 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9605 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6344 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9606 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6345 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9607 -instret:6346 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9607 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 96080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6347 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9608 -instret:6348 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9608 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 96090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6349 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9609 -instret:6350 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9609 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h064 } - 96100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6351 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9610 -instret:6352 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9610 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h064 } - 96110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96110 : [Ld resp] 'h0e; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 96110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6353 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9611 -instret:6354 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9611 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 96120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96120 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 54 <= 40000000200005841610ffff1ffff806441610 - 96120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96120 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 96120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6355 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9612 -instret:6356 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9612 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h064, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 96130 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001940, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } - 96130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 96130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96130 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 0000000000000002c00000001fffff44000000 - 96130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96130 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 96130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6357 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9613 -instret:6358 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9613 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96140 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002000000001fffff44000000 - 96140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96140 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 96140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080001940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 96140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6359 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9614 -instret:6360 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9614 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h065, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h065, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000 - 96150 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000000000000c00000001fffff44000000 - 96150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 96150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800018d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h065 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6361 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9615 -instret:6362 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9615 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 96160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h065 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfbf, localHist: 'h3fb, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h067, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h067, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 96170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 96170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h066, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h06e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96180 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000000c00000001fffff44000000 - 96180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h066 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h066 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 43 <= 0000000000000016000000001fffff44000000 - 96190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 96190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96190 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 96190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h064 } - 96200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000400000001fffff44000000 - 96200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h064 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 7a <= 0000000000000001000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000004 o: 'h0000000000000004 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h064 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96210 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 96210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h064 } - 96220 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000000000002000000001fffff44000000 -instret:6363 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9622 -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000016c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 96230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h064, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6364 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9623 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h06c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 00000000000000b6000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018e8 -After delta: vaddr = 0x800018e8 - 96240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6365 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9624 -instret:6366 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9624 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 400000002000063a18e8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800018e8 o: 'h00000000000002d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018e8 o: 'h00000000000002d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018e8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 96250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6367 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9625 -instret:6368 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9625 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96260 : [doFinishMem] DTlbResp { resp: <'h00000000800018e8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018e8 o: 'h00000000000002d8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018e8, check_high: 'h000000000800018f0, check_inclusive: True } }, specBits: 'h024 } - 96260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 96260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6369 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9626 -instret:6370 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9626 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h02c } - 96270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6371 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9627 -instret:6372 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9627 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 96280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96280 : [Ld resp] 'h15; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 96280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6373 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9628 -instret:6374 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9628 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 96290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96290 : [doRespLdMem] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7b <= 40000000200005841610ffff1ffff806441610 - 96290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96290 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } - 96290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6375 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9629 -instret:6376 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9629 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h02c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 96300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 96300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96300 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000002c00000001fffff44000000 - 96300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96300 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 96300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6377 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9630 -instret:6378 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9630 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96310 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 96310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6379 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9631 -instret:6380 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9631 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000000400000001fffff44000000 - 96320 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000001000000001fffff44000000 - 96320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 96320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800018d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6381 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9632 -instret:6382 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9632 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 96330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfdf, localHist: 'h3ef, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 96340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 96340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96350 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96350 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000001000000001fffff44000000 - 96350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 2: r 57 <= 0000000000000016000000001fffff44000000 - 96360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 96360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96360 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 96360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h02c } - 96370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96370 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000800000001fffff44000000 - 96370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 52 <= 0000000000000001400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000005 o: 'h0000000000000005 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96380 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 96380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h02c } - 96390 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000002000000001fffff44000000 -instret:6383 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9639 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6384 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9640 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 61 <= 0000000000000017000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6385 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9641 -instret:6386 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9641 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 02 <= 00000000000000b8000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h00c } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018f0 -After delta: vaddr = 0x800018f0 - 96420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6387 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9642 -instret:6388 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9642 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 400000002000063c18f0ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h00000000800018f0 o: 'h00000000000002e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018f0 o: 'h00000000000002e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018f0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 96430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6389 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9643 -instret:6390 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9643 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96440 : [doFinishMem] DTlbResp { resp: <'h00000000800018f0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018f0 o: 'h00000000000002e0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018f0, check_high: 'h000000000800018f8, check_inclusive: True } }, specBits: 'h00c } - 96440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 96440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6391 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9644 -instret:6392 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9644 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h01c } - 96450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6393 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9645 -instret:6394 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9645 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h01c } - 96460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96460 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 96460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6395 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9646 -instret:6396 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9646 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h01c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 96470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 96470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96470 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7d <= 40000000200005841610ffff1ffff806441610 - 96470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96470 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 96470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6397 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9647 -instret:6398 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9647 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018e0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96480 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000002c00000001fffff44000000 - 96480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96480 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } - 96480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6399 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9648 -instret:6400 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9648 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000000000000400000001fffff44000000 - 96490 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 72 <= 0000000000000002000000001fffff44000000 - 96490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 96490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800018e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6401 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9649 -instret:6402 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9649 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 96500 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000001400000001fffff44000000 - 96500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hfef, localHist: 'h3bf, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 96510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96520 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96520 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000001400000001fffff44000000 - 96520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +instret:6600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57912 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57921 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57930 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57939 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57948 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle calling cycle - 96530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 96530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96530 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 96530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 4c <= 0000000000000016000000001fffff44000000 - 96540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01c } - 96540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96540 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000c00000001fffff44000000 - 96540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 68 <= 0000000000000001800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000006 o: 'h0000000000000006 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96550 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 96550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01c } - 96560 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000002000000001fffff44000000 -instret:6403 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9656 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6404 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9657 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000000000017400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6405 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9658 -instret:6406 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9658 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 00000000000000ba000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800018f8 -After delta: vaddr = 0x800018f8 - 96590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6407 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9659 -instret:6408 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9659 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 400000002000063e18f8ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h00000000800018f8 o: 'h00000000000002e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800018f8 o: 'h00000000000002e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800018f8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 96600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6409 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9660 -instret:6410 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9660 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96610 : [doFinishMem] DTlbResp { resp: <'h00000000800018f8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800018f8 o: 'h00000000000002e8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h00000000800018f8, check_high: 'h00000000080001900, check_inclusive: True } }, specBits: 'h018 } - 96610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 96610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6411 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9661 -instret:6412 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9661 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h038 } - 96620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6413 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9662 -instret:6414 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9662 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h038 } - 96630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96630 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } - 96630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6415 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9663 -instret:6416 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9663 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h038, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 96640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 96640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96640 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7e <= 40000000200005841610ffff1ffff806441610 - 96640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96640 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 96640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6417 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9664 -instret:6418 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9664 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018e8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96650 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000002c00000001fffff44000000 - 96650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96650 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 96650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6419 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9665 -instret:6420 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9665 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h039, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h039, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000000000000400000001fffff44000000 - 96660 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000002000000001fffff44000000 - 96660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 96660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800018e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h039 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6421 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9666 -instret:6422 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9666 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 43 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 96670 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000001800000001fffff44000000 - 96670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h039 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hff7, localHist: 'h2ff, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h03b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 96680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 96680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h03a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96690 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96690 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000001800000001fffff44000000 - 96690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } calling cycle - 96700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 96700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96700 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 96700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h038, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 64 <= 0000000000000016000000001fffff44000000 - 96710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h038 } - 96710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96710 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001000000001fffff44000000 - 96710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h038 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 6c <= 0000000000000001c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000007 o: 'h0000000000000007 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h038 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96720 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 96720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h038 } - 96730 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000002000000001fffff44000000 -instret:6423 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9673 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6424 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9674 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h03c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 0000000000000017800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h030, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6425 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9675 -instret:6426 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9675 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 00000000000000bc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h030 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001900 -After delta: vaddr = 0x80001900 - 96760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6427 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9676 -instret:6428 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9676 - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 40000000200006401900ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001900 o: 'h00000000000002f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001900 o: 'h00000000000002f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h030 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001900, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 96770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6429 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9677 -instret:6430 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9677 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96780 : [doFinishMem] DTlbResp { resp: <'h0000000080001900,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001900 o: 'h00000000000002f0 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001900, check_high: 'h00000000080001908, check_inclusive: True } }, specBits: 'h030 } - 96780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 96780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6431 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9678 -instret:6432 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9678 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h034 } - 96790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -instret:6433 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9679 -instret:6434 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9679 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h034 } - 96800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 96800 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 96800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } -instret:6435 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9680 -instret:6436 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9680 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h034, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 96810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 96810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96810 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 7a <= 40000000200005841610ffff1ffff806441610 - 96810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 } - 96810 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 96810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6437 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9681 -instret:6438 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9681 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018f0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96820 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000002c00000001fffff44000000 - 96820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 96820 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 96820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6439 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9682 -instret:6440 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9682 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h035, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h035, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 0000000000000000400000001fffff44000000 - 96830 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000002000000001fffff44000000 - 96830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 96830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800018f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h035 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6441 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9683 -instret:6442 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9683 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 96840 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000001c00000001fffff44000000 - 96840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h035 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hffb, localHist: 'h3fd, globalTaken: False, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h037, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h037, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 96850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 96850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 96850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 96850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h036, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96860 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96860 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000001c00000001fffff44000000 - 96860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h036 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h036 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 96860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 96870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 96870 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } - 96870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h034, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 0c <= 0000000000000016000000001fffff44000000 - 96880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h034 } - 96880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96880 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000001400000001fffff44000000 - 96880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h034 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000002000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000008 o: 'h0000000000000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h034 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 96890 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 96890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h034 } - 96900 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000002000000001fffff44000000 -instret:6443 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9690 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -instret:6444 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9691 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h03c, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000000000017c00000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h024, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6445 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9692 -instret:6446 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9692 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 00000000000000be000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h024 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001908 -After delta: vaddr = 0x80001908 - 96930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6447 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9693 -instret:6448 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9693 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 40000000200006421908ffff1ffff806441610 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001908 o: 'h00000000000002f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001908 o: 'h00000000000002f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h024 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001908, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 -instret:6449 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9694 -instret:6450 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9694 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff8a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h02d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96950 : [doFinishMem] DTlbResp { resp: <'h0000000080001908,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001908 o: 'h00000000000002f8 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001908, check_high: 'h00000000080001910, check_inclusive: True } }, specBits: 'h024 } - 96950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6451 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9695 -instret:6452 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9695 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h7fd, localHist: 'h3ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h02f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 96960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } - 96960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h80ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 96960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h02e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } -instret:6453 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9696 -instret:6454 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9696 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 96970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 96970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 96970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } - 96970 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } - 96970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 96970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f4c -After delta: vaddr = 0x80000f4c -instret:6455 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9697 -instret:6456 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9697 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02e } - 96980 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000000000002c00000001fffff44000000 - 96980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f4c, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 96980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6457 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9698 -instret:6458 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9698 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 96990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f4c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f4c o: 'h0000000080000f4c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f4c, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800018f8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 96990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f4c, shiftedBE: tagged DataMemAccess , pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 96990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 96990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h02c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 96990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } -instret:6459 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9699 -instret:6460 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9699 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hbfe, localHist: 'h3f7, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h07d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000000000000001fffff44000000 - 97000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03d } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 97000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f4c, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } - 97000 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 97000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h02c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 97000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h07d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800018f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6461 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9700 -instret:6462 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9700 -calling cycle -[RFile] wr_ 1: r 65 <= 0000000000000003000000001fffff44000000 - 97010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 97010 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000003000000001fffff44000000 - 97010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000c o: 'h000000000000000c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h02c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800018f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 97010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800018f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 97010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h07c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h02c } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 97020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03c } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h03e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h03c } - 97030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 97030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03c } - 97040 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 97040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97050 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 97050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97050 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 97050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 97050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 97060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h03f } - 97060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97060 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000001800000001fffff44000000 - 97060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97060 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 97060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h03e } - 97070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97070 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000002000000001fffff44000000 - 97070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97070 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } - 97070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h03e } - 97080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97080 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5d <= 40000000200005841610ffff1ffff806441610 - 97080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6463 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9708 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 97090 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000003000000001fffff44000000 - 97090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97090 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 97090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6464 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9709 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97100 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000002000000001fffff44000000 - 97100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6465 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9710 -instret:6466 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9710 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6467 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9711 -instret:6468 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9711 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6469 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9712 -instret:6470 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9712 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 97130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 97130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6471 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9713 -instret:6472 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9713 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97140 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 -instret:6473 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9714 -instret:6474 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9714 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 2: r 7c <= 0000000000000018000000001fffff44000000 - 97150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6475 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9715 -instret:6476 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9715 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h01f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000000000000400000001fffff44000000 - 97160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6477 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9716 -instret:6478 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9716 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001900, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 97170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01f } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6479 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9717 -instret:6480 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9717 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hdff, localHist: 'h3df, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h03f, spec_tag: tagged Valid 'h6, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 97180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 97180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 97180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h03e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6481 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9718 -instret:6482 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9718 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000000000018000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 97190 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 - 97190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h03e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h03e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 00000000000000c0000000001fffff44000000 - 97200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 97200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 97200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001910 -After delta: vaddr = 0x80001910 - 97200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h01e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97200 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 40000000200006441910ffff1ffff806441610 - 97210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h01e } - 97210 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001910 o: 'h0000000000000300 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001910 o: 'h0000000000000300 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001910, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 97210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 97210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 97210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000000400000001fffff44000000 - 97220 : [doFinishMem] DTlbResp { resp: <'h0000000080001910,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001910 o: 'h0000000000000300 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001910, check_high: 'h00000000080001918, check_inclusive: True } }, specBits: 'h01e } - 97220 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h01e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97220 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } } - 97220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05f } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 97220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 97230 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001980, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 97230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h01e } - 97230 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 05 <= 0000000000000001c00000001fffff44000000 - 97230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 97230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97230 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 97230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 97230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h05e } - 97240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97240 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000002000000001fffff44000000 - 97240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h05e } - 97250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97250 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 97250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6483 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9725 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 97260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05e } - 97260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97260 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 43 <= 40000000200005841610ffff1ffff806441610 - 97260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6484 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9726 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97270 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000000000003000000001fffff44000000 - 97270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97270 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 97270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6485 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9727 -instret:6486 PC:0x1ffff000000000000000000008000006e instr:0x0040006f iType:J [doCommitNormalInst [1]] 9727 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97280 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000000000002000000001fffff44000000 - 97280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6487 PC:0x1ffff0000000000000000000080000072 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9728 -instret:6488 PC:0x1ffff0000000000000000000080000076 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 9728 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6489 PC:0x1ffff000000000000000000008000007a instr:0xfd846603 iType:Ld [doCommitNormalInst [0]] 9729 -instret:6490 PC:0x1ffff000000000000000000008000007e instr:0x02c585b3 iType:Alu [doCommitNormalInst [1]] 9729 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 97300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 97300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6491 PC:0x1ffff0000000000000000000080000082 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 9730 -instret:6492 PC:0x1ffff0000000000000000000080000086 instr:0x000095b2 iType:Alu [doCommitNormalInst [1]] 9730 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h05a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97310 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000400000001fffff44000000 -instret:6493 PC:0x1ffff0000000000000000000080000088 instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 9731 -instret:6494 PC:0x1ffff000000000000000000008000008a instr:0x22b505db iType:Cap [doCommitNormalInst [1]] 9731 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6495 PC:0x1ffff000000000000000000008000008e instr:0x00004505 iType:Alu [doCommitNormalInst [0]] 9732 -instret:6496 PC:0x1ffff0000000000000000000080000090 instr:0x0000157a iType:Alu [doCommitNormalInst [1]] 9732 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffba }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h05b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h05b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 50 <= 0000000000000018000000001fffff44000000 - 97330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6497 PC:0x1ffff0000000000000000000080000092 instr:0xf8a585db iType:St [doCommitNormalInst [0]] 9733 -instret:6498 PC:0x1ffff0000000000000000000080000096 instr:0x0040006f iType:J [doCommitNormalInst [1]] 9733 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 1000000000000000040000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001908, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8092 } - 97340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -instret:6499 PC:0x1ffff000000000000000000008000009a instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9734 -instret:6500 PC:0x1ffff000000000000000000008000009e instr:0x00000505 iType:Alu [doCommitNormalInst [1]] 9734 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'heff, localHist: 'h37f, globalTaken: True, localTaken: True, pcIndex: 'h033 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h05f, spec_tag: tagged Valid 'h5, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 97350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } - 97350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8092 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 97350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h05e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6501 PC:0x1ffff00000000000000000000800000a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 9735 -instret:6502 PC:0x1ffff00000000000000000000800000a4 instr:0xfbbff06f iType:J [doCommitNormalInst [1]] 9735 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h07e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } - 97360 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000400000001fffff44000000 - 97360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05e } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000018400000001fffff44000000 - 97370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 97370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } - 97370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 97370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: FpuMulDivRSData { execFunc: tagged MulDiv MulDivInst { func: Mul, w: False, sign: Signed } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 00000000000000c2000000001fffff44000000 - 97380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h05a } - 97380 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h805e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07b } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 97380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001918 -After delta: vaddr = 0x80001918 - 97380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h05a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000000000000800000001fffff44000000 -[RFile] wr_ 1: r 41 <= 40000000200006461918ffff1ffff806441610 - 97390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h07b } - 97390 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001918 o: 'h0000000000000308 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h4000000000000000 o: 'h4000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001918 o: 'h0000000000000308 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001918, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } - 97390 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 97390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h05a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 97390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } -calling cycle - 97400 : [doFinishMem] DTlbResp { resp: <'h0000000080001918,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001918 o: 'h0000000000000308 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001610, authority_top: 'h00000000080001910, authority_idx: 'h0b, check_low: 'h0000000080001918, check_high: 'h00000000080001920, check_inclusive: True } }, specBits: 'h05a } - 97400 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8072 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97400 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000002000000001fffff44000000 - 97400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000002 o: 'h0000000000000002 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h05a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 } - 97400 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 97400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07b } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f40 -After delta: vaddr = 0x80000f40 - 97400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h07b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h05a } - 97410 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000000000002000000001fffff44000000 - 97410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8072 } - 97410 : [Ld resp] 'h14; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h07a } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h07a } - 97420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8076 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97420 : [doRespLdMem] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 57 <= 40000000200005841610ffff1ffff806441610 - 97420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h07a } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6503 PC:0x1ffff000000000000000000008000005e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 9742 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f4c, check_inclusive: True } }, specBits: 'h07a } - 97430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97430 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 0000000000000003000000001fffff44000000 - 97430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } -instret:6504 PC:0x1ffff0000000000000000000080000062 instr:0xfd846583 iType:Ld [doCommitNormalInst [0]] 9743 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h07a, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } - 97440 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 97440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6505 PC:0x1ffff0000000000000000000080000066 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9744 -instret:6506 PC:0x1ffff000000000000000000008000006a instr:0x03e0006f iType:J [doCommitNormalInst [1]] 9744 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 97450 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000002000000001fffff44000000 - 97450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h072 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -instret:6507 PC:0x1ffff00000000000000000000800000a8 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9745 -instret:6508 PC:0x1ffff00000000000000000000800000ac instr:0xfd043503 iType:Ld [doCommitNormalInst [1]] 9745 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 97460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h072 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6509 PC:0x1ffff00000000000000000000800000b0 instr:0x00000505 iType:Alu [doCommitNormalInst [0]] 9746 -instret:6510 PC:0x1ffff00000000000000000000800000b2 instr:0xfca43823 iType:St [doCommitNormalInst [1]] 9746 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 97470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b2 } - 97470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 97470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -instret:6511 PC:0x1ffff00000000000000000000800000b6 instr:0xf8bff06f iType:J [doCommitNormalInst [0]] 9747 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h072, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 97480 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000000800000001fffff44000000 - 97480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } - 97480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97490 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8040 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h073, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } -calling cycle -[RFile] wr_ 0: r 52 <= 0000000000000000400000001fffff44000000 -[RFile] wr_ 2: r 77 <= 0000000000000018000000001fffff44000000 - 97500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 97500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8040 } - 97500 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 97500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h073 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 -calling cycle -[RFile] wr_ 1: r 6d <= 1000000000000000040000001fffff44000000 - 97510 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000003000000001fffff44000000 - 97510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h073 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h072 } - 97520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f4c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97530 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000000000000800000001fffff44000000 -instret:6512 PC:0x1ffff0000000000000000000080000040 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 9753 +instret:6605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57957 calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000018800000001fffff44000000 -[ALU redirect - 1] 'h1ffff000000000000000000008000004c; 'h4; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } - 97540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h072, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6513 PC:0x1ffff0000000000000000000080000044 instr:0xfdc46583 iType:Ld [doCommitNormalInst [0]] 9754 calling cycle -[ROB incorrectSpec] 'h4 ; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:6514 PC:0x1ffff0000000000000000000080000048 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 9756 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000006e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 97620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57966 calling cycle - 97630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 97630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 97640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 calling cycle - 97650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } - 97650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h80ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } -calling cycle -[RFile] wr_ 1: r 45 <= 00000000200003dc000000001fffff44000000 - 97660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 97660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h80bc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 97660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ba } - 97660 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 97660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } -instret:6515 PC:0x1ffff000000000000000000008000004c instr:0x06e0006f iType:J [doCommitNormalInst [0]] 9766 -calling cycle - 97670 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000020000163800000001fffff44000000 - 97670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 97670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } - 97670 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 97670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff90, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97680 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000020000400000000001fffff44000000 - 97680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff90, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ca }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 97690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff90, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:6516 PC:0x1ffff00000000000000000000800000ba instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 9769 calling cycle -[ALU redirect - 0] 'h1ffff000000000000000000008000058e; 'h1; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } - 97700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff90, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc -instret:6517 PC:0x1ffff00000000000000000000800000bc instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 9770 -instret:6518 PC:0x1ffff00000000000000000000800000be instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 9770 calling cycle - 97710 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001980, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 97720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97720 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 97720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080001980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 97720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6519 PC:0x1ffff00000000000000000000800000c0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 9772 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57975 calling cycle - 97760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000e2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 97770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb0, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb0 -After delta: vaddr = 0x80000fb0 calling cycle - 97780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc calling cycle -[RFile] wr_ 1: r 44 <= 0000000020000164800000001fffff44000000 - 97790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 97790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h858e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ca }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 49 <= 0000000020000166800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000674; 'h0; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } - 97800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } - 97800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h858e } - 97800 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 97800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 97820 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 5c <= 40000000200004021008ffff1ffff805821008 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } calling cycle -instret:6520 PC:0x1ffff000000000000000000008000058e instr:0xfb04250f iType:Ld [doCommitNormalInst [0]] 9784 -instret:6521 PC:0x1ffff0000000000000000000080000592 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 9784 +instret:6608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57984 calling cycle -instret:6522 PC:0x1ffff0000000000000000000080000596 instr:0x0e2080e7 iType:Jr [doCommitNormalInst [0]] 9785 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 97870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 97880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 97880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5d <= 00000000200003d0000000001fffff44000000 - 97890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000059a o: 'h000000008000059a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 97890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 00000000200003dc000000001fffff44000000 - 97900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 97900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 97900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6523 PC:0x1ffff0000000000000000000080000674 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 9790 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 97910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001608 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 97910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 97910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6524 PC:0x1ffff0000000000000000000080000676 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 9791 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 97920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8676 } - 97920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 97920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 97920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -instret:6525 PC:0x1ffff0000000000000000000080000678 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 9792 -instret:6526 PC:0x1ffff000000000000000000008000067a instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 9792 -calling cycle - 97930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 97930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8680 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 97930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } - 97930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6527 PC:0x1ffff000000000000000000008000067c instr:0xfea44023 iType:St [doCommitNormalInst [0]] 9793 -calling cycle -[RFile] wr_ 1: r 6a <= 00000000200001a3800000001fffff44000000 - 97940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8678 } - 97940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 97940 : [doRespLdForward] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 53 <= 40000000200004021008ffff1ffff805821008 - 97940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h3fe, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h155 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } -[RFile] wr_ 1: r 4e <= 00000000200001a5800000001fffff44000000 -[ALU redirect - 1] 'h1ffff00000000000000000000800008a2; 'h0; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } - 97950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 97950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 97950 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 97950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 97950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h16, t: 'h2c } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 97970 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000300000002000000001fffff44000000 - 97970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - 97970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 97970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 97970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 -instret:6528 PC:0x1ffff0000000000000000000080000680 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 9797 -calling cycle -[RFile] wr_ 0: r 5b <= 0000000020000402000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h867c } - 97980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 97980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } -calling cycle - 97990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 97990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 97990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - 97990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 97990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 97990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6529 PC:0x1ffff0000000000000000000080000684 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 9799 -calling cycle -instret:6530 PC:0x1ffff0000000000000000000080000686 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 9800 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8686 } - 98010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 98020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - 98020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 98040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 00000000200003c4000000001fffff44000000 - 98050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 98050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 00000000200003d0000000001fffff44000000 - 98060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 98060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 98060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h1ff, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 98070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000c00000008 o: 'h0000000c00000008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 98070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle calling cycle calling cycle calling cycle +instret:6609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57993 calling cycle calling cycle calling cycle @@ -97728,6 +71628,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58002 calling cycle calling cycle calling cycle @@ -97737,6 +71638,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58011 calling cycle calling cycle calling cycle @@ -97746,6 +71648,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58020 calling cycle calling cycle calling cycle @@ -97755,6 +71658,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58029 calling cycle calling cycle calling cycle @@ -97764,256 +71668,27 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58038 calling cycle - 98580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 98590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 98600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6a <= 00000000200001a3800000001fffff44000000 - 98610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 98610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 98610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 98610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4e <= 00000000200001a5800000001fffff44000000 - 98620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 98620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 98620 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 98620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 98620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 98620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5a <= 00000000200003c4000000001fffff44000000 - 98630 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000020000402000000001fffff44000000 - 98630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 98630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 60 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 98640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 98640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 98640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h0ff, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 98650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 98650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6531 PC:0x1ffff000000000000000000008000068a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 9865 -instret:6532 PC:0x1ffff000000000000000000008000068e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 9865 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 98660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6533 PC:0x1ffff0000000000000000000080000692 instr:0x214080e7 iType:Jr [doCommitNormalInst [0]] 9866 -instret:6534 PC:0x1ffff00000000000000000000800008a2 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 9866 -calling cycle - 98670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 98670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 98670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6535 PC:0x1ffff00000000000000000000800008a4 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 9867 -instret:6536 PC:0x1ffff00000000000000000000800008a6 instr:0x0000f022 iType:St [doCommitNormalInst [1]] 9867 -calling cycle - 98680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a4 } - 98680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 98680 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000020000402000000001fffff44000000 - 98680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -instret:6537 PC:0x1ffff00000000000000000000800008a8 instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 9868 -instret:6538 PC:0x1ffff00000000000000000000800008aa instr:0xfea43423 iType:St [doCommitNormalInst [1]] 9868 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 98690 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000020000402000000001fffff44000000 - 98690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } - 98690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 98690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a6 } - 98700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 98700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -instret:6539 PC:0x1ffff00000000000000000000800008ae instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 9870 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000020000400000000001fffff44000000 - 98710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } - 98710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 98720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88aa } - 98720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 98720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -instret:6540 PC:0x1ffff00000000000000000000800008b2 instr:0x00001561 iType:Alu [doCommitNormalInst [0]] 9872 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h07f, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h070 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000020040232800000001fffff44000000 - 98730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } - 98730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 98730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 98730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6541 PC:0x1ffff00000000000000000000800008b4 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 9873 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000fa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000020040402000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88b4 } - 98740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 98740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } calling cycle - 98750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 98750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } - 98750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6542 PC:0x1ffff00000000000000000000800008b8 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 9875 -instret:6543 PC:0x1ffff00000000000000000000800008bc instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 9875 -calling cycle - 98760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 98760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h88da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:6544 PC:0x1ffff00000000000000000000800008be instr:0x00c0006f iType:J [doCommitNormalInst [0]] 9876 -instret:6545 PC:0x1ffff00000000000000000000800008ca instr:0x00100517 iType:Auipc [doCommitNormalInst [1]] 9876 -calling cycle - 98770 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000020040402000000001fffff44000000 - 98770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6546 PC:0x1ffff00000000000000000000800008ce instr:0x73e50513 iType:Alu [doCommitNormalInst [0]] 9877 -instret:6547 PC:0x1ffff00000000000000000000800008d2 instr:0xfea43023 iType:St [doCommitNormalInst [1]] 9877 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88d2 } - 98780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 98780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } -instret:6548 PC:0x1ffff00000000000000000000800008d6 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9878 calling cycle - 98790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 98790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } - 98790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 98790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6549 PC:0x1ffff00000000000000000000800008da instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 9879 calling cycle - 98800 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 98800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h88de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 98800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } calling cycle - 98810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 98810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 98810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 98810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 98810 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 98810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 98820 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000000000000000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:6615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58047 calling cycle -instret:6550 PC:0x1ffff00000000000000000000800008de instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 9884 calling cycle calling cycle -instret:6551 PC:0x1ffff00000000000000000000800008e0 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 9886 -instret:6552 PC:0x1ffff00000000000000000000800008e2 instr:0x0fa0006f iType:J [doCommitNormalInst [1]] 9886 calling cycle calling cycle calling cycle calling cycle calling cycle calling cycle +instret:6616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58056 calling cycle calling cycle calling cycle @@ -98023,6 +71698,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58065 calling cycle calling cycle calling cycle @@ -98032,6 +71708,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58074 calling cycle calling cycle calling cycle @@ -98041,6 +71718,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58083 calling cycle calling cycle calling cycle @@ -98049,233 +71727,28 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 99280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +instret:6620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58092 calling cycle - 99290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 99300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - 99310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 99310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 99310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89dc } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 99320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89dc } - 99320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89dc } - 99320 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 99320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 99330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 99330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99330 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000020040402000000001fffff44000000 - 99330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 99330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 99330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e2 } - 99340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e2 } - 99340 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 99340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 99340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 99350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 99350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99350 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000020000400000000001fffff44000000 - 99350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 99350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 99350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } -instret:6553 PC:0x1ffff00000000000000000000800009dc instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 9935 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 99360 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 99360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h89e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } - 99360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } - 99360 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } } - 99360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 99360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 99360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 99370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 99370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99370 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 79 <= 0000000020000400000000001fffff44000000 - 99370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 99370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 99370 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 99370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 99370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89ec } -calling cycle - 99380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 99380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h89f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99380 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000000000000001fffff44000000 - 99380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89ec } - 99380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89ec } - 99380 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } } - 99380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 99380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } -calling cycle -[RFile] wr_ 0: r 57 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 99390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h89f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99390 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 71 <= 0000000020040402000000001fffff44000000 - 99390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 99390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 99390 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 99390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001008 -After delta: vaddr = 0x80001008 - 99390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 99390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99400 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 00000000200001a5800000001fffff44000000 - 99400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 99400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 99400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 99400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 -instret:6554 PC:0x1ffff00000000000000000000800009e0 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 9940 -calling cycle - 99410 : [doFinishMem] DTlbResp { resp: <'h0000000080001008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001008, check_high: 'h00000000080001010, check_inclusive: True } }, specBits: 'h000 } - 99410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 00000000200003dc000000001fffff44000000 - 99410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6555 PC:0x1ffff00000000000000000000800009e2 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 9941 calling cycle - 99420 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } -instret:6556 PC:0x1ffff00000000000000000000800009e6 instr:0x0000e588 iType:St [doCommitNormalInst [0]] 9942 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h89e6 } - 99430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e6 } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e6 } - 99440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 99440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6557 PC:0x1ffff00000000000000000000800009e8 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 9944 calling cycle -instret:6558 PC:0x1ffff00000000000000000000800009ec instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 9945 -instret:6559 PC:0x1ffff00000000000000000000800009f0 instr:0x0000e188 iType:St [doCommitNormalInst [1]] 9945 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080101008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h89f0 } - 99460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f0 } -instret:6560 PC:0x1ffff00000000000000000000800009f2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 9946 +instret:6621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58101 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f0 } - 99470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080101008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 99470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6561 PC:0x1ffff00000000000000000000800009f6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 9947 calling cycle -instret:6562 PC:0x1ffff00000000000000000000800009f8 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 9948 -instret:6563 PC:0x1ffff00000000000000000000800009fa instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 9948 calling cycle -instret:6564 PC:0x1ffff00000000000000000000800009fc instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 9949 calling cycle calling cycle calling cycle calling cycle calling cycle calling cycle +instret:6622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58110 calling cycle calling cycle calling cycle @@ -98285,6 +71758,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58119 calling cycle calling cycle calling cycle @@ -98294,6 +71768,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58128 calling cycle calling cycle calling cycle @@ -98303,1076 +71778,107 @@ calling cycle calling cycle calling cycle calling cycle +instret:6625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58137 calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 99860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 99870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 99870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 99880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 calling cycle - 99890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 99890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -calling cycle -[RFile] wr_ 1: r 4a <= 00000000200003dc000000001fffff44000000 - 99900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 99900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8698 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 99900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 99900 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 99900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 99910 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000020000166800000001fffff44000000 - 99910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 99910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 99910 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } - 99910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 99910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99920 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 77 <= 0000000020000400000000001fffff44000000 - 99920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 99920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 99930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:6565 PC:0x1ffff0000000000000000000080000696 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 9993 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000059a; 'h0; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } - 99940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } - 99940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 99940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 99940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -instret:6566 PC:0x1ffff0000000000000000000080000698 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 9994 -instret:6567 PC:0x1ffff000000000000000000008000069a instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 9994 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 99960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 99960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 99960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 99960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 99960 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 99960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6568 PC:0x1ffff000000000000000000008000069c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 9996 +instret:6626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58146 calling cycle - 99970 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000d6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 calling cycle - 100020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc calling cycle -[RFile] wr_ 1: r 46 <= 0000000020000167800000001fffff44000000 - 100030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 100030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h859a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 52 <= 0000000020000169800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000674; 'h0; InstTag { way: 'h0, ptr: 'h14, t: 'h28 } - 100040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859a } - 100040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859a } - 100040 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 100040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h14, t: 'h28 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +instret:6627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58155 calling cycle - 100060 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 67 <= 40000000200005841610ffff1ffff806441610 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } calling cycle -instret:6569 PC:0x1ffff000000000000000000008000059a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 10008 -instret:6570 PC:0x1ffff000000000000000000008000059e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10008 calling cycle -instret:6571 PC:0x1ffff00000000000000000000800005a2 instr:0x0d6080e7 iType:Jr [doCommitNormalInst [0]] 10009 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 100120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6d <= 00000000200003d0000000001fffff44000000 - 100130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005a6 o: 'h00000000800005a6 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 100130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 00000000200003dc000000001fffff44000000 - 100140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 100140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 100140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6572 PC:0x1ffff0000000000000000000080000674 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 10014 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 100150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001610 o: 'h0000000000000000 b: 'h0000000080001610 t: 'h00000000080001910 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: True, potentialCapLoad: True } -L1 TLB inc - 100150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 100150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6573 PC:0x1ffff0000000000000000000080000676 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10015 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8676 } - 100160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 100160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 100160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -instret:6574 PC:0x1ffff0000000000000000000080000678 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 10016 -instret:6575 PC:0x1ffff000000000000000000008000067a instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 10016 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 100170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8680 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: True, data: } } - 100170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } - 100170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6576 PC:0x1ffff000000000000000000008000067c instr:0xfea44023 iType:St [doCommitNormalInst [0]] 10017 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 00000000200001a3800000001fffff44000000 - 100180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8678 } - 100180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100180 : [doRespLdForward] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } -[RFile] wr_ 3: r 47 <= 40000000200005841610ffff1ffff806441610 - 100180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 100180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 00000000200003c4000000001fffff44000000 -[RFile] wr_ 1: r 76 <= 00000000200001a5800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 100190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 100190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 100190 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 100190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 100190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 100200 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000020000402000000001fffff44000000 - 100200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - 100200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 100200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6577 PC:0x1ffff0000000000000000000080000680 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 10020 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 0000000020000584000000001fffff44000000 -[RFile] wr_ 1: r 44 <= 00000000200003d0000000001fffff44000000 - 100210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h867c } - 100210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 100210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h03f, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 100220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - 100220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } - 100220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 100220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6578 PC:0x1ffff0000000000000000000080000684 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 10022 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 100230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6579 PC:0x1ffff0000000000000000000080000686 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10023 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 100240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8686 } - 100240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 100250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100250 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000020000402000000001fffff44000000 - 100250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - 100250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h01f, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h070 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000020040232800000001fffff44000000 - 100260 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000020000402000000001fffff44000000 - 100260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000fa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000020040402000000001fffff44000000 - 100270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 100270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000020000400000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } - 100280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 100290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 100300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 100300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h88da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h008 } - 100310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100310 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000020040402000000001fffff44000000 - 100310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h008 } - 100320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100320 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020040402000000001fffff44000000 - 100320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 100320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100330 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000020000400000000001fffff44000000 - 100330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 100330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100340 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 100340 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h88de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 100340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100350 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h008 } - 100350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h89e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 100350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 100350 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 100350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h008 } - 100360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100360 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000400000000001fffff44000000 - 100360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 100360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 100360 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 100360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 100360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h008 } - 100370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100370 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000020000400000000001fffff44000000 - 100370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 100370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 100380 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000020000400000000001fffff44000000 - 100380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001008 -After delta: vaddr = 0x80001008 - 100380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - 100400 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +instret:6628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58164 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58173 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58182 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58191 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle calling cycle +instret:6632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58200 calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 100480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 00000000200001a3800000001fffff44000000 - 100490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 100490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 00000000200001a5800000001fffff44000000 - 100500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 100500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 100500 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } - 100500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 100500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7d <= 00000000200003c4000000001fffff44000000 - 100510 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000020000584000000001fffff44000000 - 100510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 100510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 44 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 100520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 100520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h00f, localHist: 'h0aa, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 100530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 100530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6580 PC:0x1ffff000000000000000000008000068a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 10053 -instret:6581 PC:0x1ffff000000000000000000008000068e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10053 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 100540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6582 PC:0x1ffff0000000000000000000080000692 instr:0x214080e7 iType:Jr [doCommitNormalInst [0]] 10054 -instret:6583 PC:0x1ffff00000000000000000000800008a2 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 10054 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 100550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 100550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6584 PC:0x1ffff00000000000000000000800008a4 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10055 -instret:6585 PC:0x1ffff00000000000000000000800008a6 instr:0x0000f022 iType:St [doCommitNormalInst [1]] 10055 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a4 } - 100560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100560 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000020000584000000001fffff44000000 - 100560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -instret:6586 PC:0x1ffff00000000000000000000800008a8 instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 10056 -instret:6587 PC:0x1ffff00000000000000000000800008aa instr:0xfea43423 iType:St [doCommitNormalInst [1]] 10056 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h007, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h071 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6e <= 0000000020040232800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100570 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000020000584000000001fffff44000000 - 100570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } - 100570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000fa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5b <= 0000000020040402000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a6 } - 100580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 100580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -instret:6588 PC:0x1ffff00000000000000000000800008ae instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10058 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000020000582000000001fffff44000000 - 100590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } - 100590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } - 100590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88aa } - 100600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -instret:6589 PC:0x1ffff00000000000000000000800008b2 instr:0x00001561 iType:Alu [doCommitNormalInst [0]] 10060 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 100610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } - 100610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h88da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h018 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } - 100610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h018 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 -instret:6590 PC:0x1ffff00000000000000000000800008b4 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10061 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h018, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88b4 } - 100620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100620 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 0000000020040402000000001fffff44000000 - 100620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h008 } - 100630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100630 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020040402000000001fffff44000000 - 100630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } - 100630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 100630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6591 PC:0x1ffff00000000000000000000800008b8 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10063 -instret:6592 PC:0x1ffff00000000000000000000800008bc instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 10063 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h008, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100640 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7e <= 0000000020000582000000001fffff44000000 - 100640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 100640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6593 PC:0x1ffff00000000000000000000800008be instr:0x00c0006f iType:J [doCommitNormalInst [0]] 10064 -instret:6594 PC:0x1ffff00000000000000000000800008ca instr:0x00100517 iType:Auipc [doCommitNormalInst [1]] 10064 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100650 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 100650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h88de } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 100650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } -instret:6595 PC:0x1ffff00000000000000000000800008ce instr:0x73e50513 iType:Alu [doCommitNormalInst [0]] 10065 -instret:6596 PC:0x1ffff00000000000000000000800008d2 instr:0xfea43023 iType:St [doCommitNormalInst [1]] 10065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100660 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h008 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88d2 } - 100660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h89e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 100660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88de } - 100660 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 100660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 100660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } -instret:6597 PC:0x1ffff00000000000000000000800008d6 instr:0x0040006f iType:J [doCommitNormalInst [0]] 10066 -instret:6598 PC:0x1ffff00000000000000000000800008da instr:0xfe043503 iType:Ld [doCommitNormalInst [1]] 10066 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h009, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h008 } - 100670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h89e8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100670 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000400000000001fffff44000000 - 100670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 100670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e0 } - 100670 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 100670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h009 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 100670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h009, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00b, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h008 } - 100680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h89ec } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 100680 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000020000400000000001fffff44000000 - 100680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } - 100680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89e8 } - 100680 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 100680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 100680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h00a, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h008 } - 100690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h89f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100690 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000020000582000000001fffff44000000 - 100690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } - 100690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88d2 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h008 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001610 -After delta: vaddr = 0x80001610 - 100690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h008, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } -instret:6599 PC:0x1ffff00000000000000000000800008de instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 10069 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff00000000000000000000800008e6; 'h3; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } - 100700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h008 } - 100700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h89f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100700 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000020040402000000001fffff44000000 - 100700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h008 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001610, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 100700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 100700 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 100700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } calling cycle -[ROB incorrectSpec] 'h3 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 100720 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 100720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 100720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 100720 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 100720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6600 PC:0x1ffff00000000000000000000800008e0 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 10072 +instret:6633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58209 calling cycle - 100730 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 100760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 100770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 100780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } - 100790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h88ea } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ea } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 100800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ea } - 100800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ea } - 100800 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 100800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 -instret:6601 PC:0x1ffff00000000000000000000800008e6 instr:0x0040006f iType:J [doCommitNormalInst [0]] 10080 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 100810 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020040402000000001fffff44000000 - 100810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 100820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h88f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80101008 -After delta: vaddr = 0x80101008 - 100820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } calling cycle - 100830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080101008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } - 100830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } - 100830 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 100830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 -instret:6602 PC:0x1ffff00000000000000000000800008ea instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 10083 -calling cycle - 100840 : [doFinishMem] DTlbResp { resp: <'h0000000080101008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080101008, check_high: 'h00000000080101010, check_inclusive: True } }, specBits: 'h000 } - 100840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080101008, shiftedBE: tagged DataMemAccess , pcHash: 'h88ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100840 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000020000584000000001fffff44000000 - 100840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 100840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ee } -calling cycle - 100850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 100850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h88fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040080, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ee } - 100850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080101008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88ee } - 100850 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 100850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001610 -After delta: vaddr = 0x80001610 - 100850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } -calling cycle - 100860 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000020000400000000001fffff44000000 - 100860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001610, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } - 100860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } - 100860 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 100860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 100860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080101008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100870 : [doFinishMem] DTlbResp { resp: <'h0000000080001610,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001610, check_high: 'h00000000080001618, check_inclusive: True } }, specBits: 'h000 } - 100870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080001610, shiftedBE: tagged DataMemAccess , pcHash: 'h88f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 100870 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000582000000001fffff44000000 - 100870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 100870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080001610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } calling cycle - 100880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 100880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080001610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } - 100880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080001610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } - 100880 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 100880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6603 PC:0x1ffff00000000000000000000800008ee instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 10088 +instret:6634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58218 calling cycle - 100890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 100890 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 1000000000000000040000001fffff44000000 calling cycle -instret:6604 PC:0x1ffff00000000000000000000800008f0 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 10090 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88f0 } - 100910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f0 } calling cycle -[RFile] wr_ 1: r 43 <= 1000000020000584040000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080001610, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 100920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 100920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f0 } - 100920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 100920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 100920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle calling cycle calling cycle +instret:6635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58227 calling cycle calling cycle calling cycle @@ -99382,6 +71888,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58236 calling cycle calling cycle calling cycle @@ -99391,6 +71898,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58245 calling cycle calling cycle calling cycle @@ -99400,6 +71908,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58254 calling cycle calling cycle calling cycle @@ -99408,101 +71917,28 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 101330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +instret:6639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58263 calling cycle - 101340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h803, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h080 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 101350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000062 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 101360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 101360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h88f4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 101360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } calling cycle - 101370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 101370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } - 101370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 101370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f4 } - 101370 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 101370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 101380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 101380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h88fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101380 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000020000400000000001fffff44000000 - 101380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 101380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 101390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 101390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } - 101390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 101390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88fc } - 101390 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 101390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 101390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001000 -After delta: vaddr = 0x80001000 calling cycle - 101400 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000582000000001fffff44000000 - 101400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6605 PC:0x1ffff00000000000000000000800008f4 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 10140 calling cycle - 101410 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } - 101410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess , pcHash: 'h88f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } calling cycle - 101420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 101420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } - 101420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 101420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88f8 } - 101420 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } - 101420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle - 101430 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000182000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080001000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:6640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58272 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:6606 PC:0x1ffff00000000000000000000800008f8 instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 10145 calling cycle -[RFile] wr_ 1: r 43 <= 0000000020000582000000001fffff44000000 calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080000908; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:6607 PC:0x1ffff00000000000000000000800008fa instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 10147 -instret:6608 PC:0x1ffff00000000000000000000800008fc instr:0xfd843583 iType:Ld [doCommitNormalInst [1]] 10147 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:6609 PC:0x1ffff0000000000000000000080000900 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 10149 calling cycle calling cycle calling cycle calling cycle +instret:6641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58281 calling cycle calling cycle calling cycle @@ -99512,6 +71948,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58290 calling cycle calling cycle calling cycle @@ -99521,6 +71958,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58299 calling cycle calling cycle calling cycle @@ -99530,6 +71968,7 @@ calling cycle calling cycle calling cycle calling cycle +instret:6644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58308 calling cycle calling cycle calling cycle @@ -99539,600 +71978,37 @@ calling cycle calling cycle calling cycle calling cycle +instret:6645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58317 calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 101910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 101920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 101930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 101940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h001 } - 101940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h890c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 101940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h890c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - 101950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 101950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h890c } - 101950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 101950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h890c } - 101950 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 101950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6610 PC:0x1ffff0000000000000000000080000908 instr:0x0040006f iType:J [doCommitNormalInst [0]] 10195 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 101960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 101960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8912 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101960 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000020000582000000001fffff44000000 - 101960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 101960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8912 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc01, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h092 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 101970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 101970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8912 } - 101970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 101970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8912 } - 101970 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } - 101970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 101970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001608 -After delta: vaddr = 0x80001608 - 101970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 101980 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 50 <= 0000000020000400000000001fffff44000000 - 101980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001608, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f10 -After delta: vaddr = 0x80000f10 - 101980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6611 PC:0x1ffff000000000000000000008000090c instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 10198 -calling cycle - 101990 : [doFinishMem] DTlbResp { resp: <'h0000000080001608,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001608 o: 'h0000000080001608 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001608, check_high: 'h00000000080001610, check_inclusive: True } }, specBits: 'h000 } - 101990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080001608, shiftedBE: tagged DataMemAccess , pcHash: 'h8910 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 101990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 101990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001000 -After delta: vaddr = 0x80001000 - 101990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080001608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8910 } -calling cycle - 102000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f18, check_inclusive: True } }, specBits: 'h000 } - 102000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h891c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080001608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8910 } - 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080001608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8910 } - 102000 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } - 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000094 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102010 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } - 102010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess , pcHash: 'h8916 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102010 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 70 <= 00000000000000c2000000001fffff44000000 - 102010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891c } - 102010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891c } - 102010 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 102010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8916 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080001608, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102020 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 - 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8916 } - 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8916 } - 102020 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000008, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102030 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000182000000001fffff44000000 - 102030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001008 -After delta: vaddr = 0x80001008 -instret:6612 PC:0x1ffff0000000000000000000080000910 instr:0x00006110 iType:Ld [doCommitNormalInst [0]] 10203 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080001000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6613 PC:0x1ffff0000000000000000000080000912 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 10204 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102050 : [doFinishMem] DTlbResp { resp: <'h0000000080001008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001008, check_high: 'h00000000080001010, check_inclusive: True } }, specBits: 'h000 } - 102050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001008, shiftedBE: tagged DataMemAccess , pcHash: 'h8920 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001000 -After delta: vaddr = 0x80001000 - 102050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8920 } -instret:6614 PC:0x1ffff0000000000000000000080000916 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 10205 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000000000244000000001fffff44000000 - 102060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000910 o: 'h0000000000000910 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8920 } - 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8920 } - 102060 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 102060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102070 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } - 102070 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000000000000001fffff44000000 - 102070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 102070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6615 PC:0x1ffff0000000000000000000080000918 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 10207 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } - 102080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h89f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 102080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } -instret:6616 PC:0x1ffff000000000000000000008000091a instr:0x0000e188 iType:St [doCommitNormalInst [0]] 10208 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5f <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h001 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h891a } - 102090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h89f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 102090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 102090 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 102090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 102090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000d6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080001008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h003 } - 102100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102100 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 00000000200001a5800000001fffff44000000 - 102100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 102100 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -instret:6617 PC:0x1ffff000000000000000000008000091c instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 10210 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 00000000200003dc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h002 } - 102110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8698 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102110 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 00000000200003dc000000001fffff44000000 - 102110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102110 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 102110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } -instret:6618 PC:0x1ffff0000000000000000000080000920 instr:0x00006508 iType:Ld [doCommitNormalInst [0]] 10211 -instret:6619 PC:0x1ffff0000000000000000000080000922 instr:0x0000e119 iType:Br [doCommitNormalInst [1]] 10211 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102120 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000020000169800000001fffff44000000 - 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 102120 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891a } -instret:6620 PC:0x1ffff0000000000000000000080000924 instr:0x03e0006f iType:J [doCommitNormalInst [0]] 10212 -instret:6621 PC:0x1ffff0000000000000000000080000962 instr:0x0940006f iType:J [doCommitNormalInst [1]] 10212 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000020000167800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102130 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000020000400000000001fffff44000000 - 102130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891a } - 102130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h891a } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h00e } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 102130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6622 PC:0x1ffff00000000000000000000800009f6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 10213 -instret:6623 PC:0x1ffff00000000000000000000800009f8 instr:0x00007402 iType:Ld [doCommitNormalInst [1]] 10213 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h00e, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 00000000200003d0000000001fffff44000000 -[RFile] wr_ 1: r 66 <= 0000000020000169800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005a6 o: 'h00000000800005a6 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h00c } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 102140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6624 PC:0x1ffff00000000000000000000800009fa instr:0x00006145 iType:Alu [doCommitNormalInst [0]] 10214 -instret:6625 PC:0x1ffff00000000000000000000800009fc instr:0x00008082 iType:Jr [doCommitNormalInst [1]] 10214 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h00c, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 00000000200003dc000000001fffff44000000 -[ALU redirect - 1] 'h1ffff00000000000000000000800005a6; 'h2; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } - 102150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h004 } - 102150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 102150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 102150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6626 PC:0x1ffff0000000000000000000080000696 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 10215 -instret:6627 PC:0x1ffff0000000000000000000080000698 instr:0x00007402 iType:Ld [doCommitNormalInst [1]] 10215 calling cycle -[ROB incorrectSpec] 'h2 ; InstTag { way: 'h0, ptr: 'h0c, t: 'h18 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; +instret:6646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58326 calling cycle -instret:6628 PC:0x1ffff000000000000000000008000069a instr:0x00006145 iType:Alu [doCommitNormalInst [0]] 10217 -instret:6629 PC:0x1ffff000000000000000000008000069c instr:0x00008082 iType:Jr [doCommitNormalInst [1]] 10217 calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff90, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff90, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000ca }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff90, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 calling cycle - 102240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff90, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc calling cycle -[RFile] wr_ 1: r 57 <= 000000002000016a800000001fffff44000000 - 102250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 102250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h85a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58335 calling cycle -[RFile] wr_ 1: r 66 <= 000000002000016c800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000674; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } - 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } - 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } - 102260 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 102280 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000000000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } calling cycle -instret:6630 PC:0x1ffff00000000000000000000800005a6 instr:0xf904250f iType:Ld [doCommitNormalInst [0]] 10230 -instret:6631 PC:0x1ffff00000000000000000000800005aa instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10230 calling cycle -instret:6632 PC:0x1ffff00000000000000000000800005ae instr:0x0ca080e7 iType:Jr [doCommitNormalInst [0]] 10231 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 102340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 00000000200003d0000000001fffff44000000 - 102350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005b2 o: 'h00000000800005b2 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 102350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 00000000200003dc000000001fffff44000000 - 102360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 102360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 102360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6633 PC:0x1ffff0000000000000000000080000674 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 10236 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 102370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 102370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 102370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6634 PC:0x1ffff0000000000000000000080000676 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10237 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8676 } - 102380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 102380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 102380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -instret:6635 PC:0x1ffff0000000000000000000080000678 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 10238 -instret:6636 PC:0x1ffff000000000000000000008000067a instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 10238 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 102390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8680 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 102390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } - 102390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6637 PC:0x1ffff000000000000000000008000067c instr:0xfea44023 iType:St [doCommitNormalInst [0]] 10239 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 00000000200001a3800000001fffff44000000 - 102400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8678 } - 102400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102400 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 - 102400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 102400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 00000000200003c4000000001fffff44000000 -[RFile] wr_ 1: r 72 <= 00000000200001a5800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 102410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 102410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 102410 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 102410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 102410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 102420 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000020000584000000001fffff44000000 - 102420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 102420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6638 PC:0x1ffff0000000000000000000080000680 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 10242 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 6d <= 00000000200003d0000000001fffff44000000 - 102430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h867c } - 102430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 102430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h600, localHist: 'h055, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 102440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001610 o: 'h0000000080001610 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 102440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6639 PC:0x1ffff0000000000000000000080000684 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 10244 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 102450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6640 PC:0x1ffff0000000000000000000080000686 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10245 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 102460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8686 } - 102460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 102460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 102470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 102470 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000020000584000000001fffff44000000 - 102470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - 102470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h300, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h070 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000020040232800000001fffff44000000 - 102480 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000020000584000000001fffff44000000 - 102480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 102480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58344 calling cycle calling cycle calling cycle @@ -100140,1192 +72016,123 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +instret:6649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58353 calling cycle - 102580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 00000000200001a3800000001fffff44000000 - 102590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 102590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 00000000200001a5800000001fffff44000000 - 102600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 102600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 102600 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } } - 102600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 102600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7f <= 00000000200003c4000000001fffff44000000 - 102610 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000000000000001fffff44000000 - 102610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 102610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6d <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 102620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 102620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h180, localHist: 'h055, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 102630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 102630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6641 PC:0x1ffff000000000000000000008000068a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 10263 -instret:6642 PC:0x1ffff000000000000000000008000068e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10263 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 102640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6643 PC:0x1ffff0000000000000000000080000692 instr:0x214080e7 iType:Jr [doCommitNormalInst [0]] 10264 -instret:6644 PC:0x1ffff00000000000000000000800008a2 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 10264 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 102650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 102650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 102650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6645 PC:0x1ffff00000000000000000000800008a4 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10265 -instret:6646 PC:0x1ffff00000000000000000000800008a6 instr:0x0000f022 iType:St [doCommitNormalInst [1]] 10265 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a4 } - 102660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 102660 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000 - 102660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -instret:6647 PC:0x1ffff00000000000000000000800008a8 instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 10266 -instret:6648 PC:0x1ffff00000000000000000000800008aa instr:0xfea43423 iType:St [doCommitNormalInst [1]] 10266 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h0c0, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h071 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 63 <= 0000000020040232800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102670 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6f <= 0000000000000000000000001fffff44000000 - 102670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } - 102670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 102670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000fa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 0000000020040402000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a6 } - 102680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080101008 o: 'h0000000080101008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 102680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -instret:6649 PC:0x1ffff00000000000000000000800008ae instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10268 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4f <= 3ffffffffffffffe0fff00001fffff44000000 - 102690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } - 102690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfffffffffffffff8 o: 'hfffffffffffffff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } - 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 102690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 0] 'h1ffff00000000000000000000800008c2; 'h0; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } - 102700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88aa } - 102700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h01d } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 102700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h01d, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -instret:6650 PC:0x1ffff00000000000000000000800008b2 instr:0x00001561 iType:Alu [doCommitNormalInst [0]] 10270 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 102720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } - 102720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6651 PC:0x1ffff00000000000000000000800008b4 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10272 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88b4 } - 102730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } calling cycle - 102740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } - 102740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 102740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6652 PC:0x1ffff00000000000000000000800008b8 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10274 -instret:6653 PC:0x1ffff00000000000000000000800008bc instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 10274 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000130 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle +instret:6650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58362 calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6654 PC:0x1ffff00000000000000000000800008c2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 10281 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 102820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6655 PC:0x1ffff00000000000000000000800008c6 instr:0x1300006f iType:J [doCommitNormalInst [0]] 10282 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 102830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 102840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 102840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h89f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 102840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 102840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 68 <= 00000000200003d0000000001fffff44000000 - 102850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 102850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h89f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 102850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 102850 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 102850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 102850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } -calling cycle - 102860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 } - 102860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102860 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 00000000200001a5800000001fffff44000000 - 102860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 102860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 102860 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 102860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -calling cycle -[RFile] wr_ 0: r 5b <= 00000000200003dc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h001 } - 102870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8698 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102870 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 00000000200003dc000000001fffff44000000 - 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102870 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102880 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000016c800000001fffff44000000 - 102880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 102880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 102880 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 102880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 102880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6656 PC:0x1ffff00000000000000000000800009f6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 10288 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102890 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000020000400000000001fffff44000000 - 102890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 102890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6657 PC:0x1ffff00000000000000000000800009f8 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 10289 -instret:6658 PC:0x1ffff00000000000000000000800009fa instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 10289 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 102900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:6659 PC:0x1ffff00000000000000000000800009fc instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 10290 -instret:6660 PC:0x1ffff0000000000000000000080000696 instr:0x000070a2 iType:Ld [doCommitNormalInst [1]] 10290 -calling cycle -[ALU redirect - 0] 'h1ffff00000000000000000000800005b2; 'h1; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 102910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h002 } - 102910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 102910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 102910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -instret:6661 PC:0x1ffff0000000000000000000080000698 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 10291 -instret:6662 PC:0x1ffff000000000000000000008000069a instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 10291 calling cycle -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 102930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 102930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 102930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 102930 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 102930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6663 PC:0x1ffff000000000000000000008000069c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 10293 calling cycle - 102940 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff80, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58371 calling cycle - 102970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff80, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 102980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff80, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 calling cycle - 102990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff80, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc calling cycle -[RFile] wr_ 1: r 7c <= 000000002000016d800000001fffff44000000 - 103000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 103000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h85b2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 0a <= 000000002000016f800000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000674; 'h0; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } - 103010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b2 } - 103010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b2 } - 103010 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } - 103010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0c, t: 'h19 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle - 103030 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000000000000001fffff44000000 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } calling cycle -instret:6664 PC:0x1ffff00000000000000000000800005b2 instr:0xf804250f iType:Ld [doCommitNormalInst [0]] 10305 -instret:6665 PC:0x1ffff00000000000000000000800005b6 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10305 +instret:6652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58380 calling cycle -instret:6666 PC:0x1ffff00000000000000000000800005ba instr:0x0be080e7 iType:Jr [doCommitNormalInst [0]] 10306 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 103090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 42 <= 00000000200003d0000000001fffff44000000 - 103100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800005be o: 'h00000000800005be b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 103100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 00000000200003dc000000001fffff44000000 - 103110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } - 103110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 103110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6667 PC:0x1ffff0000000000000000000080000674 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 10311 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h000 } - 103120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 103120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f50 -After delta: vaddr = 0x80000f50 - 103120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6668 PC:0x1ffff0000000000000000000080000676 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10312 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8676 } - 103130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f50, write: False, capStore: False, potentialCapLoad: True } -L1 TLB inc - 103130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 103130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -instret:6669 PC:0x1ffff0000000000000000000080000678 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 10313 -instret:6670 PC:0x1ffff000000000000000000008000067a instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 10313 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f50,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f50, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 103140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f50, shiftedBE: tagged DataMemAccess , pcHash: 'h8680 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 103140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } - 103140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8676 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6671 PC:0x1ffff000000000000000000008000067c instr:0xfea44023 iType:St [doCommitNormalInst [0]] 10314 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 00000000200001a3800000001fffff44000000 - 103150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8678 } - 103150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103150 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000 - 103150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 103150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 00000000200003c4000000001fffff44000000 -[RFile] wr_ 1: r 54 <= 00000000200001a5800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } - 103160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 103160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 103160 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 103160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 103160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 103170 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000000000001fffff44000000 - 103170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } - 103170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8678 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - 103170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6672 PC:0x1ffff0000000000000000000080000680 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 10317 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 05 <= 00000000200003d0000000001fffff44000000 - 103180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f50, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h867c } - 103180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 103180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h8c0, localHist: 'h22a, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 103190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } - 103190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h867c } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 103190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6673 PC:0x1ffff0000000000000000000080000684 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 10319 -calling cycle - 103200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 103200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6674 PC:0x1ffff0000000000000000000080000686 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10320 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 103210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8686 } - 103210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 103210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 103220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 103220 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 103220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } - 103220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8686 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103230 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 - 103230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 103240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 3ffffffffffffffe0fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfffffffffffffff8 o: 'hfffffffffffffff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h460, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h070 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[ALU redirect - 0] 'h1ffff00000000000000000000800008c2; 'h0; InstTag { way: 'h0, ptr: 'h17, t: 'h2e } - 103260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } - 103260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 103260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h17, t: 'h2e } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle calling cycle calling cycle +instret:6653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58389 calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f48 -After delta: vaddr = 0x80000f48 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 103380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 08 <= 00000000200001a3800000001fffff44000000 - 103390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } - 103390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h868a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 54 <= 00000000200001a5800000001fffff44000000 - 103400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 103400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h868a } - 103400 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 103400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 103400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 00000000200003c4000000001fffff44000000 - 103410 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000000000000001fffff44000000 - 103410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000696 o: 'h0000000080000696 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 103410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 00000000200003d0000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } - 103420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 103420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'hc60, localHist: 'h315, globalTaken: True, localTaken: False, pcIndex: 'h05e }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 103430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 - 103430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6675 PC:0x1ffff000000000000000000008000068a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 10343 -instret:6676 PC:0x1ffff000000000000000000008000068e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 10343 -calling cycle - 103440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 103440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f28 -After delta: vaddr = 0x80000f28 -instret:6677 PC:0x1ffff0000000000000000000080000692 instr:0x214080e7 iType:Jr [doCommitNormalInst [0]] 10344 -instret:6678 PC:0x1ffff00000000000000000000800008a2 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 10344 -calling cycle - 103450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } - 103450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88ae } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 103450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:6679 PC:0x1ffff00000000000000000000800008a4 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 10345 -instret:6680 PC:0x1ffff00000000000000000000800008a6 instr:0x0000f022 iType:St [doCommitNormalInst [1]] 10345 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a4 } - 103460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h88b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 103460 : [doRespLdForward] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 103460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -instret:6681 PC:0x1ffff00000000000000000000800008a8 instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 10346 -instret:6682 PC:0x1ffff00000000000000000000800008aa instr:0xfea43423 iType:St [doCommitNormalInst [1]] 10346 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000073e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00100000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103470 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 - 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } - 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88a6 } - 103480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f18 -After delta: vaddr = 0x80000f18 - 103480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -instret:6683 PC:0x1ffff00000000000000000000800008ae instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10348 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 3ffffffffffffffe0fff00001fffff44000000 - 103490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfffffffffffffff8 o: 'hfffffffffffffff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } - 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88a6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h630, localHist: 'h155, globalTaken: True, localTaken: False, pcIndex: 'h070 }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[ALU redirect - 0] 'h1ffff00000000000000000000800008c2; 'h0; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } - 103500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88aa } - 103500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f20 -After delta: vaddr = 0x80000f20 - 103500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -instret:6684 PC:0x1ffff00000000000000000000800008b2 instr:0x00001561 iType:Alu [doCommitNormalInst [0]] 10350 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle - 103520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } - 103520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88aa } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6685 PC:0x1ffff00000000000000000000800008b4 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 10352 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h88b4 } - 103530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } -calling cycle - 103540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } - 103540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h88b4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 103540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6686 PC:0x1ffff00000000000000000000800008b8 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 10354 -instret:6687 PC:0x1ffff00000000000000000000800008bc instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 10354 -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000130 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f38 -After delta: vaddr = 0x80000f38 - 103580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f30 -After delta: vaddr = 0x80000f30 - 103590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h002 } - 103600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h89f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f68 -After delta: vaddr = 0x80000f68 - 103600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 103600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } -instret:6688 PC:0x1ffff00000000000000000000800008c2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 10360 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 00000000200003d0000000001fffff44000000 - 103610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } - 103610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h89f8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 103610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f6 } - 103610 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 103610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f60 -After delta: vaddr = 0x80000f60 - 103610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } -instret:6689 PC:0x1ffff00000000000000000000800008c6 instr:0x1300006f iType:J [doCommitNormalInst [0]] 10361 -calling cycle - 103620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h004 } - 103620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103620 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 00000000200001a5800000001fffff44000000 - 103620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 103620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h89f8 } - 103620 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 103620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -calling cycle -[RFile] wr_ 1: r 57 <= 00000000200003dc000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f68, check_inclusive: True } }, specBits: 'h004 } - 103630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h8698 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103630 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 00000000200003dc000000001fffff44000000 - 103630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 103630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 103630 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 103630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103640 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 000000002000016f800000001fffff44000000 - 103640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 103640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8698 } - 103640 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 103640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6690 PC:0x1ffff00000000000000000000800009f6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 10364 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103650 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000020000400000000001fffff44000000 - 103650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 103650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6691 PC:0x1ffff00000000000000000000800009f8 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 10365 -instret:6692 PC:0x1ffff00000000000000000000800009fa instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 10365 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:6693 PC:0x1ffff00000000000000000000800009fc instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 10366 -instret:6694 PC:0x1ffff0000000000000000000080000696 instr:0x000070a2 iType:Ld [doCommitNormalInst [1]] 10366 -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800005be; 'h0; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } - 103670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } - 103670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8696 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } -instret:6695 PC:0x1ffff0000000000000000000080000698 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 10367 -instret:6696 PC:0x1ffff000000000000000000008000069a instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 10367 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0b, t: 'h16 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +instret:6654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58398 calling cycle - 103690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 103690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8696 } - 103690 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 103690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6697 PC:0x1ffff000000000000000000008000069c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 10369 calling cycle - 103700 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 103750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 103750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000000000000000000001fffff44000000 - 103760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 calling cycle - 103770 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 103770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -instret:6698 PC:0x1ffff00000000000000000000800005be instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 10377 -calling cycle -[RFile] wr_ 0: r 73 <= 0000000020000400000000001fffff44000000 - 103780 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } - 103780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h85c2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 103780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 103780 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 103780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103790 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000020000006000000001fffff44000000 - 103790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 103790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c2 } - 103790 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 103790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 103790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000088, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000090 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103800 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000000000000000000001fffff44000000 - 103800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000088, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001088 -After delta: vaddr = 0x80001088 - 103800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000080, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff80, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 103810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000088, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001088 o: 'h0000000080001088 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001088, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000080, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80001080 -After delta: vaddr = 0x80001080 -instret:6699 PC:0x1ffff00000000000000000000800005c0 instr:0x000060aa iType:Ld [doCommitNormalInst [0]] 10381 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 0000000000000000000000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } - 103820 : [doFinishMem] DTlbResp { resp: <'h0000000080001088,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001088 o: 'h0000000080001088 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001088, check_high: 'h00000000080001090, check_inclusive: True } }, specBits: 'h001 } - 103820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080001088, shiftedBE: tagged DataMemAccess , pcHash: 'h85c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 103820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000080, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001080 o: 'h0000000080001080 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001080, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080001088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } -instret:6700 PC:0x1ffff00000000000000000000800005c2 instr:0x0000640a iType:Ld [doCommitNormalInst [0]] 10382 -instret:6701 PC:0x1ffff00000000000000000000800005c4 instr:0x00006149 iType:Alu [doCommitNormalInst [1]] 10382 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +instret:6655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58407 calling cycle - 103840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 103840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080001088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 103840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 103840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080001088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85c0 } - 103840 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 103840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:6702 PC:0x1ffff00000000000000000000800005c6 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 10384 calling cycle - 103850 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 103910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 75 <= 0000000000000000000000001fffff44000000 - 103920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x00000000 -After delta: vaddr = 0x00000000 - 103920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000000000000400000001fffff44000000 - 103930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff8 -After delta: vaddr = 0x80000ff8 - 103930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6703 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 10393 -instret:6704 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 10393 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 00000000200003f0000000001fffff44000000 - 103940 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } - 103940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000ff0 -After delta: vaddr = 0x80000ff0 - 103940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:6705 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 10394 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000020000400000000001fffff44000000 - 103950 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 103950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe0 -After delta: vaddr = 0x80000fe0 - 103950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103960 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } - 103960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: True, capStore: False, potentialCapLoad: True } -L1 TLB inc - 103960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fdc -After delta: vaddr = 0x80000fdc - 103960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 103970 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe0, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } - 103970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fdc o: 'h0000000080000fdc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fdc, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd8 -After delta: vaddr = 0x80000fd8 - 103970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'he30, localHist: 'h1ff, globalTaken: True, localTaken: True, pcIndex: 'h024 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000000000000001fffff44000000 - 103980 : [doFinishMem] DTlbResp { resp: <'h0000000080000fdc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fdc o: 'h0000000080000fdc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fdc, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } - 103980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000308 o: 'h0000000000000308 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 103980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:6656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58416 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58425 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58434 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58443 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +instret:6660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58452 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle calling cycle - 103990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fdc, check_inclusive: True } }, specBits: 'h000 } - 103990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 103990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fd0 -After delta: vaddr = 0x80000fd0 - 103990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -10400: mmioPlatform.rl_tohost: 0x1 (= 1) -PASS